gallium: Use enum pipe_shader_type in bind_sampler_states() (v2)
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.h
1 #ifndef __NV50_SCREEN_H__
2 #define __NV50_SCREEN_H__
3
4 #include "nouveau_screen.h"
5 #include "nouveau_fence.h"
6 #include "nouveau_mm.h"
7 #include "nouveau_heap.h"
8
9 #include "nv50/nv50_winsys.h"
10 #include "nv50/nv50_stateobj.h"
11
12 #define NV50_TIC_MAX_ENTRIES 2048
13 #define NV50_TSC_MAX_ENTRIES 2048
14
15 /* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
16 #define NV50_MAX_PIPE_CONSTBUFS 14
17
18 struct nv50_context;
19
20 #define NV50_CODE_BO_SIZE_LOG2 19
21
22 #define NV50_SCREEN_RESIDENT_BO_COUNT 5
23
24 #define NV50_MAX_VIEWPORTS 16
25
26 #define NV50_MAX_WINDOW_RECTANGLES 8
27
28 #define NV50_MAX_GLOBALS 16
29
30 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
31
32 struct nv50_blitter;
33
34 struct nv50_graph_state {
35 uint32_t instance_elts; /* bitmask of per-instance elements */
36 uint32_t instance_base;
37 uint32_t interpolant_ctrl;
38 uint32_t semantic_color;
39 uint32_t semantic_psize;
40 int32_t index_bias;
41 uint32_t clip_mode;
42 bool uniform_buffer_bound[3];
43 bool prim_restart;
44 bool point_sprite;
45 bool rt_serialize;
46 bool flushed;
47 bool rasterizer_discard;
48 uint8_t tls_required;
49 bool new_tls_space;
50 uint8_t num_vtxbufs;
51 uint8_t num_vtxelts;
52 uint8_t num_textures[3];
53 uint8_t num_samplers[3];
54 uint8_t prim_size;
55 uint16_t scissor;
56 bool seamless_cube_map;
57 };
58
59 struct nv50_screen {
60 struct nouveau_screen base;
61
62 struct nv50_context *cur_ctx;
63 struct nv50_graph_state save_state;
64
65 int num_occlusion_queries_active;
66
67 struct nouveau_bo *code;
68 struct nouveau_bo *uniforms;
69 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
70 struct nouveau_bo *stack_bo;
71 struct nouveau_bo *tls_bo;
72
73 unsigned TPs;
74 unsigned MPsInTP;
75 unsigned max_tls_space;
76 unsigned cur_tls_space;
77 unsigned mp_count;
78
79 struct nouveau_heap *vp_code_heap;
80 struct nouveau_heap *gp_code_heap;
81 struct nouveau_heap *fp_code_heap;
82
83 struct nv50_blitter *blitter;
84
85 struct {
86 void **entries;
87 int next;
88 uint32_t lock[NV50_TIC_MAX_ENTRIES / 32];
89 } tic;
90
91 struct {
92 void **entries;
93 int next;
94 uint32_t lock[NV50_TSC_MAX_ENTRIES / 32];
95 } tsc;
96
97 struct {
98 uint32_t *map;
99 struct nouveau_bo *bo;
100 } fence;
101
102 struct {
103 struct nv50_program *prog; /* compute state object to read MP counters */
104 struct nv50_hw_sm_query *mp_counter[4]; /* counter to query allocation */
105 uint8_t num_hw_sm_active;
106 } pm;
107
108 struct nouveau_object *sync;
109
110 struct nouveau_object *tesla;
111 struct nouveau_object *compute;
112 struct nouveau_object *eng2d;
113 struct nouveau_object *m2mf;
114 };
115
116 static inline struct nv50_screen *
117 nv50_screen(struct pipe_screen *screen)
118 {
119 return (struct nv50_screen *)screen;
120 }
121
122 int nv50_screen_get_driver_query_info(struct pipe_screen *, unsigned,
123 struct pipe_driver_query_info *);
124 int nv50_screen_get_driver_query_group_info(struct pipe_screen *, unsigned,
125 struct pipe_driver_query_group_info *);
126
127 bool nv50_blitter_create(struct nv50_screen *);
128 void nv50_blitter_destroy(struct nv50_screen *);
129
130 int nv50_screen_tic_alloc(struct nv50_screen *, void *);
131 int nv50_screen_tsc_alloc(struct nv50_screen *, void *);
132
133 int nv50_screen_compute_setup(struct nv50_screen *, struct nouveau_pushbuf *);
134
135 static inline void
136 nv50_resource_fence(struct nv04_resource *res, uint32_t flags)
137 {
138 struct nv50_screen *screen = nv50_screen(res->base.screen);
139
140 if (res->mm) {
141 nouveau_fence_ref(screen->base.fence.current, &res->fence);
142 if (flags & NOUVEAU_BO_WR)
143 nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
144 }
145 }
146
147 static inline void
148 nv50_resource_validate(struct nv04_resource *res, uint32_t flags)
149 {
150 if (likely(res->bo)) {
151 if (flags & NOUVEAU_BO_WR)
152 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING |
153 NOUVEAU_BUFFER_STATUS_DIRTY;
154 if (flags & NOUVEAU_BO_RD)
155 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
156
157 nv50_resource_fence(res, flags);
158 }
159 }
160
161 struct nv50_format {
162 uint32_t rt;
163 struct {
164 unsigned format:6;
165 unsigned type_r:3;
166 unsigned type_g:3;
167 unsigned type_b:3;
168 unsigned type_a:3;
169 unsigned src_x:3;
170 unsigned src_y:3;
171 unsigned src_z:3;
172 unsigned src_w:3;
173 } tic;
174 uint32_t usage;
175 };
176
177 struct nv50_vertex_format {
178 uint32_t vtx;
179 uint32_t usage;
180 };
181
182 extern const struct nv50_format nv50_format_table[];
183 extern const struct nv50_vertex_format nv50_vertex_format[];
184
185 static inline void
186 nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry *tic)
187 {
188 if (tic->id >= 0)
189 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
190 }
191
192 static inline void
193 nv50_screen_tsc_unlock(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
194 {
195 if (tsc->id >= 0)
196 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
197 }
198
199 static inline void
200 nv50_screen_tic_free(struct nv50_screen *screen, struct nv50_tic_entry *tic)
201 {
202 if (tic->id >= 0) {
203 screen->tic.entries[tic->id] = NULL;
204 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
205 }
206 }
207
208 static inline void
209 nv50_screen_tsc_free(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
210 {
211 if (tsc->id >= 0) {
212 screen->tsc.entries[tsc->id] = NULL;
213 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
214 }
215 }
216
217 extern int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space);
218
219 #endif