softpipe: Add support for reporting shader-db output.
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_screen.h
1 #ifndef __NV50_SCREEN_H__
2 #define __NV50_SCREEN_H__
3
4 #include "nouveau_screen.h"
5 #include "nouveau_fence.h"
6 #include "nouveau_mm.h"
7 #include "nouveau_heap.h"
8
9 #include "nv50/nv50_winsys.h"
10 #include "nv50/nv50_stateobj.h"
11
12 #define NV50_TIC_MAX_ENTRIES 2048
13 #define NV50_TSC_MAX_ENTRIES 2048
14
15 /* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
16 #define NV50_MAX_PIPE_CONSTBUFS 14
17
18 struct nv50_context;
19
20 #define NV50_CODE_BO_SIZE_LOG2 19
21
22 #define NV50_SCREEN_RESIDENT_BO_COUNT 5
23
24 #define NV50_MAX_VIEWPORTS 16
25
26 #define NV50_MAX_WINDOW_RECTANGLES 8
27
28 #define NV50_MAX_GLOBALS 16
29
30 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
31
32 struct nv50_blitter;
33
34 struct nv50_graph_state {
35 uint32_t instance_elts; /* bitmask of per-instance elements */
36 uint32_t instance_base;
37 uint32_t interpolant_ctrl;
38 uint32_t semantic_color;
39 uint32_t semantic_psize;
40 int32_t index_bias;
41 uint32_t clip_mode;
42 bool uniform_buffer_bound[3];
43 bool prim_restart;
44 bool point_sprite;
45 bool rt_serialize;
46 bool flushed;
47 bool rasterizer_discard;
48 uint8_t tls_required;
49 bool new_tls_space;
50 uint8_t num_vtxbufs;
51 uint8_t num_vtxelts;
52 uint8_t num_textures[3];
53 uint8_t num_samplers[3];
54 uint8_t prim_size;
55 uint16_t scissor;
56 bool seamless_cube_map;
57 bool mul_zero_wins;
58 };
59
60 struct nv50_screen {
61 struct nouveau_screen base;
62
63 struct nv50_context *cur_ctx;
64 struct nv50_graph_state save_state;
65
66 int num_occlusion_queries_active;
67
68 struct nouveau_bo *code;
69 struct nouveau_bo *uniforms;
70 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
71 struct nouveau_bo *stack_bo;
72 struct nouveau_bo *tls_bo;
73
74 unsigned TPs;
75 unsigned MPsInTP;
76 unsigned max_tls_space;
77 unsigned cur_tls_space;
78 unsigned mp_count;
79
80 struct nouveau_heap *vp_code_heap;
81 struct nouveau_heap *gp_code_heap;
82 struct nouveau_heap *fp_code_heap;
83
84 struct nv50_blitter *blitter;
85
86 struct {
87 void **entries;
88 int next;
89 uint32_t lock[NV50_TIC_MAX_ENTRIES / 32];
90 } tic;
91
92 struct {
93 void **entries;
94 int next;
95 uint32_t lock[NV50_TSC_MAX_ENTRIES / 32];
96 } tsc;
97
98 struct {
99 uint32_t *map;
100 struct nouveau_bo *bo;
101 } fence;
102
103 struct {
104 struct nv50_program *prog; /* compute state object to read MP counters */
105 struct nv50_hw_sm_query *mp_counter[4]; /* counter to query allocation */
106 uint8_t num_hw_sm_active;
107 } pm;
108
109 struct nouveau_object *sync;
110
111 struct nouveau_object *tesla;
112 struct nouveau_object *compute;
113 struct nouveau_object *eng2d;
114 struct nouveau_object *m2mf;
115 };
116
117 static inline struct nv50_screen *
118 nv50_screen(struct pipe_screen *screen)
119 {
120 return (struct nv50_screen *)screen;
121 }
122
123 int nv50_screen_get_driver_query_info(struct pipe_screen *, unsigned,
124 struct pipe_driver_query_info *);
125 int nv50_screen_get_driver_query_group_info(struct pipe_screen *, unsigned,
126 struct pipe_driver_query_group_info *);
127
128 bool nv50_blitter_create(struct nv50_screen *);
129 void nv50_blitter_destroy(struct nv50_screen *);
130
131 int nv50_screen_tic_alloc(struct nv50_screen *, void *);
132 int nv50_screen_tsc_alloc(struct nv50_screen *, void *);
133
134 int nv50_screen_compute_setup(struct nv50_screen *, struct nouveau_pushbuf *);
135
136 static inline void
137 nv50_resource_fence(struct nv04_resource *res, uint32_t flags)
138 {
139 struct nv50_screen *screen = nv50_screen(res->base.screen);
140
141 if (res->mm) {
142 nouveau_fence_ref(screen->base.fence.current, &res->fence);
143 if (flags & NOUVEAU_BO_WR)
144 nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
145 }
146 }
147
148 static inline void
149 nv50_resource_validate(struct nv04_resource *res, uint32_t flags)
150 {
151 if (likely(res->bo)) {
152 if (flags & NOUVEAU_BO_WR)
153 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING |
154 NOUVEAU_BUFFER_STATUS_DIRTY;
155 if (flags & NOUVEAU_BO_RD)
156 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
157
158 nv50_resource_fence(res, flags);
159 }
160 }
161
162 struct nv50_format {
163 uint32_t rt;
164 struct {
165 unsigned format:6;
166 unsigned type_r:3;
167 unsigned type_g:3;
168 unsigned type_b:3;
169 unsigned type_a:3;
170 unsigned src_x:3;
171 unsigned src_y:3;
172 unsigned src_z:3;
173 unsigned src_w:3;
174 } tic;
175 uint32_t usage;
176 };
177
178 struct nv50_vertex_format {
179 uint32_t vtx;
180 uint32_t usage;
181 };
182
183 extern const struct nv50_format nv50_format_table[];
184 extern const struct nv50_vertex_format nv50_vertex_format[];
185
186 static inline void
187 nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry *tic)
188 {
189 if (tic->id >= 0)
190 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
191 }
192
193 static inline void
194 nv50_screen_tsc_unlock(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
195 {
196 if (tsc->id >= 0)
197 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
198 }
199
200 static inline void
201 nv50_screen_tic_free(struct nv50_screen *screen, struct nv50_tic_entry *tic)
202 {
203 if (tic->id >= 0) {
204 screen->tic.entries[tic->id] = NULL;
205 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
206 }
207 }
208
209 static inline void
210 nv50_screen_tsc_free(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
211 {
212 if (tsc->id >= 0) {
213 screen->tsc.entries[tsc->id] = NULL;
214 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
215 }
216 }
217
218 extern int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space);
219
220 #endif