src/gallium/drivers/nouveau/nv50/nv50_shader_state.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  * Copyright 2010 Christoph Bumiller
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "pipe/p_context.h"
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28
  29 #include "nv50/nv50_context.h"
  30 #include "nv50/nv50_query_hw.h"
  31
  32 #include "nv50/nv50_compute.xml.h"
  33
  34 void
  35 nv50_constbufs_validate(struct nv50_context *nv50)
  36 {
  37    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  38    unsigned s;
  39
  40    for (s = 0; s < 3; ++s) {
  41       unsigned p;
  42
  43       if (s == PIPE_SHADER_FRAGMENT)
  44          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_FRAGMENT;
  45       else
  46       if (s == PIPE_SHADER_GEOMETRY)
  47          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_GEOMETRY;
  48       else
  49          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_VERTEX;
  50
  51       while (nv50->constbuf_dirty[s]) {
  52          const unsigned i = (unsigned)ffs(nv50->constbuf_dirty[s]) - 1;
  53
  54          assert(i < NV50_MAX_PIPE_CONSTBUFS);
  55          nv50->constbuf_dirty[s] &= ~(1 << i);
  56
  57          if (nv50->constbuf[s][i].user) {
  58             const unsigned b = NV50_CB_PVP + s;
  59             unsigned start = 0;
  60             unsigned words = nv50->constbuf[s][0].size / 4;
  61             if (i) {
  62                NOUVEAU_ERR("user constbufs only supported in slot 0\n");
  63                continue;
  64             }
  65             if (!nv50->state.uniform_buffer_bound[s]) {
  66                nv50->state.uniform_buffer_bound[s] = true;
  67                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
  68                PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
  69             }
  70             while (words) {
  71                unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
  72
  73                PUSH_SPACE(push, nr + 3);
  74                BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
  75                PUSH_DATA (push, (start << 8) | b);
  76                BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
  77                PUSH_DATAp(push, &nv50->constbuf[s][0].u.data[start * 4], nr);
  78
  79                start += nr;
  80                words -= nr;
  81             }
  82          } else {
  83             struct nv04_resource *res =
  84                nv04_resource(nv50->constbuf[s][i].u.buf);
  85             if (res) {
  86                /* TODO: allocate persistent bindings */
  87                const unsigned b = s * 16 + i;
  88
  89                assert(nouveau_resource_mapped_by_gpu(&res->base));
  90
  91                BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
  92                PUSH_DATAh(push, res->address + nv50->constbuf[s][i].offset);
  93                PUSH_DATA (push, res->address + nv50->constbuf[s][i].offset);
  94                PUSH_DATA (push, (b << 16) |
  95                           (nv50->constbuf[s][i].size & 0xffff));
  96                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
  97                PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
  98
  99                BCTX_REFN(nv50->bufctx_3d, 3D_CB(s, i), res, RD);
 100
 101                nv50->cb_dirty = 1; /* Force cache flush for UBO. */
 102                res->cb_bindings[s] |= 1 << i;
 103             } else {
 104                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
 105                PUSH_DATA (push, (i << 8) | p | 0);
 106             }
 107             if (i == 0)
 108                nv50->state.uniform_buffer_bound[s] = false;
 109          }
 110       }
 111    }
 112 }
 113
 114 static bool
 115 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *prog)
 116 {
 117    if (!prog->translated) {
 118       prog->translated = nv50_program_translate(
 119          prog, nv50->screen->base.device->chipset, &nv50->base.debug);
 120       if (!prog->translated)
 121          return false;
 122    } else
 123    if (prog->mem)
 124       return true;
 125
 126    return nv50_program_upload_code(nv50, prog);
 127 }
 128
 129 static inline void
 130 nv50_program_update_context_state(struct nv50_context *nv50,
 131                                   struct nv50_program *prog, int stage)
 132 {
 133    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR;
 134
 135    if (prog && prog->tls_space) {
 136       if (nv50->state.new_tls_space)
 137          nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TLS);
 138       if (!nv50->state.tls_required || nv50->state.new_tls_space)
 139          BCTX_REFN_bo(nv50->bufctx_3d, 3D_TLS, flags, nv50->screen->tls_bo);
 140       nv50->state.new_tls_space = false;
 141       nv50->state.tls_required |= 1 << stage;
 142    } else {
 143       if (nv50->state.tls_required == (1 << stage))
 144          nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TLS);
 145       nv50->state.tls_required &= ~(1 << stage);
 146    }
 147 }
 148
 149 void
 150 nv50_vertprog_validate(struct nv50_context *nv50)
 151 {
 152    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 153    struct nv50_program *vp = nv50->vertprog;
 154
 155    if (!nv50_program_validate(nv50, vp))
 156          return;
 157    nv50_program_update_context_state(nv50, vp, 0);
 158
 159    BEGIN_NV04(push, NV50_3D(VP_ATTR_EN(0)), 2);
 160    PUSH_DATA (push, vp->vp.attrs[0]);
 161    PUSH_DATA (push, vp->vp.attrs[1]);
 162    BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_RESULT), 1);
 163    PUSH_DATA (push, vp->max_out);
 164    BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_TEMP), 1);
 165    PUSH_DATA (push, vp->max_gpr);
 166    BEGIN_NV04(push, NV50_3D(VP_START_ID), 1);
 167    PUSH_DATA (push, vp->code_base);
 168 }
 169
 170 void
 171 nv50_fragprog_validate(struct nv50_context *nv50)
 172 {
 173    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 174    struct nv50_program *fp = nv50->fragprog;
 175    struct pipe_rasterizer_state *rast = &nv50->rast->pipe;
 176
 177    if (fp->fp.force_persample_interp != rast->force_persample_interp) {
 178       /* Force the program to be reuploaded, which will trigger interp fixups
 179        * to get applied
 180        */
 181       if (fp->mem)
 182          nouveau_heap_free(&fp->mem);
 183
 184       fp->fp.force_persample_interp = rast->force_persample_interp;
 185    }
 186
 187    if (fp->mem && !(nv50->dirty_3d & (NV50_NEW_3D_FRAGPROG | NV50_NEW_3D_MIN_SAMPLES)))
 188       return;
 189
 190    if (!nv50_program_validate(nv50, fp))
 191       return;
 192    nv50_program_update_context_state(nv50, fp, 1);
 193
 194    BEGIN_NV04(push, NV50_3D(FP_REG_ALLOC_TEMP), 1);
 195    PUSH_DATA (push, fp->max_gpr);
 196    BEGIN_NV04(push, NV50_3D(FP_RESULT_COUNT), 1);
 197    PUSH_DATA (push, fp->max_out);
 198    BEGIN_NV04(push, NV50_3D(FP_CONTROL), 1);
 199    PUSH_DATA (push, fp->fp.flags[0]);
 200    BEGIN_NV04(push, NV50_3D(FP_CTRL_UNK196C), 1);
 201    PUSH_DATA (push, fp->fp.flags[1]);
 202    BEGIN_NV04(push, NV50_3D(FP_START_ID), 1);
 203    PUSH_DATA (push, fp->code_base);
 204
 205    if (nv50->screen->tesla->oclass >= NVA3_3D_CLASS) {
 206       BEGIN_NV04(push, SUBC_3D(NVA3_3D_FP_MULTISAMPLE), 1);
 207       if (nv50->min_samples > 1 || fp->fp.has_samplemask)
 208          PUSH_DATA(push,
 209                    NVA3_3D_FP_MULTISAMPLE_FORCE_PER_SAMPLE |
 210                    (NVA3_3D_FP_MULTISAMPLE_EXPORT_SAMPLE_MASK *
 211                     fp->fp.has_samplemask));
 212       else
 213          PUSH_DATA(push, 0);
 214    }
 215 }
 216
 217 void
 218 nv50_gmtyprog_validate(struct nv50_context *nv50)
 219 {
 220    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 221    struct nv50_program *gp = nv50->gmtyprog;
 222
 223    if (gp) {
 224       if (!nv50_program_validate(nv50, gp))
 225          return;
 226       BEGIN_NV04(push, NV50_3D(GP_REG_ALLOC_TEMP), 1);
 227       PUSH_DATA (push, gp->max_gpr);
 228       BEGIN_NV04(push, NV50_3D(GP_REG_ALLOC_RESULT), 1);
 229       PUSH_DATA (push, gp->max_out);
 230       BEGIN_NV04(push, NV50_3D(GP_OUTPUT_PRIMITIVE_TYPE), 1);
 231       PUSH_DATA (push, gp->gp.prim_type);
 232       BEGIN_NV04(push, NV50_3D(GP_VERTEX_OUTPUT_COUNT), 1);
 233       PUSH_DATA (push, gp->gp.vert_count);
 234       BEGIN_NV04(push, NV50_3D(GP_START_ID), 1);
 235       PUSH_DATA (push, gp->code_base);
 236
 237       nv50->state.prim_size = gp->gp.prim_type; /* enum matches vertex count */
 238    }
 239    nv50_program_update_context_state(nv50, gp, 2);
 240
 241    /* GP_ENABLE is updated in linkage validation */
 242 }
 243
 244 void
 245 nv50_compprog_validate(struct nv50_context *nv50)
 246 {
 247    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 248    struct nv50_program *cp = nv50->compprog;
 249
 250    if (cp && !nv50_program_validate(nv50, cp))
 251       return;
 252
 253    BEGIN_NV04(push, NV50_CP(CODE_CB_FLUSH), 1);
 254    PUSH_DATA (push, 0);
 255 }
 256
 257 static void
 258 nv50_sprite_coords_validate(struct nv50_context *nv50)
 259 {
 260    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 261    uint32_t pntc[8], mode;
 262    struct nv50_program *fp = nv50->fragprog;
 263    unsigned i, c;
 264    unsigned m = (nv50->state.interpolant_ctrl >> 8) & 0xff;
 265
 266    if (!nv50->rast->pipe.point_quad_rasterization) {
 267       if (nv50->state.point_sprite) {
 268          BEGIN_NV04(push, NV50_3D(POINT_COORD_REPLACE_MAP(0)), 8);
 269          for (i = 0; i < 8; ++i)
 270             PUSH_DATA(push, 0);
 271
 272          nv50->state.point_sprite = false;
 273       }
 274       return;
 275    } else {
 276       nv50->state.point_sprite = true;
 277    }
 278
 279    memset(pntc, 0, sizeof(pntc));
 280
 281    for (i = 0; i < fp->in_nr; i++) {
 282       unsigned n = util_bitcount(fp->in[i].mask);
 283
 284       if (fp->in[i].sn != TGSI_SEMANTIC_GENERIC) {
 285          m += n;
 286          continue;
 287       }
 288       if (!(nv50->rast->pipe.sprite_coord_enable & (1 << fp->in[i].si))) {
 289          m += n;
 290          continue;
 291       }
 292
 293       for (c = 0; c < 4; ++c) {
 294          if (fp->in[i].mask & (1 << c)) {
 295             pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
 296             ++m;
 297          }
 298       }
 299    }
 300
 301    if (nv50->rast->pipe.sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT)
 302       mode = 0x00;
 303    else
 304       mode = 0x10;
 305
 306    BEGIN_NV04(push, NV50_3D(POINT_SPRITE_CTRL), 1);
 307    PUSH_DATA (push, mode);
 308
 309    BEGIN_NV04(push, NV50_3D(POINT_COORD_REPLACE_MAP(0)), 8);
 310    PUSH_DATAp(push, pntc, 8);
 311 }
 312
 313 /* Validate state derived from shaders and the rasterizer cso. */
 314 void
 315 nv50_validate_derived_rs(struct nv50_context *nv50)
 316 {
 317    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 318    uint32_t color, psize;
 319
 320    nv50_sprite_coords_validate(nv50);
 321
 322    if (nv50->state.rasterizer_discard != nv50->rast->pipe.rasterizer_discard) {
 323       nv50->state.rasterizer_discard = nv50->rast->pipe.rasterizer_discard;
 324       BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 325       PUSH_DATA (push, !nv50->rast->pipe.rasterizer_discard);
 326    }
 327
 328    if (nv50->dirty_3d & NV50_NEW_3D_FRAGPROG)
 329       return;
 330    psize = nv50->state.semantic_psize & ~NV50_3D_SEMANTIC_PTSZ_PTSZ_EN__MASK;
 331    color = nv50->state.semantic_color & ~NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 332
 333    if (nv50->rast->pipe.clamp_vertex_color)
 334       color |= NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 335
 336    if (color != nv50->state.semantic_color) {
 337       nv50->state.semantic_color = color;
 338       BEGIN_NV04(push, NV50_3D(SEMANTIC_COLOR), 1);
 339       PUSH_DATA (push, color);
 340    }
 341
 342    if (nv50->rast->pipe.point_size_per_vertex)
 343       psize |= NV50_3D_SEMANTIC_PTSZ_PTSZ_EN__MASK;
 344
 345    if (psize != nv50->state.semantic_psize) {
 346       nv50->state.semantic_psize = psize;
 347       BEGIN_NV04(push, NV50_3D(SEMANTIC_PTSZ), 1);
 348       PUSH_DATA (push, psize);
 349    }
 350 }
 351
 352 static int
 353 nv50_vec4_map(uint8_t *map, int mid, uint32_t lin[4],
 354               struct nv50_varying *in, struct nv50_varying *out)
 355 {
 356    int c;
 357    uint8_t mv = out->mask, mf = in->mask, oid = out->hw;
 358
 359    for (c = 0; c < 4; ++c) {
 360       if (mf & 1) {
 361          if (in->linear)
 362             lin[mid / 32] |= 1 << (mid % 32);
 363          if (mv & 1)
 364             map[mid] = oid;
 365          else
 366          if (c == 3)
 367             map[mid] |= 1;
 368          ++mid;
 369       }
 370
 371       oid += mv & 1;
 372       mf >>= 1;
 373       mv >>= 1;
 374    }
 375
 376    return mid;
 377 }
 378
 379 void
 380 nv50_fp_linkage_validate(struct nv50_context *nv50)
 381 {
 382    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 383    struct nv50_program *vp = nv50->gmtyprog ? nv50->gmtyprog : nv50->vertprog;
 384    struct nv50_program *fp = nv50->fragprog;
 385    struct nv50_varying dummy;
 386    int i, n, c, m;
 387    uint32_t primid = 0;
 388    uint32_t layerid = 0;
 389    uint32_t viewportid = 0;
 390    uint32_t psiz = 0x000;
 391    uint32_t interp = fp->fp.interp;
 392    uint32_t colors = fp->fp.colors;
 393    uint32_t clpd_nr = util_last_bit(vp->vp.clip_enable | vp->vp.cull_enable);
 394    uint32_t lin[4];
 395    uint8_t map[64];
 396    uint8_t so_map[64];
 397
 398    if (!(nv50->dirty_3d & (NV50_NEW_3D_VERTPROG |
 399                            NV50_NEW_3D_FRAGPROG |
 400                            NV50_NEW_3D_GMTYPROG))) {
 401       uint8_t bfc, ffc;
 402       ffc = (nv50->state.semantic_color & NV50_3D_SEMANTIC_COLOR_FFC0_ID__MASK);
 403       bfc = (nv50->state.semantic_color & NV50_3D_SEMANTIC_COLOR_BFC0_ID__MASK)
 404          >> 8;
 405       if (nv50->rast->pipe.light_twoside == ((ffc == bfc) ? 0 : 1))
 406          return;
 407    }
 408
 409    memset(lin, 0x00, sizeof(lin));
 410
 411    /* XXX: in buggy-endian mode, is the first element of map (u32)0x000000xx
 412     *  or is it the first byte ?
 413     */
 414    memset(map, nv50->gmtyprog ? 0x80 : 0x40, sizeof(map));
 415
 416    dummy.mask = 0xf; /* map all components of HPOS */
 417    dummy.linear = 0;
 418    m = nv50_vec4_map(map, 0, lin, &dummy, &vp->out[0]);
 419
 420    for (c = 0; c < clpd_nr; ++c)
 421       map[m++] = vp->vp.clpd[c / 4] + (c % 4);
 422
 423    colors |= m << 8; /* adjust BFC0 id */
 424
 425    dummy.mask = 0x0;
 426
 427    /* if light_twoside is active, FFC0_ID == BFC0_ID is invalid */
 428    if (nv50->rast->pipe.light_twoside) {
 429       for (i = 0; i < 2; ++i) {
 430          n = vp->vp.bfc[i];
 431          if (fp->vp.bfc[i] >= fp->in_nr)
 432             continue;
 433          m = nv50_vec4_map(map, m, lin, &fp->in[fp->vp.bfc[i]],
 434                            (n < vp->out_nr) ? &vp->out[n] : &dummy);
 435       }
 436    }
 437    colors += m - 4; /* adjust FFC0 id */
 438    interp |= m << 8; /* set map id where 'normal' FP inputs start */
 439
 440    for (i = 0; i < fp->in_nr; ++i) {
 441       for (n = 0; n < vp->out_nr; ++n)
 442          if (vp->out[n].sn == fp->in[i].sn &&
 443              vp->out[n].si == fp->in[i].si)
 444             break;
 445       switch (fp->in[i].sn) {
 446       case TGSI_SEMANTIC_PRIMID:
 447          primid = m;
 448          break;
 449       case TGSI_SEMANTIC_LAYER:
 450          layerid = m;
 451          break;
 452       case TGSI_SEMANTIC_VIEWPORT_INDEX:
 453          viewportid = m;
 454          break;
 455       }
 456       m = nv50_vec4_map(map, m, lin,
 457                         &fp->in[i], (n < vp->out_nr) ? &vp->out[n] : &dummy);
 458    }
 459
 460    if (vp->gp.has_layer && !layerid) {
 461       layerid = m;
 462       map[m++] = vp->gp.layerid;
 463    }
 464
 465    if (vp->gp.has_viewport && !viewportid) {
 466       viewportid = m;
 467       map[m++] = vp->gp.viewportid;
 468    }
 469
 470    if (nv50->rast->pipe.point_size_per_vertex) {
 471       psiz = (m << 4) | 1;
 472       map[m++] = vp->vp.psiz;
 473    }
 474
 475    if (nv50->rast->pipe.clamp_vertex_color)
 476       colors |= NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 477
 478    if (unlikely(vp->so)) {
 479       /* Slot i in STRMOUT_MAP specifies the offset where slot i in RESULT_MAP
 480        * gets written.
 481        *
 482        * TODO:
 483        * Inverting vp->so->map (output -> offset) would probably speed this up.
 484        */
 485       memset(so_map, 0, sizeof(so_map));
 486       for (i = 0; i < vp->so->map_size; ++i) {
 487          if (vp->so->map[i] == 0xff)
 488             continue;
 489          for (c = 0; c < m; ++c)
 490             if (map[c] == vp->so->map[i] && !so_map[c])
 491                break;
 492          if (c == m) {
 493             c = m;
 494             map[m++] = vp->so->map[i];
 495          }
 496          so_map[c] = 0x80 | i;
 497       }
 498       for (c = m; c & 3; ++c)
 499          so_map[c] = 0;
 500    }
 501
 502    n = (m + 3) / 4;
 503    assert(m <= 64);
 504
 505    if (unlikely(nv50->gmtyprog)) {
 506       BEGIN_NV04(push, NV50_3D(GP_RESULT_MAP_SIZE), 1);
 507       PUSH_DATA (push, m);
 508       BEGIN_NV04(push, NV50_3D(GP_RESULT_MAP(0)), n);
 509       PUSH_DATAp(push, map, n);
 510    } else {
 511       BEGIN_NV04(push, NV50_3D(VP_GP_BUILTIN_ATTR_EN), 1);
 512       PUSH_DATA (push, vp->vp.attrs[2] | fp->vp.attrs[2]);
 513
 514       BEGIN_NV04(push, NV50_3D(SEMANTIC_PRIM_ID), 1);
 515       PUSH_DATA (push, primid);
 516
 517       assert(m > 0);
 518       BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP_SIZE), 1);
 519       PUSH_DATA (push, m);
 520       BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP(0)), n);
 521       PUSH_DATAp(push, map, n);
 522    }
 523
 524    BEGIN_NV04(push, NV50_3D(GP_VIEWPORT_ID_ENABLE), 5);
 525    PUSH_DATA (push, vp->gp.has_viewport);
 526    PUSH_DATA (push, colors);
 527    PUSH_DATA (push, (clpd_nr << 8) | 4);
 528    PUSH_DATA (push, layerid);
 529    PUSH_DATA (push, psiz);
 530
 531    BEGIN_NV04(push, NV50_3D(SEMANTIC_VIEWPORT), 1);
 532    PUSH_DATA (push, viewportid);
 533
 534    BEGIN_NV04(push, NV50_3D(LAYER), 1);
 535    PUSH_DATA (push, vp->gp.has_layer << 16);
 536
 537    BEGIN_NV04(push, NV50_3D(FP_INTERPOLANT_CTRL), 1);
 538    PUSH_DATA (push, interp);
 539
 540    nv50->state.interpolant_ctrl = interp;
 541
 542    nv50->state.semantic_color = colors;
 543    nv50->state.semantic_psize = psiz;
 544
 545    BEGIN_NV04(push, NV50_3D(NOPERSPECTIVE_BITMAP(0)), 4);
 546    PUSH_DATAp(push, lin, 4);
 547
 548    BEGIN_NV04(push, NV50_3D(GP_ENABLE), 1);
 549    PUSH_DATA (push, nv50->gmtyprog ? 1 : 0);
 550
 551    if (vp->so) {
 552       BEGIN_NV04(push, NV50_3D(STRMOUT_MAP(0)), n);
 553       PUSH_DATAp(push, so_map, n);
 554    }
 555 }
 556
 557 static int
 558 nv50_vp_gp_mapping(uint8_t *map, int m,
 559                    struct nv50_program *vp, struct nv50_program *gp)
 560 {
 561    int i, j, c;
 562
 563    for (i = 0; i < gp->in_nr; ++i) {
 564       uint8_t oid = 0, mv = 0, mg = gp->in[i].mask;
 565
 566       for (j = 0; j < vp->out_nr; ++j) {
 567          if (vp->out[j].sn == gp->in[i].sn &&
 568              vp->out[j].si == gp->in[i].si) {
 569             mv = vp->out[j].mask;
 570             oid = vp->out[j].hw;
 571             break;
 572          }
 573       }
 574
 575       for (c = 0; c < 4; ++c, mv >>= 1, mg >>= 1) {
 576          if (mg & mv & 1)
 577             map[m++] = oid;
 578          else
 579          if (mg & 1)
 580             map[m++] = (c == 3) ? 0x41 : 0x40;
 581          oid += mv & 1;
 582       }
 583    }
 584    if (!m)
 585       map[m++] = 0;
 586    return m;
 587 }
 588
 589 void
 590 nv50_gp_linkage_validate(struct nv50_context *nv50)
 591 {
 592    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 593    struct nv50_program *vp = nv50->vertprog;
 594    struct nv50_program *gp = nv50->gmtyprog;
 595    int m = 0;
 596    int n;
 597    uint8_t map[64];
 598
 599    if (!gp)
 600       return;
 601    memset(map, 0, sizeof(map));
 602
 603    m = nv50_vp_gp_mapping(map, m, vp, gp);
 604
 605    n = (m + 3) / 4;
 606
 607    BEGIN_NV04(push, NV50_3D(VP_GP_BUILTIN_ATTR_EN), 1);
 608    PUSH_DATA (push, vp->vp.attrs[2] | gp->vp.attrs[2]);
 609
 610    assert(m > 0);
 611    BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP_SIZE), 1);
 612    PUSH_DATA (push, m);
 613    BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP(0)), n);
 614    PUSH_DATAp(push, map, n);
 615 }
 616
 617 void
 618 nv50_stream_output_validate(struct nv50_context *nv50)
 619 {
 620    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 621    struct nv50_stream_output_state *so;
 622    uint32_t ctrl;
 623    unsigned i;
 624    unsigned prims = ~0;
 625
 626    so = nv50->gmtyprog ? nv50->gmtyprog->so : nv50->vertprog->so;
 627
 628    BEGIN_NV04(push, NV50_3D(STRMOUT_ENABLE), 1);
 629    PUSH_DATA (push, 0);
 630    if (!so || !nv50->num_so_targets) {
 631       if (nv50->screen->base.class_3d < NVA0_3D_CLASS) {
 632          BEGIN_NV04(push, NV50_3D(STRMOUT_PRIMITIVE_LIMIT), 1);
 633          PUSH_DATA (push, 0);
 634       }
 635       BEGIN_NV04(push, NV50_3D(STRMOUT_PARAMS_LATCH), 1);
 636       PUSH_DATA (push, 1);
 637       return;
 638    }
 639
 640    /* previous TFB needs to complete */
 641    if (nv50->screen->base.class_3d < NVA0_3D_CLASS) {
 642       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 643       PUSH_DATA (push, 0);
 644    }
 645
 646    ctrl = so->ctrl;
 647    if (nv50->screen->base.class_3d >= NVA0_3D_CLASS)
 648       ctrl |= NVA0_3D_STRMOUT_BUFFERS_CTRL_LIMIT_MODE_OFFSET;
 649
 650    BEGIN_NV04(push, NV50_3D(STRMOUT_BUFFERS_CTRL), 1);
 651    PUSH_DATA (push, ctrl);
 652
 653    for (i = 0; i < nv50->num_so_targets; ++i) {
 654       struct nv50_so_target *targ = nv50_so_target(nv50->so_target[i]);
 655       struct nv04_resource *buf = nv04_resource(targ->pipe.buffer);
 656
 657       const unsigned n = nv50->screen->base.class_3d >= NVA0_3D_CLASS ? 4 : 3;
 658
 659       if (n == 4 && !targ->clean)
 660          nv84_hw_query_fifo_wait(push, nv50_query(targ->pq));
 661       BEGIN_NV04(push, NV50_3D(STRMOUT_ADDRESS_HIGH(i)), n);
 662       PUSH_DATAh(push, buf->address + targ->pipe.buffer_offset);
 663       PUSH_DATA (push, buf->address + targ->pipe.buffer_offset);
 664       PUSH_DATA (push, so->num_attribs[i]);
 665       if (n == 4) {
 666          PUSH_DATA(push, targ->pipe.buffer_size);
 667          if (!targ->clean) {
 668             assert(targ->pq);
 669             nv50_hw_query_pushbuf_submit(push, NVA0_3D_STRMOUT_OFFSET(i),
 670                                          nv50_query(targ->pq), 0x4);
 671          } else {
 672             BEGIN_NV04(push, NVA0_3D(STRMOUT_OFFSET(i)), 1);
 673             PUSH_DATA(push, 0);
 674             targ->clean = false;
 675          }
 676       } else {
 677          const unsigned limit = targ->pipe.buffer_size /
 678             (so->stride[i] * nv50->state.prim_size);
 679          prims = MIN2(prims, limit);
 680       }
 681       targ->stride = so->stride[i];
 682       BCTX_REFN(nv50->bufctx_3d, 3D_SO, buf, WR);
 683    }
 684    if (prims != ~0) {
 685       BEGIN_NV04(push, NV50_3D(STRMOUT_PRIMITIVE_LIMIT), 1);
 686       PUSH_DATA (push, prims);
 687    }
 688    BEGIN_NV04(push, NV50_3D(STRMOUT_PARAMS_LATCH), 1);
 689    PUSH_DATA (push, 1);
 690    BEGIN_NV04(push, NV50_3D(STRMOUT_ENABLE), 1);
 691    PUSH_DATA (push, 1);
 692 }