src/gallium/drivers/nouveau/nv50/nv50_shader_state.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  * Copyright 2010 Christoph Bumiller
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "pipe/p_context.h"
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28
  29 #include "nv50/nv50_context.h"
  30 #include "nv50/nv50_query_hw.h"
  31
  32 #include "nv50/nv50_compute.xml.h"
  33
  34 void
  35 nv50_constbufs_validate(struct nv50_context *nv50)
  36 {
  37    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  38    unsigned s;
  39
  40    for (s = 0; s < 3; ++s) {
  41       unsigned p;
  42
  43       if (s == PIPE_SHADER_FRAGMENT)
  44          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_FRAGMENT;
  45       else
  46       if (s == PIPE_SHADER_GEOMETRY)
  47          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_GEOMETRY;
  48       else
  49          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_VERTEX;
  50
  51       while (nv50->constbuf_dirty[s]) {
  52          const unsigned i = (unsigned)ffs(nv50->constbuf_dirty[s]) - 1;
  53
  54          assert(i < NV50_MAX_PIPE_CONSTBUFS);
  55          nv50->constbuf_dirty[s] &= ~(1 << i);
  56
  57          if (nv50->constbuf[s][i].user) {
  58             const unsigned b = NV50_CB_PVP + s;
  59             unsigned start = 0;
  60             unsigned words = nv50->constbuf[s][0].size / 4;
  61             if (i) {
  62                NOUVEAU_ERR("user constbufs only supported in slot 0\n");
  63                continue;
  64             }
  65             if (!nv50->state.uniform_buffer_bound[s]) {
  66                nv50->state.uniform_buffer_bound[s] = true;
  67                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
  68                PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
  69             }
  70             while (words) {
  71                unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
  72
  73                PUSH_SPACE(push, nr + 3);
  74                BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
  75                PUSH_DATA (push, (start << 8) | b);
  76                BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
  77                PUSH_DATAp(push, &nv50->constbuf[s][0].u.data[start * 4], nr);
  78
  79                start += nr;
  80                words -= nr;
  81             }
  82          } else {
  83             struct nv04_resource *res =
  84                nv04_resource(nv50->constbuf[s][i].u.buf);
  85             if (res) {
  86                /* TODO: allocate persistent bindings */
  87                const unsigned b = s * 16 + i;
  88
  89                assert(nouveau_resource_mapped_by_gpu(&res->base));
  90
  91                BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
  92                PUSH_DATAh(push, res->address + nv50->constbuf[s][i].offset);
  93                PUSH_DATA (push, res->address + nv50->constbuf[s][i].offset);
  94                PUSH_DATA (push, (b << 16) |
  95                           (nv50->constbuf[s][i].size & 0xffff));
  96                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
  97                PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
  98
  99                BCTX_REFN(nv50->bufctx_3d, 3D_CB(s, i), res, RD);
 100
 101                nv50->cb_dirty = 1; /* Force cache flush for UBO. */
 102             } else {
 103                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
 104                PUSH_DATA (push, (i << 8) | p | 0);
 105             }
 106             if (i == 0)
 107                nv50->state.uniform_buffer_bound[s] = false;
 108          }
 109       }
 110    }
 111 }
 112
 113 static bool
 114 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *prog)
 115 {
 116    if (!prog->translated) {
 117       prog->translated = nv50_program_translate(
 118          prog, nv50->screen->base.device->chipset, &nv50->base.debug);
 119       if (!prog->translated)
 120          return false;
 121    } else
 122    if (prog->mem)
 123       return true;
 124
 125    return nv50_program_upload_code(nv50, prog);
 126 }
 127
 128 static inline void
 129 nv50_program_update_context_state(struct nv50_context *nv50,
 130                                   struct nv50_program *prog, int stage)
 131 {
 132    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR;
 133
 134    if (prog && prog->tls_space) {
 135       if (nv50->state.new_tls_space)
 136          nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TLS);
 137       if (!nv50->state.tls_required || nv50->state.new_tls_space)
 138          BCTX_REFN_bo(nv50->bufctx_3d, 3D_TLS, flags, nv50->screen->tls_bo);
 139       nv50->state.new_tls_space = false;
 140       nv50->state.tls_required |= 1 << stage;
 141    } else {
 142       if (nv50->state.tls_required == (1 << stage))
 143          nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TLS);
 144       nv50->state.tls_required &= ~(1 << stage);
 145    }
 146 }
 147
 148 void
 149 nv50_vertprog_validate(struct nv50_context *nv50)
 150 {
 151    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 152    struct nv50_program *vp = nv50->vertprog;
 153
 154    if (!nv50_program_validate(nv50, vp))
 155          return;
 156    nv50_program_update_context_state(nv50, vp, 0);
 157
 158    BEGIN_NV04(push, NV50_3D(VP_ATTR_EN(0)), 2);
 159    PUSH_DATA (push, vp->vp.attrs[0]);
 160    PUSH_DATA (push, vp->vp.attrs[1]);
 161    BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_RESULT), 1);
 162    PUSH_DATA (push, vp->max_out);
 163    BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_TEMP), 1);
 164    PUSH_DATA (push, vp->max_gpr);
 165    BEGIN_NV04(push, NV50_3D(VP_START_ID), 1);
 166    PUSH_DATA (push, vp->code_base);
 167 }
 168
 169 void
 170 nv50_fragprog_validate(struct nv50_context *nv50)
 171 {
 172    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 173    struct nv50_program *fp = nv50->fragprog;
 174    struct pipe_rasterizer_state *rast = &nv50->rast->pipe;
 175
 176    if (fp->fp.force_persample_interp != rast->force_persample_interp) {
 177       /* Force the program to be reuploaded, which will trigger interp fixups
 178        * to get applied
 179        */
 180       if (fp->mem)
 181          nouveau_heap_free(&fp->mem);
 182
 183       fp->fp.force_persample_interp = rast->force_persample_interp;
 184    }
 185
 186    if (fp->mem && !(nv50->dirty_3d & (NV50_NEW_3D_FRAGPROG | NV50_NEW_3D_MIN_SAMPLES)))
 187       return;
 188
 189    if (!nv50_program_validate(nv50, fp))
 190       return;
 191    nv50_program_update_context_state(nv50, fp, 1);
 192
 193    BEGIN_NV04(push, NV50_3D(FP_REG_ALLOC_TEMP), 1);
 194    PUSH_DATA (push, fp->max_gpr);
 195    BEGIN_NV04(push, NV50_3D(FP_RESULT_COUNT), 1);
 196    PUSH_DATA (push, fp->max_out);
 197    BEGIN_NV04(push, NV50_3D(FP_CONTROL), 1);
 198    PUSH_DATA (push, fp->fp.flags[0]);
 199    BEGIN_NV04(push, NV50_3D(FP_CTRL_UNK196C), 1);
 200    PUSH_DATA (push, fp->fp.flags[1]);
 201    BEGIN_NV04(push, NV50_3D(FP_START_ID), 1);
 202    PUSH_DATA (push, fp->code_base);
 203
 204    if (nv50->screen->tesla->oclass >= NVA3_3D_CLASS) {
 205       BEGIN_NV04(push, SUBC_3D(NVA3_3D_FP_MULTISAMPLE), 1);
 206       if (nv50->min_samples > 1 || fp->fp.has_samplemask)
 207          PUSH_DATA(push,
 208                    NVA3_3D_FP_MULTISAMPLE_FORCE_PER_SAMPLE |
 209                    (NVA3_3D_FP_MULTISAMPLE_EXPORT_SAMPLE_MASK *
 210                     fp->fp.has_samplemask));
 211       else
 212          PUSH_DATA(push, 0);
 213    }
 214 }
 215
 216 void
 217 nv50_gmtyprog_validate(struct nv50_context *nv50)
 218 {
 219    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 220    struct nv50_program *gp = nv50->gmtyprog;
 221
 222    if (gp) {
 223       if (!nv50_program_validate(nv50, gp))
 224          return;
 225       BEGIN_NV04(push, NV50_3D(GP_REG_ALLOC_TEMP), 1);
 226       PUSH_DATA (push, gp->max_gpr);
 227       BEGIN_NV04(push, NV50_3D(GP_REG_ALLOC_RESULT), 1);
 228       PUSH_DATA (push, gp->max_out);
 229       BEGIN_NV04(push, NV50_3D(GP_OUTPUT_PRIMITIVE_TYPE), 1);
 230       PUSH_DATA (push, gp->gp.prim_type);
 231       BEGIN_NV04(push, NV50_3D(GP_VERTEX_OUTPUT_COUNT), 1);
 232       PUSH_DATA (push, gp->gp.vert_count);
 233       BEGIN_NV04(push, NV50_3D(GP_START_ID), 1);
 234       PUSH_DATA (push, gp->code_base);
 235
 236       nv50->state.prim_size = gp->gp.prim_type; /* enum matches vertex count */
 237    }
 238    nv50_program_update_context_state(nv50, gp, 2);
 239
 240    /* GP_ENABLE is updated in linkage validation */
 241 }
 242
 243 void
 244 nv50_compprog_validate(struct nv50_context *nv50)
 245 {
 246    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 247    struct nv50_program *cp = nv50->compprog;
 248
 249    if (cp && !nv50_program_validate(nv50, cp))
 250       return;
 251
 252    BEGIN_NV04(push, NV50_CP(CODE_CB_FLUSH), 1);
 253    PUSH_DATA (push, 0);
 254 }
 255
 256 static void
 257 nv50_sprite_coords_validate(struct nv50_context *nv50)
 258 {
 259    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 260    uint32_t pntc[8], mode;
 261    struct nv50_program *fp = nv50->fragprog;
 262    unsigned i, c;
 263    unsigned m = (nv50->state.interpolant_ctrl >> 8) & 0xff;
 264
 265    if (!nv50->rast->pipe.point_quad_rasterization) {
 266       if (nv50->state.point_sprite) {
 267          BEGIN_NV04(push, NV50_3D(POINT_COORD_REPLACE_MAP(0)), 8);
 268          for (i = 0; i < 8; ++i)
 269             PUSH_DATA(push, 0);
 270
 271          nv50->state.point_sprite = false;
 272       }
 273       return;
 274    } else {
 275       nv50->state.point_sprite = true;
 276    }
 277
 278    memset(pntc, 0, sizeof(pntc));
 279
 280    for (i = 0; i < fp->in_nr; i++) {
 281       unsigned n = util_bitcount(fp->in[i].mask);
 282
 283       if (fp->in[i].sn != TGSI_SEMANTIC_GENERIC) {
 284          m += n;
 285          continue;
 286       }
 287       if (!(nv50->rast->pipe.sprite_coord_enable & (1 << fp->in[i].si))) {
 288          m += n;
 289          continue;
 290       }
 291
 292       for (c = 0; c < 4; ++c) {
 293          if (fp->in[i].mask & (1 << c)) {
 294             pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
 295             ++m;
 296          }
 297       }
 298    }
 299
 300    if (nv50->rast->pipe.sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT)
 301       mode = 0x00;
 302    else
 303       mode = 0x10;
 304
 305    BEGIN_NV04(push, NV50_3D(POINT_SPRITE_CTRL), 1);
 306    PUSH_DATA (push, mode);
 307
 308    BEGIN_NV04(push, NV50_3D(POINT_COORD_REPLACE_MAP(0)), 8);
 309    PUSH_DATAp(push, pntc, 8);
 310 }
 311
 312 /* Validate state derived from shaders and the rasterizer cso. */
 313 void
 314 nv50_validate_derived_rs(struct nv50_context *nv50)
 315 {
 316    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 317    uint32_t color, psize;
 318
 319    nv50_sprite_coords_validate(nv50);
 320
 321    if (nv50->state.rasterizer_discard != nv50->rast->pipe.rasterizer_discard) {
 322       nv50->state.rasterizer_discard = nv50->rast->pipe.rasterizer_discard;
 323       BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 324       PUSH_DATA (push, !nv50->rast->pipe.rasterizer_discard);
 325    }
 326
 327    if (nv50->dirty_3d & NV50_NEW_3D_FRAGPROG)
 328       return;
 329    psize = nv50->state.semantic_psize & ~NV50_3D_SEMANTIC_PTSZ_PTSZ_EN__MASK;
 330    color = nv50->state.semantic_color & ~NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 331
 332    if (nv50->rast->pipe.clamp_vertex_color)
 333       color |= NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 334
 335    if (color != nv50->state.semantic_color) {
 336       nv50->state.semantic_color = color;
 337       BEGIN_NV04(push, NV50_3D(SEMANTIC_COLOR), 1);
 338       PUSH_DATA (push, color);
 339    }
 340
 341    if (nv50->rast->pipe.point_size_per_vertex)
 342       psize |= NV50_3D_SEMANTIC_PTSZ_PTSZ_EN__MASK;
 343
 344    if (psize != nv50->state.semantic_psize) {
 345       nv50->state.semantic_psize = psize;
 346       BEGIN_NV04(push, NV50_3D(SEMANTIC_PTSZ), 1);
 347       PUSH_DATA (push, psize);
 348    }
 349 }
 350
 351 static int
 352 nv50_vec4_map(uint8_t *map, int mid, uint32_t lin[4],
 353               struct nv50_varying *in, struct nv50_varying *out)
 354 {
 355    int c;
 356    uint8_t mv = out->mask, mf = in->mask, oid = out->hw;
 357
 358    for (c = 0; c < 4; ++c) {
 359       if (mf & 1) {
 360          if (in->linear)
 361             lin[mid / 32] |= 1 << (mid % 32);
 362          if (mv & 1)
 363             map[mid] = oid;
 364          else
 365          if (c == 3)
 366             map[mid] |= 1;
 367          ++mid;
 368       }
 369
 370       oid += mv & 1;
 371       mf >>= 1;
 372       mv >>= 1;
 373    }
 374
 375    return mid;
 376 }
 377
 378 void
 379 nv50_fp_linkage_validate(struct nv50_context *nv50)
 380 {
 381    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 382    struct nv50_program *vp = nv50->gmtyprog ? nv50->gmtyprog : nv50->vertprog;
 383    struct nv50_program *fp = nv50->fragprog;
 384    struct nv50_varying dummy;
 385    int i, n, c, m;
 386    uint32_t primid = 0;
 387    uint32_t layerid = 0;
 388    uint32_t viewportid = 0;
 389    uint32_t psiz = 0x000;
 390    uint32_t interp = fp->fp.interp;
 391    uint32_t colors = fp->fp.colors;
 392    uint32_t clpd_nr = util_last_bit(vp->vp.clip_enable | vp->vp.cull_enable);
 393    uint32_t lin[4];
 394    uint8_t map[64];
 395    uint8_t so_map[64];
 396
 397    if (!(nv50->dirty_3d & (NV50_NEW_3D_VERTPROG |
 398                            NV50_NEW_3D_FRAGPROG |
 399                            NV50_NEW_3D_GMTYPROG))) {
 400       uint8_t bfc, ffc;
 401       ffc = (nv50->state.semantic_color & NV50_3D_SEMANTIC_COLOR_FFC0_ID__MASK);
 402       bfc = (nv50->state.semantic_color & NV50_3D_SEMANTIC_COLOR_BFC0_ID__MASK)
 403          >> 8;
 404       if (nv50->rast->pipe.light_twoside == ((ffc == bfc) ? 0 : 1))
 405          return;
 406    }
 407
 408    memset(lin, 0x00, sizeof(lin));
 409
 410    /* XXX: in buggy-endian mode, is the first element of map (u32)0x000000xx
 411     *  or is it the first byte ?
 412     */
 413    memset(map, nv50->gmtyprog ? 0x80 : 0x40, sizeof(map));
 414
 415    dummy.mask = 0xf; /* map all components of HPOS */
 416    dummy.linear = 0;
 417    m = nv50_vec4_map(map, 0, lin, &dummy, &vp->out[0]);
 418
 419    for (c = 0; c < clpd_nr; ++c)
 420       map[m++] = vp->vp.clpd[c / 4] + (c % 4);
 421
 422    colors |= m << 8; /* adjust BFC0 id */
 423
 424    dummy.mask = 0x0;
 425
 426    /* if light_twoside is active, FFC0_ID == BFC0_ID is invalid */
 427    if (nv50->rast->pipe.light_twoside) {
 428       for (i = 0; i < 2; ++i) {
 429          n = vp->vp.bfc[i];
 430          if (fp->vp.bfc[i] >= fp->in_nr)
 431             continue;
 432          m = nv50_vec4_map(map, m, lin, &fp->in[fp->vp.bfc[i]],
 433                            (n < vp->out_nr) ? &vp->out[n] : &dummy);
 434       }
 435    }
 436    colors += m - 4; /* adjust FFC0 id */
 437    interp |= m << 8; /* set map id where 'normal' FP inputs start */
 438
 439    for (i = 0; i < fp->in_nr; ++i) {
 440       for (n = 0; n < vp->out_nr; ++n)
 441          if (vp->out[n].sn == fp->in[i].sn &&
 442              vp->out[n].si == fp->in[i].si)
 443             break;
 444       switch (fp->in[i].sn) {
 445       case TGSI_SEMANTIC_PRIMID:
 446          primid = m;
 447          break;
 448       case TGSI_SEMANTIC_LAYER:
 449          layerid = m;
 450          break;
 451       case TGSI_SEMANTIC_VIEWPORT_INDEX:
 452          viewportid = m;
 453          break;
 454       }
 455       m = nv50_vec4_map(map, m, lin,
 456                         &fp->in[i], (n < vp->out_nr) ? &vp->out[n] : &dummy);
 457    }
 458
 459    if (vp->gp.has_layer && !layerid) {
 460       layerid = m;
 461       map[m++] = vp->gp.layerid;
 462    }
 463
 464    if (vp->gp.has_viewport && !viewportid) {
 465       viewportid = m;
 466       map[m++] = vp->gp.viewportid;
 467    }
 468
 469    if (nv50->rast->pipe.point_size_per_vertex) {
 470       psiz = (m << 4) | 1;
 471       map[m++] = vp->vp.psiz;
 472    }
 473
 474    if (nv50->rast->pipe.clamp_vertex_color)
 475       colors |= NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 476
 477    if (unlikely(vp->so)) {
 478       /* Slot i in STRMOUT_MAP specifies the offset where slot i in RESULT_MAP
 479        * gets written.
 480        *
 481        * TODO:
 482        * Inverting vp->so->map (output -> offset) would probably speed this up.
 483        */
 484       memset(so_map, 0, sizeof(so_map));
 485       for (i = 0; i < vp->so->map_size; ++i) {
 486          if (vp->so->map[i] == 0xff)
 487             continue;
 488          for (c = 0; c < m; ++c)
 489             if (map[c] == vp->so->map[i] && !so_map[c])
 490                break;
 491          if (c == m) {
 492             c = m;
 493             map[m++] = vp->so->map[i];
 494          }
 495          so_map[c] = 0x80 | i;
 496       }
 497       for (c = m; c & 3; ++c)
 498          so_map[c] = 0;
 499    }
 500
 501    n = (m + 3) / 4;
 502    assert(m <= 64);
 503
 504    if (unlikely(nv50->gmtyprog)) {
 505       BEGIN_NV04(push, NV50_3D(GP_RESULT_MAP_SIZE), 1);
 506       PUSH_DATA (push, m);
 507       BEGIN_NV04(push, NV50_3D(GP_RESULT_MAP(0)), n);
 508       PUSH_DATAp(push, map, n);
 509    } else {
 510       BEGIN_NV04(push, NV50_3D(VP_GP_BUILTIN_ATTR_EN), 1);
 511       PUSH_DATA (push, vp->vp.attrs[2] | fp->vp.attrs[2]);
 512
 513       BEGIN_NV04(push, NV50_3D(SEMANTIC_PRIM_ID), 1);
 514       PUSH_DATA (push, primid);
 515
 516       assert(m > 0);
 517       BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP_SIZE), 1);
 518       PUSH_DATA (push, m);
 519       BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP(0)), n);
 520       PUSH_DATAp(push, map, n);
 521    }
 522
 523    BEGIN_NV04(push, NV50_3D(GP_VIEWPORT_ID_ENABLE), 5);
 524    PUSH_DATA (push, vp->gp.has_viewport);
 525    PUSH_DATA (push, colors);
 526    PUSH_DATA (push, (clpd_nr << 8) | 4);
 527    PUSH_DATA (push, layerid);
 528    PUSH_DATA (push, psiz);
 529
 530    BEGIN_NV04(push, NV50_3D(SEMANTIC_VIEWPORT), 1);
 531    PUSH_DATA (push, viewportid);
 532
 533    BEGIN_NV04(push, NV50_3D(LAYER), 1);
 534    PUSH_DATA (push, vp->gp.has_layer << 16);
 535
 536    BEGIN_NV04(push, NV50_3D(FP_INTERPOLANT_CTRL), 1);
 537    PUSH_DATA (push, interp);
 538
 539    nv50->state.interpolant_ctrl = interp;
 540
 541    nv50->state.semantic_color = colors;
 542    nv50->state.semantic_psize = psiz;
 543
 544    BEGIN_NV04(push, NV50_3D(NOPERSPECTIVE_BITMAP(0)), 4);
 545    PUSH_DATAp(push, lin, 4);
 546
 547    BEGIN_NV04(push, NV50_3D(GP_ENABLE), 1);
 548    PUSH_DATA (push, nv50->gmtyprog ? 1 : 0);
 549
 550    if (vp->so) {
 551       BEGIN_NV04(push, NV50_3D(STRMOUT_MAP(0)), n);
 552       PUSH_DATAp(push, so_map, n);
 553    }
 554 }
 555
 556 static int
 557 nv50_vp_gp_mapping(uint8_t *map, int m,
 558                    struct nv50_program *vp, struct nv50_program *gp)
 559 {
 560    int i, j, c;
 561
 562    for (i = 0; i < gp->in_nr; ++i) {
 563       uint8_t oid = 0, mv = 0, mg = gp->in[i].mask;
 564
 565       for (j = 0; j < vp->out_nr; ++j) {
 566          if (vp->out[j].sn == gp->in[i].sn &&
 567              vp->out[j].si == gp->in[i].si) {
 568             mv = vp->out[j].mask;
 569             oid = vp->out[j].hw;
 570             break;
 571          }
 572       }
 573
 574       for (c = 0; c < 4; ++c, mv >>= 1, mg >>= 1) {
 575          if (mg & mv & 1)
 576             map[m++] = oid;
 577          else
 578          if (mg & 1)
 579             map[m++] = (c == 3) ? 0x41 : 0x40;
 580          oid += mv & 1;
 581       }
 582    }
 583    if (!m)
 584       map[m++] = 0;
 585    return m;
 586 }
 587
 588 void
 589 nv50_gp_linkage_validate(struct nv50_context *nv50)
 590 {
 591    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 592    struct nv50_program *vp = nv50->vertprog;
 593    struct nv50_program *gp = nv50->gmtyprog;
 594    int m = 0;
 595    int n;
 596    uint8_t map[64];
 597
 598    if (!gp)
 599       return;
 600    memset(map, 0, sizeof(map));
 601
 602    m = nv50_vp_gp_mapping(map, m, vp, gp);
 603
 604    n = (m + 3) / 4;
 605
 606    BEGIN_NV04(push, NV50_3D(VP_GP_BUILTIN_ATTR_EN), 1);
 607    PUSH_DATA (push, vp->vp.attrs[2] | gp->vp.attrs[2]);
 608
 609    assert(m > 0);
 610    BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP_SIZE), 1);
 611    PUSH_DATA (push, m);
 612    BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP(0)), n);
 613    PUSH_DATAp(push, map, n);
 614 }
 615
 616 void
 617 nv50_stream_output_validate(struct nv50_context *nv50)
 618 {
 619    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 620    struct nv50_stream_output_state *so;
 621    uint32_t ctrl;
 622    unsigned i;
 623    unsigned prims = ~0;
 624
 625    so = nv50->gmtyprog ? nv50->gmtyprog->so : nv50->vertprog->so;
 626
 627    BEGIN_NV04(push, NV50_3D(STRMOUT_ENABLE), 1);
 628    PUSH_DATA (push, 0);
 629    if (!so || !nv50->num_so_targets) {
 630       if (nv50->screen->base.class_3d < NVA0_3D_CLASS) {
 631          BEGIN_NV04(push, NV50_3D(STRMOUT_PRIMITIVE_LIMIT), 1);
 632          PUSH_DATA (push, 0);
 633       }
 634       BEGIN_NV04(push, NV50_3D(STRMOUT_PARAMS_LATCH), 1);
 635       PUSH_DATA (push, 1);
 636       return;
 637    }
 638
 639    /* previous TFB needs to complete */
 640    if (nv50->screen->base.class_3d < NVA0_3D_CLASS) {
 641       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 642       PUSH_DATA (push, 0);
 643    }
 644
 645    ctrl = so->ctrl;
 646    if (nv50->screen->base.class_3d >= NVA0_3D_CLASS)
 647       ctrl |= NVA0_3D_STRMOUT_BUFFERS_CTRL_LIMIT_MODE_OFFSET;
 648
 649    BEGIN_NV04(push, NV50_3D(STRMOUT_BUFFERS_CTRL), 1);
 650    PUSH_DATA (push, ctrl);
 651
 652    for (i = 0; i < nv50->num_so_targets; ++i) {
 653       struct nv50_so_target *targ = nv50_so_target(nv50->so_target[i]);
 654       struct nv04_resource *buf = nv04_resource(targ->pipe.buffer);
 655
 656       const unsigned n = nv50->screen->base.class_3d >= NVA0_3D_CLASS ? 4 : 3;
 657
 658       if (n == 4 && !targ->clean)
 659          nv84_hw_query_fifo_wait(push, nv50_query(targ->pq));
 660       BEGIN_NV04(push, NV50_3D(STRMOUT_ADDRESS_HIGH(i)), n);
 661       PUSH_DATAh(push, buf->address + targ->pipe.buffer_offset);
 662       PUSH_DATA (push, buf->address + targ->pipe.buffer_offset);
 663       PUSH_DATA (push, so->num_attribs[i]);
 664       if (n == 4) {
 665          PUSH_DATA(push, targ->pipe.buffer_size);
 666          if (!targ->clean) {
 667             assert(targ->pq);
 668             nv50_hw_query_pushbuf_submit(push, NVA0_3D_STRMOUT_OFFSET(i),
 669                                          nv50_query(targ->pq), 0x4);
 670          } else {
 671             BEGIN_NV04(push, NVA0_3D(STRMOUT_OFFSET(i)), 1);
 672             PUSH_DATA(push, 0);
 673             targ->clean = false;
 674          }
 675       } else {
 676          const unsigned limit = targ->pipe.buffer_size /
 677             (so->stride[i] * nv50->state.prim_size);
 678          prims = MIN2(prims, limit);
 679       }
 680       targ->stride = so->stride[i];
 681       BCTX_REFN(nv50->bufctx_3d, 3D_SO, buf, WR);
 682    }
 683    if (prims != ~0) {
 684       BEGIN_NV04(push, NV50_3D(STRMOUT_PRIMITIVE_LIMIT), 1);
 685       PUSH_DATA (push, prims);
 686    }
 687    BEGIN_NV04(push, NV50_3D(STRMOUT_PARAMS_LATCH), 1);
 688    PUSH_DATA (push, 1);
 689    BEGIN_NV04(push, NV50_3D(STRMOUT_ENABLE), 1);
 690    PUSH_DATA (push, 1);
 691 }