src/gallium/drivers/nouveau/nv50/nv50_shader_state.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  * Copyright 2010 Christoph Bumiller
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "pipe/p_context.h"
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28
  29 #include "nv50/nv50_context.h"
  30
  31 void
  32 nv50_constbufs_validate(struct nv50_context *nv50)
  33 {
  34    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  35    unsigned s;
  36
  37    for (s = 0; s < 3; ++s) {
  38       unsigned p;
  39
  40       if (s == PIPE_SHADER_FRAGMENT)
  41          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_FRAGMENT;
  42       else
  43       if (s == PIPE_SHADER_GEOMETRY)
  44          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_GEOMETRY;
  45       else
  46          p = NV50_3D_SET_PROGRAM_CB_PROGRAM_VERTEX;
  47
  48       while (nv50->constbuf_dirty[s]) {
  49          const unsigned i = (unsigned)ffs(nv50->constbuf_dirty[s]) - 1;
  50
  51          assert(i < NV50_MAX_PIPE_CONSTBUFS);
  52          nv50->constbuf_dirty[s] &= ~(1 << i);
  53
  54          if (nv50->constbuf[s][i].user) {
  55             const unsigned b = NV50_CB_PVP + s;
  56             unsigned start = 0;
  57             unsigned words = nv50->constbuf[s][0].size / 4;
  58             if (i) {
  59                NOUVEAU_ERR("user constbufs only supported in slot 0\n");
  60                continue;
  61             }
  62             if (!nv50->state.uniform_buffer_bound[s]) {
  63                nv50->state.uniform_buffer_bound[s] = true;
  64                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
  65                PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
  66             }
  67             while (words) {
  68                unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
  69
  70                PUSH_SPACE(push, nr + 3);
  71                BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
  72                PUSH_DATA (push, (start << 8) | b);
  73                BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
  74                PUSH_DATAp(push, &nv50->constbuf[s][0].u.data[start * 4], nr);
  75
  76                start += nr;
  77                words -= nr;
  78             }
  79          } else {
  80             struct nv04_resource *res =
  81                nv04_resource(nv50->constbuf[s][i].u.buf);
  82             if (res) {
  83                /* TODO: allocate persistent bindings */
  84                const unsigned b = s * 16 + i;
  85
  86                assert(nouveau_resource_mapped_by_gpu(&res->base));
  87
  88                BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
  89                PUSH_DATAh(push, res->address + nv50->constbuf[s][i].offset);
  90                PUSH_DATA (push, res->address + nv50->constbuf[s][i].offset);
  91                PUSH_DATA (push, (b << 16) |
  92                           (nv50->constbuf[s][i].size & 0xffff));
  93                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
  94                PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
  95
  96                BCTX_REFN(nv50->bufctx_3d, CB(s, i), res, RD);
  97
  98                nv50->cb_dirty = 1; /* Force cache flush for UBO. */
  99             } else {
 100                BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
 101                PUSH_DATA (push, (i << 8) | p | 0);
 102             }
 103             if (i == 0)
 104                nv50->state.uniform_buffer_bound[s] = false;
 105          }
 106       }
 107    }
 108 }
 109
 110 static bool
 111 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *prog)
 112 {
 113    if (!prog->translated) {
 114       prog->translated = nv50_program_translate(
 115          prog, nv50->screen->base.device->chipset);
 116       if (!prog->translated)
 117          return false;
 118    } else
 119    if (prog->mem)
 120       return true;
 121
 122    return nv50_program_upload_code(nv50, prog);
 123 }
 124
 125 static inline void
 126 nv50_program_update_context_state(struct nv50_context *nv50,
 127                                   struct nv50_program *prog, int stage)
 128 {
 129    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR;
 130
 131    if (prog && prog->tls_space) {
 132       if (nv50->state.new_tls_space)
 133          nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TLS);
 134       if (!nv50->state.tls_required || nv50->state.new_tls_space)
 135          BCTX_REFN_bo(nv50->bufctx_3d, TLS, flags, nv50->screen->tls_bo);
 136       nv50->state.new_tls_space = false;
 137       nv50->state.tls_required |= 1 << stage;
 138    } else {
 139       if (nv50->state.tls_required == (1 << stage))
 140          nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TLS);
 141       nv50->state.tls_required &= ~(1 << stage);
 142    }
 143 }
 144
 145 void
 146 nv50_vertprog_validate(struct nv50_context *nv50)
 147 {
 148    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 149    struct nv50_program *vp = nv50->vertprog;
 150
 151    if (!nv50_program_validate(nv50, vp))
 152          return;
 153    nv50_program_update_context_state(nv50, vp, 0);
 154
 155    BEGIN_NV04(push, NV50_3D(VP_ATTR_EN(0)), 2);
 156    PUSH_DATA (push, vp->vp.attrs[0]);
 157    PUSH_DATA (push, vp->vp.attrs[1]);
 158    BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_RESULT), 1);
 159    PUSH_DATA (push, vp->max_out);
 160    BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_TEMP), 1);
 161    PUSH_DATA (push, vp->max_gpr);
 162    BEGIN_NV04(push, NV50_3D(VP_START_ID), 1);
 163    PUSH_DATA (push, vp->code_base);
 164 }
 165
 166 void
 167 nv50_fragprog_validate(struct nv50_context *nv50)
 168 {
 169    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 170    struct nv50_program *fp = nv50->fragprog;
 171
 172    fp->fp.sample_interp = nv50->min_samples > 1;
 173
 174    if (!nv50_program_validate(nv50, fp))
 175          return;
 176    nv50_program_update_context_state(nv50, fp, 1);
 177
 178    BEGIN_NV04(push, NV50_3D(FP_REG_ALLOC_TEMP), 1);
 179    PUSH_DATA (push, fp->max_gpr);
 180    BEGIN_NV04(push, NV50_3D(FP_RESULT_COUNT), 1);
 181    PUSH_DATA (push, fp->max_out);
 182    BEGIN_NV04(push, NV50_3D(FP_CONTROL), 1);
 183    PUSH_DATA (push, fp->fp.flags[0]);
 184    BEGIN_NV04(push, NV50_3D(FP_CTRL_UNK196C), 1);
 185    PUSH_DATA (push, fp->fp.flags[1]);
 186    BEGIN_NV04(push, NV50_3D(FP_START_ID), 1);
 187    PUSH_DATA (push, fp->code_base);
 188
 189    if (nv50->screen->tesla->oclass >= NVA3_3D_CLASS) {
 190       BEGIN_NV04(push, SUBC_3D(NVA3_3D_FP_MULTISAMPLE), 1);
 191       if (nv50->min_samples > 1 || fp->fp.has_samplemask)
 192          PUSH_DATA(push,
 193                    NVA3_3D_FP_MULTISAMPLE_FORCE_PER_SAMPLE |
 194                    (NVA3_3D_FP_MULTISAMPLE_EXPORT_SAMPLE_MASK *
 195                     fp->fp.has_samplemask));
 196       else
 197          PUSH_DATA(push, 0);
 198    }
 199 }
 200
 201 void
 202 nv50_gmtyprog_validate(struct nv50_context *nv50)
 203 {
 204    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 205    struct nv50_program *gp = nv50->gmtyprog;
 206
 207    if (gp) {
 208       if (!nv50_program_validate(nv50, gp))
 209          return;
 210       BEGIN_NV04(push, NV50_3D(GP_REG_ALLOC_TEMP), 1);
 211       PUSH_DATA (push, gp->max_gpr);
 212       BEGIN_NV04(push, NV50_3D(GP_REG_ALLOC_RESULT), 1);
 213       PUSH_DATA (push, gp->max_out);
 214       BEGIN_NV04(push, NV50_3D(GP_OUTPUT_PRIMITIVE_TYPE), 1);
 215       PUSH_DATA (push, gp->gp.prim_type);
 216       BEGIN_NV04(push, NV50_3D(GP_VERTEX_OUTPUT_COUNT), 1);
 217       PUSH_DATA (push, gp->gp.vert_count);
 218       BEGIN_NV04(push, NV50_3D(GP_START_ID), 1);
 219       PUSH_DATA (push, gp->code_base);
 220
 221       nv50->state.prim_size = gp->gp.prim_type; /* enum matches vertex count */
 222    }
 223    nv50_program_update_context_state(nv50, gp, 2);
 224
 225    /* GP_ENABLE is updated in linkage validation */
 226 }
 227
 228 static void
 229 nv50_sprite_coords_validate(struct nv50_context *nv50)
 230 {
 231    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 232    uint32_t pntc[8], mode;
 233    struct nv50_program *fp = nv50->fragprog;
 234    unsigned i, c;
 235    unsigned m = (nv50->state.interpolant_ctrl >> 8) & 0xff;
 236
 237    if (!nv50->rast->pipe.point_quad_rasterization) {
 238       if (nv50->state.point_sprite) {
 239          BEGIN_NV04(push, NV50_3D(POINT_COORD_REPLACE_MAP(0)), 8);
 240          for (i = 0; i < 8; ++i)
 241             PUSH_DATA(push, 0);
 242
 243          nv50->state.point_sprite = false;
 244       }
 245       return;
 246    } else {
 247       nv50->state.point_sprite = true;
 248    }
 249
 250    memset(pntc, 0, sizeof(pntc));
 251
 252    for (i = 0; i < fp->in_nr; i++) {
 253       unsigned n = util_bitcount(fp->in[i].mask);
 254
 255       if (fp->in[i].sn != TGSI_SEMANTIC_GENERIC) {
 256          m += n;
 257          continue;
 258       }
 259       if (!(nv50->rast->pipe.sprite_coord_enable & (1 << fp->in[i].si))) {
 260          m += n;
 261          continue;
 262       }
 263
 264       for (c = 0; c < 4; ++c) {
 265          if (fp->in[i].mask & (1 << c)) {
 266             pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
 267             ++m;
 268          }
 269       }
 270    }
 271
 272    if (nv50->rast->pipe.sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT)
 273       mode = 0x00;
 274    else
 275       mode = 0x10;
 276
 277    BEGIN_NV04(push, NV50_3D(POINT_SPRITE_CTRL), 1);
 278    PUSH_DATA (push, mode);
 279
 280    BEGIN_NV04(push, NV50_3D(POINT_COORD_REPLACE_MAP(0)), 8);
 281    PUSH_DATAp(push, pntc, 8);
 282 }
 283
 284 /* Validate state derived from shaders and the rasterizer cso. */
 285 void
 286 nv50_validate_derived_rs(struct nv50_context *nv50)
 287 {
 288    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 289    uint32_t color, psize;
 290
 291    nv50_sprite_coords_validate(nv50);
 292
 293    if (nv50->state.rasterizer_discard != nv50->rast->pipe.rasterizer_discard) {
 294       nv50->state.rasterizer_discard = nv50->rast->pipe.rasterizer_discard;
 295       BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 296       PUSH_DATA (push, !nv50->rast->pipe.rasterizer_discard);
 297    }
 298
 299    if (nv50->dirty & NV50_NEW_FRAGPROG)
 300       return;
 301    psize = nv50->state.semantic_psize & ~NV50_3D_SEMANTIC_PTSZ_PTSZ_EN__MASK;
 302    color = nv50->state.semantic_color & ~NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 303
 304    if (nv50->rast->pipe.clamp_vertex_color)
 305       color |= NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 306
 307    if (color != nv50->state.semantic_color) {
 308       nv50->state.semantic_color = color;
 309       BEGIN_NV04(push, NV50_3D(SEMANTIC_COLOR), 1);
 310       PUSH_DATA (push, color);
 311    }
 312
 313    if (nv50->rast->pipe.point_size_per_vertex)
 314       psize |= NV50_3D_SEMANTIC_PTSZ_PTSZ_EN__MASK;
 315
 316    if (psize != nv50->state.semantic_psize) {
 317       nv50->state.semantic_psize = psize;
 318       BEGIN_NV04(push, NV50_3D(SEMANTIC_PTSZ), 1);
 319       PUSH_DATA (push, psize);
 320    }
 321 }
 322
 323 static int
 324 nv50_vec4_map(uint8_t *map, int mid, uint32_t lin[4],
 325               struct nv50_varying *in, struct nv50_varying *out)
 326 {
 327    int c;
 328    uint8_t mv = out->mask, mf = in->mask, oid = out->hw;
 329
 330    for (c = 0; c < 4; ++c) {
 331       if (mf & 1) {
 332          if (in->linear)
 333             lin[mid / 32] |= 1 << (mid % 32);
 334          if (mv & 1)
 335             map[mid] = oid;
 336          else
 337          if (c == 3)
 338             map[mid] |= 1;
 339          ++mid;
 340       }
 341
 342       oid += mv & 1;
 343       mf >>= 1;
 344       mv >>= 1;
 345    }
 346
 347    return mid;
 348 }
 349
 350 void
 351 nv50_fp_linkage_validate(struct nv50_context *nv50)
 352 {
 353    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 354    struct nv50_program *vp = nv50->gmtyprog ? nv50->gmtyprog : nv50->vertprog;
 355    struct nv50_program *fp = nv50->fragprog;
 356    struct nv50_varying dummy;
 357    int i, n, c, m;
 358    uint32_t primid = 0;
 359    uint32_t layerid = 0;
 360    uint32_t viewportid = 0;
 361    uint32_t psiz = 0x000;
 362    uint32_t interp = fp->fp.interp;
 363    uint32_t colors = fp->fp.colors;
 364    uint32_t lin[4];
 365    uint8_t map[64];
 366    uint8_t so_map[64];
 367
 368    if (!(nv50->dirty & (NV50_NEW_VERTPROG |
 369                         NV50_NEW_FRAGPROG |
 370                         NV50_NEW_GMTYPROG))) {
 371       uint8_t bfc, ffc;
 372       ffc = (nv50->state.semantic_color & NV50_3D_SEMANTIC_COLOR_FFC0_ID__MASK);
 373       bfc = (nv50->state.semantic_color & NV50_3D_SEMANTIC_COLOR_BFC0_ID__MASK)
 374          >> 8;
 375       if (nv50->rast->pipe.light_twoside == ((ffc == bfc) ? 0 : 1))
 376          return;
 377    }
 378
 379    memset(lin, 0x00, sizeof(lin));
 380
 381    /* XXX: in buggy-endian mode, is the first element of map (u32)0x000000xx
 382     *  or is it the first byte ?
 383     */
 384    memset(map, nv50->gmtyprog ? 0x80 : 0x40, sizeof(map));
 385
 386    dummy.mask = 0xf; /* map all components of HPOS */
 387    dummy.linear = 0;
 388    m = nv50_vec4_map(map, 0, lin, &dummy, &vp->out[0]);
 389
 390    for (c = 0; c < vp->vp.clpd_nr; ++c)
 391       map[m++] = vp->vp.clpd[c / 4] + (c % 4);
 392
 393    colors |= m << 8; /* adjust BFC0 id */
 394
 395    dummy.mask = 0x0;
 396
 397    /* if light_twoside is active, FFC0_ID == BFC0_ID is invalid */
 398    if (nv50->rast->pipe.light_twoside) {
 399       for (i = 0; i < 2; ++i) {
 400          n = vp->vp.bfc[i];
 401          if (fp->vp.bfc[i] >= fp->in_nr)
 402             continue;
 403          m = nv50_vec4_map(map, m, lin, &fp->in[fp->vp.bfc[i]],
 404                            (n < vp->out_nr) ? &vp->out[n] : &dummy);
 405       }
 406    }
 407    colors += m - 4; /* adjust FFC0 id */
 408    interp |= m << 8; /* set map id where 'normal' FP inputs start */
 409
 410    for (i = 0; i < fp->in_nr; ++i) {
 411       for (n = 0; n < vp->out_nr; ++n)
 412          if (vp->out[n].sn == fp->in[i].sn &&
 413              vp->out[n].si == fp->in[i].si)
 414             break;
 415       switch (fp->in[i].sn) {
 416       case TGSI_SEMANTIC_PRIMID:
 417          primid = m;
 418          break;
 419       case TGSI_SEMANTIC_LAYER:
 420          layerid = m;
 421          break;
 422       case TGSI_SEMANTIC_VIEWPORT_INDEX:
 423          viewportid = m;
 424          break;
 425       }
 426       m = nv50_vec4_map(map, m, lin,
 427                         &fp->in[i], (n < vp->out_nr) ? &vp->out[n] : &dummy);
 428    }
 429
 430    if (vp->gp.has_layer && !layerid) {
 431       layerid = m;
 432       map[m++] = vp->gp.layerid;
 433    }
 434
 435    if (vp->gp.has_viewport && !viewportid) {
 436       viewportid = m;
 437       map[m++] = vp->gp.viewportid;
 438    }
 439
 440    if (nv50->rast->pipe.point_size_per_vertex) {
 441       psiz = (m << 4) | 1;
 442       map[m++] = vp->vp.psiz;
 443    }
 444
 445    if (nv50->rast->pipe.clamp_vertex_color)
 446       colors |= NV50_3D_SEMANTIC_COLOR_CLMP_EN;
 447
 448    if (unlikely(vp->so)) {
 449       /* Slot i in STRMOUT_MAP specifies the offset where slot i in RESULT_MAP
 450        * gets written.
 451        *
 452        * TODO:
 453        * Inverting vp->so->map (output -> offset) would probably speed this up.
 454        */
 455       memset(so_map, 0, sizeof(so_map));
 456       for (i = 0; i < vp->so->map_size; ++i) {
 457          if (vp->so->map[i] == 0xff)
 458             continue;
 459          for (c = 0; c < m; ++c)
 460             if (map[c] == vp->so->map[i] && !so_map[c])
 461                break;
 462          if (c == m) {
 463             c = m;
 464             map[m++] = vp->so->map[i];
 465          }
 466          so_map[c] = 0x80 | i;
 467       }
 468       for (c = m; c & 3; ++c)
 469          so_map[c] = 0;
 470    }
 471
 472    n = (m + 3) / 4;
 473    assert(m <= 64);
 474
 475    if (unlikely(nv50->gmtyprog)) {
 476       BEGIN_NV04(push, NV50_3D(GP_RESULT_MAP_SIZE), 1);
 477       PUSH_DATA (push, m);
 478       BEGIN_NV04(push, NV50_3D(GP_RESULT_MAP(0)), n);
 479       PUSH_DATAp(push, map, n);
 480    } else {
 481       BEGIN_NV04(push, NV50_3D(VP_GP_BUILTIN_ATTR_EN), 1);
 482       PUSH_DATA (push, vp->vp.attrs[2] | fp->vp.attrs[2]);
 483
 484       BEGIN_NV04(push, NV50_3D(SEMANTIC_PRIM_ID), 1);
 485       PUSH_DATA (push, primid);
 486
 487       assert(m > 0);
 488       BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP_SIZE), 1);
 489       PUSH_DATA (push, m);
 490       BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP(0)), n);
 491       PUSH_DATAp(push, map, n);
 492    }
 493
 494    BEGIN_NV04(push, NV50_3D(GP_VIEWPORT_ID_ENABLE), 5);
 495    PUSH_DATA (push, vp->gp.has_viewport);
 496    PUSH_DATA (push, colors);
 497    PUSH_DATA (push, (vp->vp.clpd_nr << 8) | 4);
 498    PUSH_DATA (push, layerid);
 499    PUSH_DATA (push, psiz);
 500
 501    BEGIN_NV04(push, NV50_3D(SEMANTIC_VIEWPORT), 1);
 502    PUSH_DATA (push, viewportid);
 503
 504    BEGIN_NV04(push, NV50_3D(LAYER), 1);
 505    PUSH_DATA (push, vp->gp.has_layer << 16);
 506
 507    BEGIN_NV04(push, NV50_3D(FP_INTERPOLANT_CTRL), 1);
 508    PUSH_DATA (push, interp);
 509
 510    nv50->state.interpolant_ctrl = interp;
 511
 512    nv50->state.semantic_color = colors;
 513    nv50->state.semantic_psize = psiz;
 514
 515    BEGIN_NV04(push, NV50_3D(NOPERSPECTIVE_BITMAP(0)), 4);
 516    PUSH_DATAp(push, lin, 4);
 517
 518    BEGIN_NV04(push, NV50_3D(GP_ENABLE), 1);
 519    PUSH_DATA (push, nv50->gmtyprog ? 1 : 0);
 520
 521    if (vp->so) {
 522       BEGIN_NV04(push, NV50_3D(STRMOUT_MAP(0)), n);
 523       PUSH_DATAp(push, so_map, n);
 524    }
 525 }
 526
 527 static int
 528 nv50_vp_gp_mapping(uint8_t *map, int m,
 529                    struct nv50_program *vp, struct nv50_program *gp)
 530 {
 531    int i, j, c;
 532
 533    for (i = 0; i < gp->in_nr; ++i) {
 534       uint8_t oid = 0, mv = 0, mg = gp->in[i].mask;
 535
 536       for (j = 0; j < vp->out_nr; ++j) {
 537          if (vp->out[j].sn == gp->in[i].sn &&
 538              vp->out[j].si == gp->in[i].si) {
 539             mv = vp->out[j].mask;
 540             oid = vp->out[j].hw;
 541             break;
 542          }
 543       }
 544
 545       for (c = 0; c < 4; ++c, mv >>= 1, mg >>= 1) {
 546          if (mg & mv & 1)
 547             map[m++] = oid;
 548          else
 549          if (mg & 1)
 550             map[m++] = (c == 3) ? 0x41 : 0x40;
 551          oid += mv & 1;
 552       }
 553    }
 554    if (!m)
 555       map[m++] = 0;
 556    return m;
 557 }
 558
 559 void
 560 nv50_gp_linkage_validate(struct nv50_context *nv50)
 561 {
 562    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 563    struct nv50_program *vp = nv50->vertprog;
 564    struct nv50_program *gp = nv50->gmtyprog;
 565    int m = 0;
 566    int n;
 567    uint8_t map[64];
 568
 569    if (!gp)
 570       return;
 571    memset(map, 0, sizeof(map));
 572
 573    m = nv50_vp_gp_mapping(map, m, vp, gp);
 574
 575    n = (m + 3) / 4;
 576
 577    BEGIN_NV04(push, NV50_3D(VP_GP_BUILTIN_ATTR_EN), 1);
 578    PUSH_DATA (push, vp->vp.attrs[2] | gp->vp.attrs[2]);
 579
 580    assert(m > 0);
 581    BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP_SIZE), 1);
 582    PUSH_DATA (push, m);
 583    BEGIN_NV04(push, NV50_3D(VP_RESULT_MAP(0)), n);
 584    PUSH_DATAp(push, map, n);
 585 }
 586
 587 void
 588 nv50_stream_output_validate(struct nv50_context *nv50)
 589 {
 590    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 591    struct nv50_stream_output_state *so;
 592    uint32_t ctrl;
 593    unsigned i;
 594    unsigned prims = ~0;
 595
 596    so = nv50->gmtyprog ? nv50->gmtyprog->so : nv50->vertprog->so;
 597
 598    BEGIN_NV04(push, NV50_3D(STRMOUT_ENABLE), 1);
 599    PUSH_DATA (push, 0);
 600    if (!so || !nv50->num_so_targets) {
 601       if (nv50->screen->base.class_3d < NVA0_3D_CLASS) {
 602          BEGIN_NV04(push, NV50_3D(STRMOUT_PRIMITIVE_LIMIT), 1);
 603          PUSH_DATA (push, 0);
 604       }
 605       BEGIN_NV04(push, NV50_3D(STRMOUT_PARAMS_LATCH), 1);
 606       PUSH_DATA (push, 1);
 607       return;
 608    }
 609
 610    /* previous TFB needs to complete */
 611    if (nv50->screen->base.class_3d < NVA0_3D_CLASS) {
 612       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 613       PUSH_DATA (push, 0);
 614    }
 615
 616    ctrl = so->ctrl;
 617    if (nv50->screen->base.class_3d >= NVA0_3D_CLASS)
 618       ctrl |= NVA0_3D_STRMOUT_BUFFERS_CTRL_LIMIT_MODE_OFFSET;
 619
 620    BEGIN_NV04(push, NV50_3D(STRMOUT_BUFFERS_CTRL), 1);
 621    PUSH_DATA (push, ctrl);
 622
 623    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_SO);
 624
 625    for (i = 0; i < nv50->num_so_targets; ++i) {
 626       struct nv50_so_target *targ = nv50_so_target(nv50->so_target[i]);
 627       struct nv04_resource *buf = nv04_resource(targ->pipe.buffer);
 628
 629       const unsigned n = nv50->screen->base.class_3d >= NVA0_3D_CLASS ? 4 : 3;
 630
 631       if (n == 4 && !targ->clean)
 632          nv84_query_fifo_wait(push, targ->pq);
 633       BEGIN_NV04(push, NV50_3D(STRMOUT_ADDRESS_HIGH(i)), n);
 634       PUSH_DATAh(push, buf->address + targ->pipe.buffer_offset);
 635       PUSH_DATA (push, buf->address + targ->pipe.buffer_offset);
 636       PUSH_DATA (push, so->num_attribs[i]);
 637       if (n == 4) {
 638          PUSH_DATA(push, targ->pipe.buffer_size);
 639          if (!targ->clean) {
 640             assert(targ->pq);
 641             nv50_query_pushbuf_submit(push, NVA0_3D_STRMOUT_OFFSET(i),
 642                                       targ->pq, 0x4);
 643          } else {
 644             BEGIN_NV04(push, NVA0_3D(STRMOUT_OFFSET(i)), 1);
 645             PUSH_DATA(push, 0);
 646             targ->clean = false;
 647          }
 648       } else {
 649          const unsigned limit = targ->pipe.buffer_size /
 650             (so->stride[i] * nv50->state.prim_size);
 651          prims = MIN2(prims, limit);
 652       }
 653       targ->stride = so->stride[i];
 654       BCTX_REFN(nv50->bufctx_3d, SO, buf, WR);
 655    }
 656    if (prims != ~0) {
 657       BEGIN_NV04(push, NV50_3D(STRMOUT_PRIMITIVE_LIMIT), 1);
 658       PUSH_DATA (push, prims);
 659    }
 660    BEGIN_NV04(push, NV50_3D(STRMOUT_PARAMS_LATCH), 1);
 661    PUSH_DATA (push, 1);
 662    BEGIN_NV04(push, NV50_3D(STRMOUT_ENABLE), 1);
 663    PUSH_DATA (push, 1);
 664 }