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nv50: reinstate dedicated constbuf push path
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28 #include "util/format_srgb.h"
29
30 #include "tgsi/tgsi_parse.h"
31
32 #include "nv50/nv50_stateobj.h"
33 #include "nv50/nv50_context.h"
34 #include "nv50/nv50_query_hw.h"
35
36 #include "nv50/nv50_3d.xml.h"
37 #include "nv50/g80_texture.xml.h"
38
39 #include "nouveau_gldefs.h"
40
41 /* Caveats:
42 * ! pipe_sampler_state.normalized_coords is ignored - rectangle textures will
43 * use non-normalized coordinates, everything else won't
44 * (The relevant bit is in the TIC entry and not the TSC entry.)
45 *
46 * ! pipe_sampler_state.seamless_cube_map is ignored - seamless filtering is
47 * always activated on NVA0 +
48 * (Give me the global bit, otherwise it's not worth the CPU work.)
49 *
50 * ! pipe_sampler_state.border_color is not swizzled according to the texture
51 * swizzle in pipe_sampler_view
52 * (This will be ugly with indirect independent texture/sampler access,
53 * we'd have to emulate the logic in the shader. GL doesn't have that,
54 * D3D doesn't have swizzle, if we knew what we were implementing we'd be
55 * good.)
56 *
57 * ! pipe_rasterizer_state.line_last_pixel is ignored - it is never drawn
58 *
59 * ! pipe_rasterizer_state.flatshade_first also applies to QUADS
60 * (There's a GL query for that, forcing an exception is just ridiculous.)
61 *
62 * ! pipe_rasterizer_state.sprite_coord_enable is masked with 0xff on NVC0
63 * (The hardware only has 8 slots meant for TexCoord and we have to assign
64 * in advance to maintain elegant separate shader objects.)
65 */
66
67 static inline uint32_t
68 nv50_colormask(unsigned mask)
69 {
70 uint32_t ret = 0;
71
72 if (mask & PIPE_MASK_R)
73 ret |= 0x0001;
74 if (mask & PIPE_MASK_G)
75 ret |= 0x0010;
76 if (mask & PIPE_MASK_B)
77 ret |= 0x0100;
78 if (mask & PIPE_MASK_A)
79 ret |= 0x1000;
80
81 return ret;
82 }
83
84 #define NV50_BLEND_FACTOR_CASE(a, b) \
85 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
86
87 static inline uint32_t
88 nv50_blend_fac(unsigned factor)
89 {
90 switch (factor) {
91 NV50_BLEND_FACTOR_CASE(ONE, ONE);
92 NV50_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
93 NV50_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
94 NV50_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
95 NV50_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
96 NV50_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
97 NV50_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
98 NV50_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
99 NV50_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
100 NV50_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
101 NV50_BLEND_FACTOR_CASE(ZERO, ZERO);
102 NV50_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
103 NV50_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
104 NV50_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
105 NV50_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
106 NV50_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
107 NV50_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
108 NV50_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
109 NV50_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
110 default:
111 return NV50_BLEND_FACTOR_ZERO;
112 }
113 }
114
115 static void *
116 nv50_blend_state_create(struct pipe_context *pipe,
117 const struct pipe_blend_state *cso)
118 {
119 struct nv50_blend_stateobj *so = CALLOC_STRUCT(nv50_blend_stateobj);
120 int i;
121 bool emit_common_func = cso->rt[0].blend_enable;
122
123 if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
124 SB_BEGIN_3D(so, BLEND_INDEPENDENT, 1);
125 SB_DATA (so, cso->independent_blend_enable);
126 }
127
128 so->pipe = *cso;
129
130 SB_BEGIN_3D(so, COLOR_MASK_COMMON, 1);
131 SB_DATA (so, !cso->independent_blend_enable);
132
133 SB_BEGIN_3D(so, BLEND_ENABLE_COMMON, 1);
134 SB_DATA (so, !cso->independent_blend_enable);
135
136 if (cso->independent_blend_enable) {
137 SB_BEGIN_3D(so, BLEND_ENABLE(0), 8);
138 for (i = 0; i < 8; ++i) {
139 SB_DATA(so, cso->rt[i].blend_enable);
140 if (cso->rt[i].blend_enable)
141 emit_common_func = true;
142 }
143
144 if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
145 emit_common_func = false;
146
147 for (i = 0; i < 8; ++i) {
148 if (!cso->rt[i].blend_enable)
149 continue;
150 SB_BEGIN_3D_(so, NVA3_3D_IBLEND_EQUATION_RGB(i), 6);
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
152 SB_DATA (so, nv50_blend_fac(cso->rt[i].rgb_src_factor));
153 SB_DATA (so, nv50_blend_fac(cso->rt[i].rgb_dst_factor));
154 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
155 SB_DATA (so, nv50_blend_fac(cso->rt[i].alpha_src_factor));
156 SB_DATA (so, nv50_blend_fac(cso->rt[i].alpha_dst_factor));
157 }
158 }
159 } else {
160 SB_BEGIN_3D(so, BLEND_ENABLE(0), 1);
161 SB_DATA (so, cso->rt[0].blend_enable);
162 }
163
164 if (emit_common_func) {
165 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
166 SB_DATA (so, nvgl_blend_eqn(cso->rt[0].rgb_func));
167 SB_DATA (so, nv50_blend_fac(cso->rt[0].rgb_src_factor));
168 SB_DATA (so, nv50_blend_fac(cso->rt[0].rgb_dst_factor));
169 SB_DATA (so, nvgl_blend_eqn(cso->rt[0].alpha_func));
170 SB_DATA (so, nv50_blend_fac(cso->rt[0].alpha_src_factor));
171 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
172 SB_DATA (so, nv50_blend_fac(cso->rt[0].alpha_dst_factor));
173 }
174
175 if (cso->logicop_enable) {
176 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
177 SB_DATA (so, 1);
178 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
179 } else {
180 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 1);
181 SB_DATA (so, 0);
182 }
183
184 if (cso->independent_blend_enable) {
185 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
186 for (i = 0; i < 8; ++i)
187 SB_DATA(so, nv50_colormask(cso->rt[i].colormask));
188 } else {
189 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
190 SB_DATA (so, nv50_colormask(cso->rt[0].colormask));
191 }
192
193 assert(so->size <= ARRAY_SIZE(so->state));
194 return so;
195 }
196
197 static void
198 nv50_blend_state_bind(struct pipe_context *pipe, void *hwcso)
199 {
200 struct nv50_context *nv50 = nv50_context(pipe);
201
202 nv50->blend = hwcso;
203 nv50->dirty_3d |= NV50_NEW_3D_BLEND;
204 }
205
206 static void
207 nv50_blend_state_delete(struct pipe_context *pipe, void *hwcso)
208 {
209 FREE(hwcso);
210 }
211
212 /* NOTE: ignoring line_last_pixel */
213 static void *
214 nv50_rasterizer_state_create(struct pipe_context *pipe,
215 const struct pipe_rasterizer_state *cso)
216 {
217 struct nv50_rasterizer_stateobj *so;
218 uint32_t reg;
219
220 so = CALLOC_STRUCT(nv50_rasterizer_stateobj);
221 if (!so)
222 return NULL;
223 so->pipe = *cso;
224
225 #ifndef NV50_SCISSORS_CLIPPING
226 for (int i = 0; i < NV50_MAX_VIEWPORTS; i++) {
227 SB_BEGIN_3D(so, SCISSOR_ENABLE(i), 1);
228 SB_DATA (so, cso->scissor);
229 }
230 #endif
231
232 SB_BEGIN_3D(so, SHADE_MODEL, 1);
233 SB_DATA (so, cso->flatshade ? NV50_3D_SHADE_MODEL_FLAT :
234 NV50_3D_SHADE_MODEL_SMOOTH);
235 SB_BEGIN_3D(so, PROVOKING_VERTEX_LAST, 1);
236 SB_DATA (so, !cso->flatshade_first);
237 SB_BEGIN_3D(so, VERTEX_TWO_SIDE_ENABLE, 1);
238 SB_DATA (so, cso->light_twoside);
239
240 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
241 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
242
243 SB_BEGIN_3D(so, MULTISAMPLE_ENABLE, 1);
244 SB_DATA (so, cso->multisample);
245
246 SB_BEGIN_3D(so, LINE_WIDTH, 1);
247 SB_DATA (so, fui(cso->line_width));
248 SB_BEGIN_3D(so, LINE_SMOOTH_ENABLE, 1);
249 SB_DATA (so, cso->line_smooth);
250
251 SB_BEGIN_3D(so, LINE_STIPPLE_ENABLE, 1);
252 if (cso->line_stipple_enable) {
253 SB_DATA (so, 1);
254 SB_BEGIN_3D(so, LINE_STIPPLE, 1);
255 SB_DATA (so, (cso->line_stipple_pattern << 8) |
256 cso->line_stipple_factor);
257 } else {
258 SB_DATA (so, 0);
259 }
260
261 if (!cso->point_size_per_vertex) {
262 SB_BEGIN_3D(so, POINT_SIZE, 1);
263 SB_DATA (so, fui(cso->point_size));
264 }
265 SB_BEGIN_3D(so, POINT_SPRITE_ENABLE, 1);
266 SB_DATA (so, cso->point_quad_rasterization);
267 SB_BEGIN_3D(so, POINT_SMOOTH_ENABLE, 1);
268 SB_DATA (so, cso->point_smooth);
269
270 SB_BEGIN_3D(so, POLYGON_MODE_FRONT, 3);
271 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
272 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
273 SB_DATA (so, cso->poly_smooth);
274
275 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
276 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
277 SB_DATA (so, cso->front_ccw ? NV50_3D_FRONT_FACE_CCW :
278 NV50_3D_FRONT_FACE_CW);
279 switch (cso->cull_face) {
280 case PIPE_FACE_FRONT_AND_BACK:
281 SB_DATA(so, NV50_3D_CULL_FACE_FRONT_AND_BACK);
282 break;
283 case PIPE_FACE_FRONT:
284 SB_DATA(so, NV50_3D_CULL_FACE_FRONT);
285 break;
286 case PIPE_FACE_BACK:
287 default:
288 SB_DATA(so, NV50_3D_CULL_FACE_BACK);
289 break;
290 }
291
292 SB_BEGIN_3D(so, POLYGON_STIPPLE_ENABLE, 1);
293 SB_DATA (so, cso->poly_stipple_enable);
294 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
295 SB_DATA (so, cso->offset_point);
296 SB_DATA (so, cso->offset_line);
297 SB_DATA (so, cso->offset_tri);
298
299 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
300 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
301 SB_DATA (so, fui(cso->offset_scale));
302 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
303 SB_DATA (so, fui(cso->offset_units * 2.0f));
304 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
305 SB_DATA (so, fui(cso->offset_clamp));
306 }
307
308 if (cso->depth_clip) {
309 reg = 0;
310 } else {
311 reg =
312 NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
313 NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
314 NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
315 }
316 #ifndef NV50_SCISSORS_CLIPPING
317 reg |=
318 NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK7 |
319 NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
320 #endif
321 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
322 SB_DATA (so, reg);
323
324 SB_BEGIN_3D(so, DEPTH_CLIP_NEGATIVE_Z, 1);
325 SB_DATA (so, cso->clip_halfz);
326
327 SB_BEGIN_3D(so, PIXEL_CENTER_INTEGER, 1);
328 SB_DATA (so, !cso->half_pixel_center);
329
330 assert(so->size <= ARRAY_SIZE(so->state));
331 return (void *)so;
332 }
333
334 static void
335 nv50_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
336 {
337 struct nv50_context *nv50 = nv50_context(pipe);
338
339 nv50->rast = hwcso;
340 nv50->dirty_3d |= NV50_NEW_3D_RASTERIZER;
341 }
342
343 static void
344 nv50_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
345 {
346 FREE(hwcso);
347 }
348
349 static void *
350 nv50_zsa_state_create(struct pipe_context *pipe,
351 const struct pipe_depth_stencil_alpha_state *cso)
352 {
353 struct nv50_zsa_stateobj *so = CALLOC_STRUCT(nv50_zsa_stateobj);
354
355 so->pipe = *cso;
356
357 SB_BEGIN_3D(so, DEPTH_WRITE_ENABLE, 1);
358 SB_DATA (so, cso->depth.writemask);
359 SB_BEGIN_3D(so, DEPTH_TEST_ENABLE, 1);
360 if (cso->depth.enabled) {
361 SB_DATA (so, 1);
362 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
363 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
364 } else {
365 SB_DATA (so, 0);
366 }
367
368 SB_BEGIN_3D(so, DEPTH_BOUNDS_EN, 1);
369 if (cso->depth.bounds_test) {
370 SB_DATA (so, 1);
371 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
372 SB_DATA (so, fui(cso->depth.bounds_min));
373 SB_DATA (so, fui(cso->depth.bounds_max));
374 } else {
375 SB_DATA (so, 0);
376 }
377
378 if (cso->stencil[0].enabled) {
379 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
380 SB_DATA (so, 1);
381 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
382 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
383 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
384 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
385 SB_BEGIN_3D(so, STENCIL_FRONT_MASK, 2);
386 SB_DATA (so, cso->stencil[0].writemask);
387 SB_DATA (so, cso->stencil[0].valuemask);
388 } else {
389 SB_BEGIN_3D(so, STENCIL_ENABLE, 1);
390 SB_DATA (so, 0);
391 }
392
393 if (cso->stencil[1].enabled) {
394 assert(cso->stencil[0].enabled);
395 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
396 SB_DATA (so, 1);
397 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
398 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
399 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
400 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
401 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
402 SB_DATA (so, cso->stencil[1].writemask);
403 SB_DATA (so, cso->stencil[1].valuemask);
404 } else {
405 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 1);
406 SB_DATA (so, 0);
407 }
408
409 SB_BEGIN_3D(so, ALPHA_TEST_ENABLE, 1);
410 if (cso->alpha.enabled) {
411 SB_DATA (so, 1);
412 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
413 SB_DATA (so, fui(cso->alpha.ref_value));
414 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
415 } else {
416 SB_DATA (so, 0);
417 }
418
419 assert(so->size <= ARRAY_SIZE(so->state));
420 return (void *)so;
421 }
422
423 static void
424 nv50_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
425 {
426 struct nv50_context *nv50 = nv50_context(pipe);
427
428 nv50->zsa = hwcso;
429 nv50->dirty_3d |= NV50_NEW_3D_ZSA;
430 }
431
432 static void
433 nv50_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
434 {
435 FREE(hwcso);
436 }
437
438 /* ====================== SAMPLERS AND TEXTURES ================================
439 */
440
441 static inline unsigned
442 nv50_tsc_wrap_mode(unsigned wrap)
443 {
444 switch (wrap) {
445 case PIPE_TEX_WRAP_REPEAT:
446 return G80_TSC_WRAP_WRAP;
447 case PIPE_TEX_WRAP_MIRROR_REPEAT:
448 return G80_TSC_WRAP_MIRROR;
449 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
450 return G80_TSC_WRAP_CLAMP_TO_EDGE;
451 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
452 return G80_TSC_WRAP_BORDER;
453 case PIPE_TEX_WRAP_CLAMP:
454 return G80_TSC_WRAP_CLAMP_OGL;
455 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
456 return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_TO_EDGE;
457 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
458 return G80_TSC_WRAP_MIRROR_ONCE_BORDER;
459 case PIPE_TEX_WRAP_MIRROR_CLAMP:
460 return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_OGL;
461 default:
462 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
463 return G80_TSC_WRAP_WRAP;
464 }
465 }
466
467 void *
468 nv50_sampler_state_create(struct pipe_context *pipe,
469 const struct pipe_sampler_state *cso)
470 {
471 struct nv50_tsc_entry *so = MALLOC_STRUCT(nv50_tsc_entry);
472 float f[2];
473
474 so->id = -1;
475
476 so->tsc[0] = (0x00026000 |
477 (nv50_tsc_wrap_mode(cso->wrap_s) << 0) |
478 (nv50_tsc_wrap_mode(cso->wrap_t) << 3) |
479 (nv50_tsc_wrap_mode(cso->wrap_r) << 6));
480
481 switch (cso->mag_img_filter) {
482 case PIPE_TEX_FILTER_LINEAR:
483 so->tsc[1] = G80_TSC_1_MAG_FILTER_LINEAR;
484 break;
485 case PIPE_TEX_FILTER_NEAREST:
486 default:
487 so->tsc[1] = G80_TSC_1_MAG_FILTER_NEAREST;
488 break;
489 }
490
491 switch (cso->min_img_filter) {
492 case PIPE_TEX_FILTER_LINEAR:
493 so->tsc[1] |= G80_TSC_1_MIN_FILTER_LINEAR;
494 break;
495 case PIPE_TEX_FILTER_NEAREST:
496 default:
497 so->tsc[1] |= G80_TSC_1_MIN_FILTER_NEAREST;
498 break;
499 }
500
501 switch (cso->min_mip_filter) {
502 case PIPE_TEX_MIPFILTER_LINEAR:
503 so->tsc[1] |= G80_TSC_1_MIP_FILTER_LINEAR;
504 break;
505 case PIPE_TEX_MIPFILTER_NEAREST:
506 so->tsc[1] |= G80_TSC_1_MIP_FILTER_NEAREST;
507 break;
508 case PIPE_TEX_MIPFILTER_NONE:
509 default:
510 so->tsc[1] |= G80_TSC_1_MIP_FILTER_NONE;
511 break;
512 }
513
514 if (nouveau_screen(pipe->screen)->class_3d >= NVE4_3D_CLASS) {
515 if (cso->seamless_cube_map)
516 so->tsc[1] |= GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING;
517 if (!cso->normalized_coords)
518 so->tsc[1] |= GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS;
519 } else {
520 so->seamless_cube_map = cso->seamless_cube_map;
521 }
522
523 if (cso->max_anisotropy >= 16)
524 so->tsc[0] |= (7 << 20);
525 else
526 if (cso->max_anisotropy >= 12)
527 so->tsc[0] |= (6 << 20);
528 else {
529 so->tsc[0] |= (cso->max_anisotropy >> 1) << 20;
530
531 if (cso->max_anisotropy >= 4)
532 so->tsc[1] |= 6 << G80_TSC_1_TRILIN_OPT__SHIFT;
533 else
534 if (cso->max_anisotropy >= 2)
535 so->tsc[1] |= 4 << G80_TSC_1_TRILIN_OPT__SHIFT;
536 }
537
538 if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
539 /* NOTE: must be deactivated for non-shadow textures */
540 so->tsc[0] |= (1 << 9);
541 so->tsc[0] |= (nvgl_comparison_op(cso->compare_func) & 0x7) << 10;
542 }
543
544 f[0] = CLAMP(cso->lod_bias, -16.0f, 15.0f);
545 so->tsc[1] |= ((int)(f[0] * 256.0f) & 0x1fff) << 12;
546
547 f[0] = CLAMP(cso->min_lod, 0.0f, 15.0f);
548 f[1] = CLAMP(cso->max_lod, 0.0f, 15.0f);
549 so->tsc[2] =
550 (((int)(f[1] * 256.0f) & 0xfff) << 12) | ((int)(f[0] * 256.0f) & 0xfff);
551
552 so->tsc[2] |=
553 util_format_linear_float_to_srgb_8unorm(cso->border_color.f[0]) << 24;
554 so->tsc[3] =
555 util_format_linear_float_to_srgb_8unorm(cso->border_color.f[1]) << 12;
556 so->tsc[3] |=
557 util_format_linear_float_to_srgb_8unorm(cso->border_color.f[2]) << 20;
558
559 so->tsc[4] = fui(cso->border_color.f[0]);
560 so->tsc[5] = fui(cso->border_color.f[1]);
561 so->tsc[6] = fui(cso->border_color.f[2]);
562 so->tsc[7] = fui(cso->border_color.f[3]);
563
564 return (void *)so;
565 }
566
567 static void
568 nv50_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
569 {
570 unsigned s, i;
571
572 for (s = 0; s < 3; ++s) {
573 assert(nv50_context(pipe)->num_samplers[s] <= PIPE_MAX_SAMPLERS);
574 for (i = 0; i < nv50_context(pipe)->num_samplers[s]; ++i)
575 if (nv50_context(pipe)->samplers[s][i] == hwcso)
576 nv50_context(pipe)->samplers[s][i] = NULL;
577 }
578
579 nv50_screen_tsc_free(nv50_context(pipe)->screen, nv50_tsc_entry(hwcso));
580
581 FREE(hwcso);
582 }
583
584 static inline void
585 nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
586 unsigned nr, void **hwcso)
587 {
588 unsigned i;
589
590 assert(nr <= PIPE_MAX_SAMPLERS);
591 for (i = 0; i < nr; ++i) {
592 struct nv50_tsc_entry *old = nv50->samplers[s][i];
593
594 nv50->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
595 if (old)
596 nv50_screen_tsc_unlock(nv50->screen, old);
597 }
598 assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
599 for (; i < nv50->num_samplers[s]; ++i) {
600 if (nv50->samplers[s][i]) {
601 nv50_screen_tsc_unlock(nv50->screen, nv50->samplers[s][i]);
602 nv50->samplers[s][i] = NULL;
603 }
604 }
605
606 nv50->num_samplers[s] = nr;
607
608 nv50->dirty_3d |= NV50_NEW_3D_SAMPLERS;
609 }
610
611 static void
612 nv50_vp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
613 {
614 nv50_stage_sampler_states_bind(nv50_context(pipe), 0, nr, s);
615 }
616
617 static void
618 nv50_fp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
619 {
620 nv50_stage_sampler_states_bind(nv50_context(pipe), 2, nr, s);
621 }
622
623 static void
624 nv50_gp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
625 {
626 nv50_stage_sampler_states_bind(nv50_context(pipe), 1, nr, s);
627 }
628
629 static void
630 nv50_bind_sampler_states(struct pipe_context *pipe,
631 unsigned shader, unsigned start,
632 unsigned num_samplers, void **samplers)
633 {
634 assert(start == 0);
635 switch (shader) {
636 case PIPE_SHADER_VERTEX:
637 nv50_vp_sampler_states_bind(pipe, num_samplers, samplers);
638 break;
639 case PIPE_SHADER_GEOMETRY:
640 nv50_gp_sampler_states_bind(pipe, num_samplers, samplers);
641 break;
642 case PIPE_SHADER_FRAGMENT:
643 nv50_fp_sampler_states_bind(pipe, num_samplers, samplers);
644 break;
645 }
646 }
647
648
649
650 /* NOTE: only called when not referenced anywhere, won't be bound */
651 static void
652 nv50_sampler_view_destroy(struct pipe_context *pipe,
653 struct pipe_sampler_view *view)
654 {
655 pipe_resource_reference(&view->texture, NULL);
656
657 nv50_screen_tic_free(nv50_context(pipe)->screen, nv50_tic_entry(view));
658
659 FREE(nv50_tic_entry(view));
660 }
661
662 static inline void
663 nv50_stage_set_sampler_views(struct nv50_context *nv50, int s,
664 unsigned nr,
665 struct pipe_sampler_view **views)
666 {
667 unsigned i;
668
669 assert(nr <= PIPE_MAX_SAMPLERS);
670 for (i = 0; i < nr; ++i) {
671 struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
672 if (old)
673 nv50_screen_tic_unlock(nv50->screen, old);
674
675 if (views[i] && views[i]->texture) {
676 struct pipe_resource *res = views[i]->texture;
677 if (res->target == PIPE_BUFFER &&
678 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
679 nv50->textures_coherent[s] |= 1 << i;
680 else
681 nv50->textures_coherent[s] &= ~(1 << i);
682 } else {
683 nv50->textures_coherent[s] &= ~(1 << i);
684 }
685
686 pipe_sampler_view_reference(&nv50->textures[s][i], views[i]);
687 }
688
689 assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
690 for (i = nr; i < nv50->num_textures[s]; ++i) {
691 struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
692 if (!old)
693 continue;
694 nv50_screen_tic_unlock(nv50->screen, old);
695
696 pipe_sampler_view_reference(&nv50->textures[s][i], NULL);
697 }
698
699 nv50->num_textures[s] = nr;
700
701 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
702
703 nv50->dirty_3d |= NV50_NEW_3D_TEXTURES;
704 }
705
706 static void
707 nv50_set_sampler_views(struct pipe_context *pipe, unsigned shader,
708 unsigned start, unsigned nr,
709 struct pipe_sampler_view **views)
710 {
711 assert(start == 0);
712 switch (shader) {
713 case PIPE_SHADER_VERTEX:
714 nv50_stage_set_sampler_views(nv50_context(pipe), 0, nr, views);
715 break;
716 case PIPE_SHADER_GEOMETRY:
717 nv50_stage_set_sampler_views(nv50_context(pipe), 1, nr, views);
718 break;
719 case PIPE_SHADER_FRAGMENT:
720 nv50_stage_set_sampler_views(nv50_context(pipe), 2, nr, views);
721 break;
722 default:
723 ;
724 }
725 }
726
727
728
729 /* ============================= SHADERS =======================================
730 */
731
732 static void *
733 nv50_sp_state_create(struct pipe_context *pipe,
734 const struct pipe_shader_state *cso, unsigned type)
735 {
736 struct nv50_program *prog;
737
738 prog = CALLOC_STRUCT(nv50_program);
739 if (!prog)
740 return NULL;
741
742 prog->type = type;
743 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
744
745 if (cso->stream_output.num_outputs)
746 prog->pipe.stream_output = cso->stream_output;
747
748 prog->translated = nv50_program_translate(
749 prog, nv50_context(pipe)->screen->base.device->chipset,
750 &nouveau_context(pipe)->debug);
751
752 return (void *)prog;
753 }
754
755 static void
756 nv50_sp_state_delete(struct pipe_context *pipe, void *hwcso)
757 {
758 struct nv50_program *prog = (struct nv50_program *)hwcso;
759
760 nv50_program_destroy(nv50_context(pipe), prog);
761
762 FREE((void *)prog->pipe.tokens);
763 FREE(prog);
764 }
765
766 static void *
767 nv50_vp_state_create(struct pipe_context *pipe,
768 const struct pipe_shader_state *cso)
769 {
770 return nv50_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
771 }
772
773 static void
774 nv50_vp_state_bind(struct pipe_context *pipe, void *hwcso)
775 {
776 struct nv50_context *nv50 = nv50_context(pipe);
777
778 nv50->vertprog = hwcso;
779 nv50->dirty_3d |= NV50_NEW_3D_VERTPROG;
780 }
781
782 static void *
783 nv50_fp_state_create(struct pipe_context *pipe,
784 const struct pipe_shader_state *cso)
785 {
786 return nv50_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
787 }
788
789 static void
790 nv50_fp_state_bind(struct pipe_context *pipe, void *hwcso)
791 {
792 struct nv50_context *nv50 = nv50_context(pipe);
793
794 nv50->fragprog = hwcso;
795 nv50->dirty_3d |= NV50_NEW_3D_FRAGPROG;
796 }
797
798 static void *
799 nv50_gp_state_create(struct pipe_context *pipe,
800 const struct pipe_shader_state *cso)
801 {
802 return nv50_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
803 }
804
805 static void
806 nv50_gp_state_bind(struct pipe_context *pipe, void *hwcso)
807 {
808 struct nv50_context *nv50 = nv50_context(pipe);
809
810 nv50->gmtyprog = hwcso;
811 nv50->dirty_3d |= NV50_NEW_3D_GMTYPROG;
812 }
813
814 static void *
815 nv50_cp_state_create(struct pipe_context *pipe,
816 const struct pipe_compute_state *cso)
817 {
818 struct nv50_program *prog;
819
820 prog = CALLOC_STRUCT(nv50_program);
821 if (!prog)
822 return NULL;
823 prog->type = PIPE_SHADER_COMPUTE;
824
825 prog->cp.smem_size = cso->req_local_mem;
826 prog->cp.lmem_size = cso->req_private_mem;
827 prog->parm_size = cso->req_input_mem;
828
829 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
830
831 return (void *)prog;
832 }
833
834 static void
835 nv50_cp_state_bind(struct pipe_context *pipe, void *hwcso)
836 {
837 struct nv50_context *nv50 = nv50_context(pipe);
838
839 nv50->compprog = hwcso;
840 nv50->dirty_cp |= NV50_NEW_CP_PROGRAM;
841 }
842
843 static void
844 nv50_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
845 struct pipe_constant_buffer *cb)
846 {
847 struct nv50_context *nv50 = nv50_context(pipe);
848 struct pipe_resource *res = cb ? cb->buffer : NULL;
849 const unsigned s = nv50_context_shader_stage(shader);
850 const unsigned i = index;
851
852 if (shader == PIPE_SHADER_COMPUTE)
853 return;
854
855 assert(i < NV50_MAX_PIPE_CONSTBUFS);
856 if (nv50->constbuf[s][i].user)
857 nv50->constbuf[s][i].u.buf = NULL;
858 else
859 if (nv50->constbuf[s][i].u.buf) {
860 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_CB(s, i));
861 nv04_resource(nv50->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
862 }
863 pipe_resource_reference(&nv50->constbuf[s][i].u.buf, res);
864
865 nv50->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
866 if (nv50->constbuf[s][i].user) {
867 nv50->constbuf[s][i].u.data = cb->user_buffer;
868 nv50->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
869 nv50->constbuf_valid[s] |= 1 << i;
870 nv50->constbuf_coherent[s] &= ~(1 << i);
871 } else
872 if (res) {
873 nv50->constbuf[s][i].offset = cb->buffer_offset;
874 nv50->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
875 nv50->constbuf_valid[s] |= 1 << i;
876 if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
877 nv50->constbuf_coherent[s] |= 1 << i;
878 else
879 nv50->constbuf_coherent[s] &= ~(1 << i);
880 } else {
881 nv50->constbuf_valid[s] &= ~(1 << i);
882 nv50->constbuf_coherent[s] &= ~(1 << i);
883 }
884 nv50->constbuf_dirty[s] |= 1 << i;
885
886 nv50->dirty_3d |= NV50_NEW_3D_CONSTBUF;
887 }
888
889 /* =============================================================================
890 */
891
892 static void
893 nv50_set_blend_color(struct pipe_context *pipe,
894 const struct pipe_blend_color *bcol)
895 {
896 struct nv50_context *nv50 = nv50_context(pipe);
897
898 nv50->blend_colour = *bcol;
899 nv50->dirty_3d |= NV50_NEW_3D_BLEND_COLOUR;
900 }
901
902 static void
903 nv50_set_stencil_ref(struct pipe_context *pipe,
904 const struct pipe_stencil_ref *sr)
905 {
906 struct nv50_context *nv50 = nv50_context(pipe);
907
908 nv50->stencil_ref = *sr;
909 nv50->dirty_3d |= NV50_NEW_3D_STENCIL_REF;
910 }
911
912 static void
913 nv50_set_clip_state(struct pipe_context *pipe,
914 const struct pipe_clip_state *clip)
915 {
916 struct nv50_context *nv50 = nv50_context(pipe);
917
918 memcpy(nv50->clip.ucp, clip->ucp, sizeof(clip->ucp));
919
920 nv50->dirty_3d |= NV50_NEW_3D_CLIP;
921 }
922
923 static void
924 nv50_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
925 {
926 struct nv50_context *nv50 = nv50_context(pipe);
927
928 nv50->sample_mask = sample_mask;
929 nv50->dirty_3d |= NV50_NEW_3D_SAMPLE_MASK;
930 }
931
932 static void
933 nv50_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
934 {
935 struct nv50_context *nv50 = nv50_context(pipe);
936
937 if (nv50->min_samples != min_samples) {
938 nv50->min_samples = min_samples;
939 nv50->dirty_3d |= NV50_NEW_3D_MIN_SAMPLES;
940 }
941 }
942
943 static void
944 nv50_set_framebuffer_state(struct pipe_context *pipe,
945 const struct pipe_framebuffer_state *fb)
946 {
947 struct nv50_context *nv50 = nv50_context(pipe);
948
949 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
950
951 util_copy_framebuffer_state(&nv50->framebuffer, fb);
952
953 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER;
954 }
955
956 static void
957 nv50_set_polygon_stipple(struct pipe_context *pipe,
958 const struct pipe_poly_stipple *stipple)
959 {
960 struct nv50_context *nv50 = nv50_context(pipe);
961
962 nv50->stipple = *stipple;
963 nv50->dirty_3d |= NV50_NEW_3D_STIPPLE;
964 }
965
966 static void
967 nv50_set_scissor_states(struct pipe_context *pipe,
968 unsigned start_slot,
969 unsigned num_scissors,
970 const struct pipe_scissor_state *scissor)
971 {
972 struct nv50_context *nv50 = nv50_context(pipe);
973 int i;
974
975 assert(start_slot + num_scissors <= NV50_MAX_VIEWPORTS);
976 for (i = 0; i < num_scissors; i++) {
977 if (!memcmp(&nv50->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
978 continue;
979 nv50->scissors[start_slot + i] = scissor[i];
980 nv50->scissors_dirty |= 1 << (start_slot + i);
981 nv50->dirty_3d |= NV50_NEW_3D_SCISSOR;
982 }
983 }
984
985 static void
986 nv50_set_viewport_states(struct pipe_context *pipe,
987 unsigned start_slot,
988 unsigned num_viewports,
989 const struct pipe_viewport_state *vpt)
990 {
991 struct nv50_context *nv50 = nv50_context(pipe);
992 int i;
993
994 assert(start_slot + num_viewports <= NV50_MAX_VIEWPORTS);
995 for (i = 0; i < num_viewports; i++) {
996 if (!memcmp(&nv50->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
997 continue;
998 nv50->viewports[start_slot + i] = vpt[i];
999 nv50->viewports_dirty |= 1 << (start_slot + i);
1000 nv50->dirty_3d |= NV50_NEW_3D_VIEWPORT;
1001 }
1002 }
1003
1004 static void
1005 nv50_set_vertex_buffers(struct pipe_context *pipe,
1006 unsigned start_slot, unsigned count,
1007 const struct pipe_vertex_buffer *vb)
1008 {
1009 struct nv50_context *nv50 = nv50_context(pipe);
1010 unsigned i;
1011
1012 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX);
1013 nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
1014
1015 util_set_vertex_buffers_count(nv50->vtxbuf, &nv50->num_vtxbufs, vb,
1016 start_slot, count);
1017
1018 if (!vb) {
1019 nv50->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1020 nv50->vbo_constant &= ~(((1ull << count) - 1) << start_slot);
1021 nv50->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1022 return;
1023 }
1024
1025 for (i = 0; i < count; ++i) {
1026 unsigned dst_index = start_slot + i;
1027
1028 if (!vb[i].buffer && vb[i].user_buffer) {
1029 nv50->vbo_user |= 1 << dst_index;
1030 if (!vb[i].stride)
1031 nv50->vbo_constant |= 1 << dst_index;
1032 else
1033 nv50->vbo_constant &= ~(1 << dst_index);
1034 nv50->vtxbufs_coherent &= ~(1 << dst_index);
1035 } else {
1036 nv50->vbo_user &= ~(1 << dst_index);
1037 nv50->vbo_constant &= ~(1 << dst_index);
1038
1039 if (vb[i].buffer &&
1040 vb[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1041 nv50->vtxbufs_coherent |= (1 << dst_index);
1042 else
1043 nv50->vtxbufs_coherent &= ~(1 << dst_index);
1044 }
1045 }
1046 }
1047
1048 static void
1049 nv50_set_index_buffer(struct pipe_context *pipe,
1050 const struct pipe_index_buffer *ib)
1051 {
1052 struct nv50_context *nv50 = nv50_context(pipe);
1053
1054 if (nv50->idxbuf.buffer)
1055 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_INDEX);
1056
1057 if (ib) {
1058 pipe_resource_reference(&nv50->idxbuf.buffer, ib->buffer);
1059 nv50->idxbuf.index_size = ib->index_size;
1060 if (ib->buffer) {
1061 nv50->idxbuf.offset = ib->offset;
1062 BCTX_REFN(nv50->bufctx_3d, 3D_INDEX, nv04_resource(ib->buffer), RD);
1063 } else {
1064 nv50->idxbuf.user_buffer = ib->user_buffer;
1065 }
1066 } else {
1067 pipe_resource_reference(&nv50->idxbuf.buffer, NULL);
1068 }
1069 }
1070
1071 static void
1072 nv50_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1073 {
1074 struct nv50_context *nv50 = nv50_context(pipe);
1075
1076 nv50->vertex = hwcso;
1077 nv50->dirty_3d |= NV50_NEW_3D_VERTEX;
1078 }
1079
1080 static struct pipe_stream_output_target *
1081 nv50_so_target_create(struct pipe_context *pipe,
1082 struct pipe_resource *res,
1083 unsigned offset, unsigned size)
1084 {
1085 struct nv04_resource *buf = (struct nv04_resource *)res;
1086 struct nv50_so_target *targ = MALLOC_STRUCT(nv50_so_target);
1087 if (!targ)
1088 return NULL;
1089
1090 if (nouveau_context(pipe)->screen->class_3d >= NVA0_3D_CLASS) {
1091 targ->pq = pipe->create_query(pipe,
1092 NVA0_HW_QUERY_STREAM_OUTPUT_BUFFER_OFFSET, 0);
1093 if (!targ->pq) {
1094 FREE(targ);
1095 return NULL;
1096 }
1097 } else {
1098 targ->pq = NULL;
1099 }
1100 targ->clean = true;
1101
1102 targ->pipe.buffer_size = size;
1103 targ->pipe.buffer_offset = offset;
1104 targ->pipe.context = pipe;
1105 targ->pipe.buffer = NULL;
1106 pipe_resource_reference(&targ->pipe.buffer, res);
1107 pipe_reference_init(&targ->pipe.reference, 1);
1108
1109 assert(buf->base.target == PIPE_BUFFER);
1110 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1111
1112 return &targ->pipe;
1113 }
1114
1115 static void
1116 nva0_so_target_save_offset(struct pipe_context *pipe,
1117 struct pipe_stream_output_target *ptarg,
1118 unsigned index, bool serialize)
1119 {
1120 struct nv50_so_target *targ = nv50_so_target(ptarg);
1121
1122 if (serialize) {
1123 struct nouveau_pushbuf *push = nv50_context(pipe)->base.pushbuf;
1124 PUSH_SPACE(push, 2);
1125 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
1126 PUSH_DATA (push, 0);
1127 }
1128
1129 nv50_query(targ->pq)->index = index;
1130 pipe->end_query(pipe, targ->pq);
1131 }
1132
1133 static void
1134 nv50_so_target_destroy(struct pipe_context *pipe,
1135 struct pipe_stream_output_target *ptarg)
1136 {
1137 struct nv50_so_target *targ = nv50_so_target(ptarg);
1138 if (targ->pq)
1139 pipe->destroy_query(pipe, targ->pq);
1140 pipe_resource_reference(&targ->pipe.buffer, NULL);
1141 FREE(targ);
1142 }
1143
1144 static void
1145 nv50_set_stream_output_targets(struct pipe_context *pipe,
1146 unsigned num_targets,
1147 struct pipe_stream_output_target **targets,
1148 const unsigned *offsets)
1149 {
1150 struct nv50_context *nv50 = nv50_context(pipe);
1151 unsigned i;
1152 bool serialize = true;
1153 const bool can_resume = nv50->screen->base.class_3d >= NVA0_3D_CLASS;
1154
1155 assert(num_targets <= 4);
1156
1157 for (i = 0; i < num_targets; ++i) {
1158 const bool changed = nv50->so_target[i] != targets[i];
1159 const bool append = (offsets[i] == (unsigned)-1);
1160 if (!changed && append)
1161 continue;
1162 nv50->so_targets_dirty |= 1 << i;
1163
1164 if (can_resume && changed && nv50->so_target[i]) {
1165 nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1166 serialize = false;
1167 }
1168
1169 if (targets[i] && !append)
1170 nv50_so_target(targets[i])->clean = true;
1171
1172 pipe_so_target_reference(&nv50->so_target[i], targets[i]);
1173 }
1174 for (; i < nv50->num_so_targets; ++i) {
1175 if (can_resume && nv50->so_target[i]) {
1176 nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1177 serialize = false;
1178 }
1179 pipe_so_target_reference(&nv50->so_target[i], NULL);
1180 nv50->so_targets_dirty |= 1 << i;
1181 }
1182 nv50->num_so_targets = num_targets;
1183
1184 if (nv50->so_targets_dirty) {
1185 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_SO);
1186 nv50->dirty_3d |= NV50_NEW_3D_STRMOUT;
1187 }
1188 }
1189
1190 static void
1191 nv50_set_compute_resources(struct pipe_context *pipe,
1192 unsigned start, unsigned nr,
1193 struct pipe_surface **resources)
1194 {
1195 /* TODO: bind surfaces */
1196 }
1197
1198 static inline void
1199 nv50_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1200 {
1201 struct nv04_resource *buf = nv04_resource(res);
1202 if (buf) {
1203 uint64_t limit = (buf->address + buf->base.width0) - 1;
1204 if (limit < (1ULL << 32)) {
1205 *phandle = (uint32_t)buf->address;
1206 } else {
1207 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1208 "resource not contained within 32-bit address space !\n");
1209 *phandle = 0;
1210 }
1211 } else {
1212 *phandle = 0;
1213 }
1214 }
1215
1216 static void
1217 nv50_set_global_bindings(struct pipe_context *pipe,
1218 unsigned start, unsigned nr,
1219 struct pipe_resource **resources,
1220 uint32_t **handles)
1221 {
1222 struct nv50_context *nv50 = nv50_context(pipe);
1223 struct pipe_resource **ptr;
1224 unsigned i;
1225 const unsigned end = start + nr;
1226
1227 if (nv50->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1228 const unsigned old_size = nv50->global_residents.size;
1229 const unsigned req_size = end * sizeof(struct pipe_resource *);
1230 util_dynarray_resize(&nv50->global_residents, req_size);
1231 memset((uint8_t *)nv50->global_residents.data + old_size, 0,
1232 req_size - old_size);
1233 }
1234
1235 if (resources) {
1236 ptr = util_dynarray_element(
1237 &nv50->global_residents, struct pipe_resource *, start);
1238 for (i = 0; i < nr; ++i) {
1239 pipe_resource_reference(&ptr[i], resources[i]);
1240 nv50_set_global_handle(handles[i], resources[i]);
1241 }
1242 } else {
1243 ptr = util_dynarray_element(
1244 &nv50->global_residents, struct pipe_resource *, start);
1245 for (i = 0; i < nr; ++i)
1246 pipe_resource_reference(&ptr[i], NULL);
1247 }
1248
1249 nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_GLOBAL);
1250
1251 nv50->dirty_cp |= NV50_NEW_CP_GLOBALS;
1252 }
1253
1254 void
1255 nv50_init_state_functions(struct nv50_context *nv50)
1256 {
1257 struct pipe_context *pipe = &nv50->base.pipe;
1258
1259 pipe->create_blend_state = nv50_blend_state_create;
1260 pipe->bind_blend_state = nv50_blend_state_bind;
1261 pipe->delete_blend_state = nv50_blend_state_delete;
1262
1263 pipe->create_rasterizer_state = nv50_rasterizer_state_create;
1264 pipe->bind_rasterizer_state = nv50_rasterizer_state_bind;
1265 pipe->delete_rasterizer_state = nv50_rasterizer_state_delete;
1266
1267 pipe->create_depth_stencil_alpha_state = nv50_zsa_state_create;
1268 pipe->bind_depth_stencil_alpha_state = nv50_zsa_state_bind;
1269 pipe->delete_depth_stencil_alpha_state = nv50_zsa_state_delete;
1270
1271 pipe->create_sampler_state = nv50_sampler_state_create;
1272 pipe->delete_sampler_state = nv50_sampler_state_delete;
1273 pipe->bind_sampler_states = nv50_bind_sampler_states;
1274
1275 pipe->create_sampler_view = nv50_create_sampler_view;
1276 pipe->sampler_view_destroy = nv50_sampler_view_destroy;
1277 pipe->set_sampler_views = nv50_set_sampler_views;
1278
1279 pipe->create_vs_state = nv50_vp_state_create;
1280 pipe->create_fs_state = nv50_fp_state_create;
1281 pipe->create_gs_state = nv50_gp_state_create;
1282 pipe->create_compute_state = nv50_cp_state_create;
1283 pipe->bind_vs_state = nv50_vp_state_bind;
1284 pipe->bind_fs_state = nv50_fp_state_bind;
1285 pipe->bind_gs_state = nv50_gp_state_bind;
1286 pipe->bind_compute_state = nv50_cp_state_bind;
1287 pipe->delete_vs_state = nv50_sp_state_delete;
1288 pipe->delete_fs_state = nv50_sp_state_delete;
1289 pipe->delete_gs_state = nv50_sp_state_delete;
1290 pipe->delete_compute_state = nv50_sp_state_delete;
1291
1292 pipe->set_blend_color = nv50_set_blend_color;
1293 pipe->set_stencil_ref = nv50_set_stencil_ref;
1294 pipe->set_clip_state = nv50_set_clip_state;
1295 pipe->set_sample_mask = nv50_set_sample_mask;
1296 pipe->set_min_samples = nv50_set_min_samples;
1297 pipe->set_constant_buffer = nv50_set_constant_buffer;
1298 pipe->set_framebuffer_state = nv50_set_framebuffer_state;
1299 pipe->set_polygon_stipple = nv50_set_polygon_stipple;
1300 pipe->set_scissor_states = nv50_set_scissor_states;
1301 pipe->set_viewport_states = nv50_set_viewport_states;
1302
1303 pipe->create_vertex_elements_state = nv50_vertex_state_create;
1304 pipe->delete_vertex_elements_state = nv50_vertex_state_delete;
1305 pipe->bind_vertex_elements_state = nv50_vertex_state_bind;
1306
1307 pipe->set_vertex_buffers = nv50_set_vertex_buffers;
1308 pipe->set_index_buffer = nv50_set_index_buffer;
1309
1310 pipe->create_stream_output_target = nv50_so_target_create;
1311 pipe->stream_output_target_destroy = nv50_so_target_destroy;
1312 pipe->set_stream_output_targets = nv50_set_stream_output_targets;
1313
1314 pipe->set_global_binding = nv50_set_global_bindings;
1315 pipe->set_compute_resources = nv50_set_compute_resources;
1316
1317 nv50->sample_mask = ~0;
1318 nv50->min_samples = 1;
1319 }