2 #include "util/u_format.h"
4 #include "nv50/nv50_context.h"
7 nv50_fb_set_null_rt(struct nouveau_pushbuf
*push
, unsigned i
)
9 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(i
)), 4);
14 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(i
)), 2);
20 nv50_validate_fb(struct nv50_context
*nv50
)
22 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
23 struct pipe_framebuffer_state
*fb
= &nv50
->framebuffer
;
25 unsigned ms_mode
= NV50_3D_MULTISAMPLE_MODE_MS1
;
26 uint32_t array_size
= 0xffff, array_mode
= 0;
28 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_3D_FB
);
30 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
31 PUSH_DATA (push
, (076543210 << 4) | fb
->nr_cbufs
);
32 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
33 PUSH_DATA (push
, fb
->width
<< 16);
34 PUSH_DATA (push
, fb
->height
<< 16);
36 for (i
= 0; i
< fb
->nr_cbufs
; ++i
) {
37 struct nv50_miptree
*mt
;
38 struct nv50_surface
*sf
;
39 struct nouveau_bo
*bo
;
42 nv50_fb_set_null_rt(push
, i
);
46 mt
= nv50_miptree(fb
->cbufs
[i
]->texture
);
47 sf
= nv50_surface(fb
->cbufs
[i
]);
50 array_size
= MIN2(array_size
, sf
->depth
);
52 array_mode
= NV50_3D_RT_ARRAY_MODE_MODE_3D
; /* 1 << 16 */
54 /* can't mix 3D with ARRAY or have RTs of different depth/array_size */
55 assert(mt
->layout_3d
|| !array_mode
|| array_size
== 1);
57 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(i
)), 5);
58 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
59 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
60 PUSH_DATA (push
, nv50_format_table
[sf
->base
.format
].rt
);
61 if (likely(nouveau_bo_memtype(bo
))) {
62 assert(sf
->base
.texture
->target
!= PIPE_BUFFER
);
64 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
65 PUSH_DATA (push
, mt
->layer_stride
>> 2);
66 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(i
)), 2);
67 PUSH_DATA (push
, sf
->width
);
68 PUSH_DATA (push
, sf
->height
);
69 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
70 PUSH_DATA (push
, array_mode
| array_size
);
71 nv50
->rt_array_mode
= array_mode
| array_size
;
75 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(i
)), 2);
76 PUSH_DATA (push
, NV50_3D_RT_HORIZ_LINEAR
| mt
->level
[0].pitch
);
77 PUSH_DATA (push
, sf
->height
);
78 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
85 ms_mode
= mt
->ms_mode
;
87 if (mt
->base
.status
& NOUVEAU_BUFFER_STATUS_GPU_READING
)
88 nv50
->state
.rt_serialize
= true;
89 mt
->base
.status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
90 mt
->base
.status
&= ~NOUVEAU_BUFFER_STATUS_GPU_READING
;
92 /* only register for writing, otherwise we'd always serialize here */
93 BCTX_REFN(nv50
->bufctx_3d
, 3D_FB
, &mt
->base
, WR
);
97 struct nv50_miptree
*mt
= nv50_miptree(fb
->zsbuf
->texture
);
98 struct nv50_surface
*sf
= nv50_surface(fb
->zsbuf
);
99 int unk
= mt
->base
.base
.target
== PIPE_TEXTURE_3D
|| sf
->depth
== 1;
101 BEGIN_NV04(push
, NV50_3D(ZETA_ADDRESS_HIGH
), 5);
102 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
103 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
104 PUSH_DATA (push
, nv50_format_table
[fb
->zsbuf
->format
].rt
);
105 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
106 PUSH_DATA (push
, mt
->layer_stride
>> 2);
107 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
109 BEGIN_NV04(push
, NV50_3D(ZETA_HORIZ
), 3);
110 PUSH_DATA (push
, sf
->width
);
111 PUSH_DATA (push
, sf
->height
);
112 PUSH_DATA (push
, (unk
<< 16) | sf
->depth
);
114 ms_mode
= mt
->ms_mode
;
116 if (mt
->base
.status
& NOUVEAU_BUFFER_STATUS_GPU_READING
)
117 nv50
->state
.rt_serialize
= true;
118 mt
->base
.status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
119 mt
->base
.status
&= ~NOUVEAU_BUFFER_STATUS_GPU_READING
;
121 BCTX_REFN(nv50
->bufctx_3d
, 3D_FB
, &mt
->base
, WR
);
123 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
127 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
128 PUSH_DATA (push
, ms_mode
);
130 /* Only need to initialize the first viewport, which is used for clears */
131 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
132 PUSH_DATA (push
, fb
->width
<< 16);
133 PUSH_DATA (push
, fb
->height
<< 16);
135 if (nv50
->screen
->tesla
->oclass
>= NVA3_3D_CLASS
) {
136 unsigned ms
= 1 << ms_mode
;
137 BEGIN_NV04(push
, NV50_3D(CB_ADDR
), 1);
138 PUSH_DATA (push
, (NV50_CB_AUX_SAMPLE_OFFSET
<< (8 - 2)) | NV50_CB_AUX
);
139 BEGIN_NI04(push
, NV50_3D(CB_DATA(0)), 2 * ms
);
140 for (i
= 0; i
< ms
; i
++) {
142 nv50
->base
.pipe
.get_sample_position(&nv50
->base
.pipe
, ms
, i
, xy
);
143 PUSH_DATAf(push
, xy
[0]);
144 PUSH_DATAf(push
, xy
[1]);
150 nv50_validate_blend_colour(struct nv50_context
*nv50
)
152 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
154 BEGIN_NV04(push
, NV50_3D(BLEND_COLOR(0)), 4);
155 PUSH_DATAf(push
, nv50
->blend_colour
.color
[0]);
156 PUSH_DATAf(push
, nv50
->blend_colour
.color
[1]);
157 PUSH_DATAf(push
, nv50
->blend_colour
.color
[2]);
158 PUSH_DATAf(push
, nv50
->blend_colour
.color
[3]);
162 nv50_validate_stencil_ref(struct nv50_context
*nv50
)
164 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
166 BEGIN_NV04(push
, NV50_3D(STENCIL_FRONT_FUNC_REF
), 1);
167 PUSH_DATA (push
, nv50
->stencil_ref
.ref_value
[0]);
168 BEGIN_NV04(push
, NV50_3D(STENCIL_BACK_FUNC_REF
), 1);
169 PUSH_DATA (push
, nv50
->stencil_ref
.ref_value
[1]);
173 nv50_validate_stipple(struct nv50_context
*nv50
)
175 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
178 BEGIN_NV04(push
, NV50_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
179 for (i
= 0; i
< 32; ++i
)
180 PUSH_DATA(push
, util_bswap32(nv50
->stipple
.stipple
[i
]));
184 nv50_validate_scissor(struct nv50_context
*nv50
)
186 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
187 #ifdef NV50_SCISSORS_CLIPPING
188 int minx
, maxx
, miny
, maxy
, i
;
190 if (!(nv50
->dirty_3d
&
191 (NV50_NEW_3D_SCISSOR
| NV50_NEW_3D_VIEWPORT
| NV50_NEW_3D_FRAMEBUFFER
)) &&
192 nv50
->state
.scissor
== nv50
->rast
->pipe
.scissor
)
195 if (nv50
->state
.scissor
!= nv50
->rast
->pipe
.scissor
)
196 nv50
->scissors_dirty
= (1 << NV50_MAX_VIEWPORTS
) - 1;
198 nv50
->state
.scissor
= nv50
->rast
->pipe
.scissor
;
200 if ((nv50
->dirty_3d
& NV50_NEW_3D_FRAMEBUFFER
) && !nv50
->state
.scissor
)
201 nv50
->scissors_dirty
= (1 << NV50_MAX_VIEWPORTS
) - 1;
203 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
204 struct pipe_scissor_state
*s
= &nv50
->scissors
[i
];
205 struct pipe_viewport_state
*vp
= &nv50
->viewports
[i
];
207 if (!(nv50
->scissors_dirty
& (1 << i
)) &&
208 !(nv50
->viewports_dirty
& (1 << i
)))
211 if (nv50
->state
.scissor
) {
218 maxx
= nv50
->framebuffer
.width
;
220 maxy
= nv50
->framebuffer
.height
;
223 minx
= MAX2(minx
, (int)(vp
->translate
[0] - fabsf(vp
->scale
[0])));
224 maxx
= MIN2(maxx
, (int)(vp
->translate
[0] + fabsf(vp
->scale
[0])));
225 miny
= MAX2(miny
, (int)(vp
->translate
[1] - fabsf(vp
->scale
[1])));
226 maxy
= MIN2(maxy
, (int)(vp
->translate
[1] + fabsf(vp
->scale
[1])));
228 minx
= MIN2(minx
, 8192);
229 maxx
= MAX2(maxx
, 0);
230 miny
= MIN2(miny
, 8192);
231 maxy
= MAX2(maxy
, 0);
233 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(i
)), 2);
234 PUSH_DATA (push
, (maxx
<< 16) | minx
);
235 PUSH_DATA (push
, (maxy
<< 16) | miny
);
237 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(i
)), 2);
238 PUSH_DATA (push
, (s
->maxx
<< 16) | s
->minx
);
239 PUSH_DATA (push
, (s
->maxy
<< 16) | s
->miny
);
243 nv50
->scissors_dirty
= 0;
247 nv50_validate_viewport(struct nv50_context
*nv50
)
249 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
253 for (i
= 0; i
< NV50_MAX_VIEWPORTS
; i
++) {
254 struct pipe_viewport_state
*vpt
= &nv50
->viewports
[i
];
256 if (!(nv50
->viewports_dirty
& (1 << i
)))
259 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSLATE_X(i
)), 3);
260 PUSH_DATAf(push
, vpt
->translate
[0]);
261 PUSH_DATAf(push
, vpt
->translate
[1]);
262 PUSH_DATAf(push
, vpt
->translate
[2]);
263 BEGIN_NV04(push
, NV50_3D(VIEWPORT_SCALE_X(i
)), 3);
264 PUSH_DATAf(push
, vpt
->scale
[0]);
265 PUSH_DATAf(push
, vpt
->scale
[1]);
266 PUSH_DATAf(push
, vpt
->scale
[2]);
268 zmin
= vpt
->translate
[2] - fabsf(vpt
->scale
[2]);
269 zmax
= vpt
->translate
[2] + fabsf(vpt
->scale
[2]);
271 #ifdef NV50_SCISSORS_CLIPPING
272 BEGIN_NV04(push
, NV50_3D(DEPTH_RANGE_NEAR(i
)), 2);
273 PUSH_DATAf(push
, zmin
);
274 PUSH_DATAf(push
, zmax
);
278 nv50
->viewports_dirty
= 0;
282 nv50_check_program_ucps(struct nv50_context
*nv50
,
283 struct nv50_program
*vp
, uint8_t mask
)
285 const unsigned n
= util_logbase2(mask
) + 1;
287 if (vp
->vp
.clpd_nr
>= n
)
289 nv50_program_destroy(nv50
, vp
);
292 if (likely(vp
== nv50
->vertprog
)) {
293 nv50
->dirty_3d
|= NV50_NEW_3D_VERTPROG
;
294 nv50_vertprog_validate(nv50
);
296 nv50
->dirty_3d
|= NV50_NEW_3D_GMTYPROG
;
297 nv50_gmtyprog_validate(nv50
);
299 nv50_fp_linkage_validate(nv50
);
302 /* alpha test is disabled if there are no color RTs, so make sure we have at
303 * least one if alpha test is enabled. Note that this must run after
304 * nv50_validate_fb, otherwise that will override the RT count setting.
307 nv50_validate_derived_2(struct nv50_context
*nv50
)
309 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
311 if (nv50
->zsa
&& nv50
->zsa
->pipe
.alpha
.enabled
&&
312 nv50
->framebuffer
.nr_cbufs
== 0) {
313 nv50_fb_set_null_rt(push
, 0);
314 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
315 PUSH_DATA (push
, (076543210 << 4) | 1);
320 nv50_validate_derived_3(struct nv50_context
*nv50
)
322 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
323 struct pipe_framebuffer_state
*fb
= &nv50
->framebuffer
;
326 if ((!fb
->nr_cbufs
|| !fb
->cbufs
[0] ||
327 !util_format_is_pure_integer(fb
->cbufs
[0]->format
)) && nv50
->blend
) {
328 if (nv50
->blend
->pipe
.alpha_to_coverage
)
329 ms
|= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE
;
330 if (nv50
->blend
->pipe
.alpha_to_one
)
331 ms
|= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE
;
334 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_CTRL
), 1);
335 PUSH_DATA (push
, ms
);
339 nv50_validate_clip(struct nv50_context
*nv50
)
341 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
342 struct nv50_program
*vp
;
345 if (nv50
->dirty_3d
& NV50_NEW_3D_CLIP
) {
346 BEGIN_NV04(push
, NV50_3D(CB_ADDR
), 1);
347 PUSH_DATA (push
, (NV50_CB_AUX_UCP_OFFSET
<< 8) | NV50_CB_AUX
);
348 BEGIN_NI04(push
, NV50_3D(CB_DATA(0)), PIPE_MAX_CLIP_PLANES
* 4);
349 PUSH_DATAp(push
, &nv50
->clip
.ucp
[0][0], PIPE_MAX_CLIP_PLANES
* 4);
356 clip_enable
= nv50
->rast
->pipe
.clip_plane_enable
;
358 BEGIN_NV04(push
, NV50_3D(CLIP_DISTANCE_ENABLE
), 1);
359 PUSH_DATA (push
, clip_enable
);
362 nv50_check_program_ucps(nv50
, vp
, clip_enable
);
366 nv50_validate_blend(struct nv50_context
*nv50
)
368 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
370 PUSH_SPACE(push
, nv50
->blend
->size
);
371 PUSH_DATAp(push
, nv50
->blend
->state
, nv50
->blend
->size
);
375 nv50_validate_zsa(struct nv50_context
*nv50
)
377 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
379 PUSH_SPACE(push
, nv50
->zsa
->size
);
380 PUSH_DATAp(push
, nv50
->zsa
->state
, nv50
->zsa
->size
);
384 nv50_validate_rasterizer(struct nv50_context
*nv50
)
386 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
388 PUSH_SPACE(push
, nv50
->rast
->size
);
389 PUSH_DATAp(push
, nv50
->rast
->state
, nv50
->rast
->size
);
393 nv50_validate_sample_mask(struct nv50_context
*nv50
)
395 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
399 nv50
->sample_mask
& 0xffff,
400 nv50
->sample_mask
& 0xffff,
401 nv50
->sample_mask
& 0xffff,
402 nv50
->sample_mask
& 0xffff
405 BEGIN_NV04(push
, NV50_3D(MSAA_MASK(0)), 4);
406 PUSH_DATA (push
, mask
[0]);
407 PUSH_DATA (push
, mask
[1]);
408 PUSH_DATA (push
, mask
[2]);
409 PUSH_DATA (push
, mask
[3]);
413 nv50_validate_min_samples(struct nv50_context
*nv50
)
415 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
418 if (nv50
->screen
->tesla
->oclass
< NVA3_3D_CLASS
)
421 samples
= util_next_power_of_two(nv50
->min_samples
);
423 samples
|= NVA3_3D_SAMPLE_SHADING_ENABLE
;
425 BEGIN_NV04(push
, SUBC_3D(NVA3_3D_SAMPLE_SHADING
), 1);
426 PUSH_DATA (push
, samples
);
430 nv50_switch_pipe_context(struct nv50_context
*ctx_to
)
432 struct nv50_context
*ctx_from
= ctx_to
->screen
->cur_ctx
;
435 ctx_to
->state
= ctx_from
->state
;
437 ctx_to
->state
= ctx_to
->screen
->save_state
;
439 ctx_to
->dirty_3d
= ~0;
440 ctx_to
->dirty_cp
= ~0;
441 ctx_to
->viewports_dirty
= ~0;
442 ctx_to
->scissors_dirty
= ~0;
444 ctx_to
->constbuf_dirty
[0] =
445 ctx_to
->constbuf_dirty
[1] =
446 ctx_to
->constbuf_dirty
[2] = (1 << NV50_MAX_PIPE_CONSTBUFS
) - 1;
449 ctx_to
->dirty_3d
&= ~(NV50_NEW_3D_VERTEX
| NV50_NEW_3D_ARRAYS
);
451 if (!ctx_to
->vertprog
)
452 ctx_to
->dirty_3d
&= ~NV50_NEW_3D_VERTPROG
;
453 if (!ctx_to
->fragprog
)
454 ctx_to
->dirty_3d
&= ~NV50_NEW_3D_FRAGPROG
;
457 ctx_to
->dirty_3d
&= ~NV50_NEW_3D_BLEND
;
459 #ifdef NV50_SCISSORS_CLIPPING
460 ctx_to
->dirty_3d
&= ~(NV50_NEW_3D_RASTERIZER
| NV50_NEW_3D_SCISSOR
);
462 ctx_to
->dirty_3d
&= ~NV50_NEW_3D_RASTERIZER
;
465 ctx_to
->dirty_3d
&= ~NV50_NEW_3D_ZSA
;
467 ctx_to
->screen
->cur_ctx
= ctx_to
;
470 static struct nv50_state_validate
471 validate_list_3d
[] = {
472 { nv50_validate_fb
, NV50_NEW_3D_FRAMEBUFFER
},
473 { nv50_validate_blend
, NV50_NEW_3D_BLEND
},
474 { nv50_validate_zsa
, NV50_NEW_3D_ZSA
},
475 { nv50_validate_sample_mask
, NV50_NEW_3D_SAMPLE_MASK
},
476 { nv50_validate_rasterizer
, NV50_NEW_3D_RASTERIZER
},
477 { nv50_validate_blend_colour
, NV50_NEW_3D_BLEND_COLOUR
},
478 { nv50_validate_stencil_ref
, NV50_NEW_3D_STENCIL_REF
},
479 { nv50_validate_stipple
, NV50_NEW_3D_STIPPLE
},
480 #ifdef NV50_SCISSORS_CLIPPING
481 { nv50_validate_scissor
, NV50_NEW_3D_SCISSOR
| NV50_NEW_3D_VIEWPORT
|
482 NV50_NEW_3D_RASTERIZER
|
483 NV50_NEW_3D_FRAMEBUFFER
},
485 { nv50_validate_scissor
, NV50_NEW_3D_SCISSOR
},
487 { nv50_validate_viewport
, NV50_NEW_3D_VIEWPORT
},
488 { nv50_vertprog_validate
, NV50_NEW_3D_VERTPROG
},
489 { nv50_gmtyprog_validate
, NV50_NEW_3D_GMTYPROG
},
490 { nv50_fragprog_validate
, NV50_NEW_3D_FRAGPROG
| NV50_NEW_3D_RASTERIZER
|
491 NV50_NEW_3D_MIN_SAMPLES
},
492 { nv50_fp_linkage_validate
, NV50_NEW_3D_FRAGPROG
| NV50_NEW_3D_VERTPROG
|
493 NV50_NEW_3D_GMTYPROG
| NV50_NEW_3D_RASTERIZER
},
494 { nv50_gp_linkage_validate
, NV50_NEW_3D_GMTYPROG
| NV50_NEW_3D_VERTPROG
},
495 { nv50_validate_derived_rs
, NV50_NEW_3D_FRAGPROG
| NV50_NEW_3D_RASTERIZER
|
496 NV50_NEW_3D_VERTPROG
| NV50_NEW_3D_GMTYPROG
},
497 { nv50_validate_derived_2
, NV50_NEW_3D_ZSA
| NV50_NEW_3D_FRAMEBUFFER
},
498 { nv50_validate_derived_3
, NV50_NEW_3D_BLEND
| NV50_NEW_3D_FRAMEBUFFER
},
499 { nv50_validate_clip
, NV50_NEW_3D_CLIP
| NV50_NEW_3D_RASTERIZER
|
500 NV50_NEW_3D_VERTPROG
| NV50_NEW_3D_GMTYPROG
},
501 { nv50_constbufs_validate
, NV50_NEW_3D_CONSTBUF
},
502 { nv50_validate_textures
, NV50_NEW_3D_TEXTURES
},
503 { nv50_validate_samplers
, NV50_NEW_3D_SAMPLERS
},
504 { nv50_stream_output_validate
, NV50_NEW_3D_STRMOUT
|
505 NV50_NEW_3D_VERTPROG
| NV50_NEW_3D_GMTYPROG
},
506 { nv50_vertex_arrays_validate
, NV50_NEW_3D_VERTEX
| NV50_NEW_3D_ARRAYS
},
507 { nv50_validate_min_samples
, NV50_NEW_3D_MIN_SAMPLES
},
511 nv50_state_validate(struct nv50_context
*nv50
, uint32_t mask
,
512 struct nv50_state_validate
*validate_list
, int size
,
513 uint32_t *dirty
, struct nouveau_bufctx
*bufctx
)
519 if (nv50
->screen
->cur_ctx
!= nv50
)
520 nv50_switch_pipe_context(nv50
);
522 state_mask
= *dirty
& mask
;
525 for (i
= 0; i
< size
; i
++) {
526 struct nv50_state_validate
*validate
= &validate_list
[i
];
528 if (state_mask
& validate
->states
)
529 validate
->func(nv50
);
531 *dirty
&= ~state_mask
;
533 if (nv50
->state
.rt_serialize
) {
534 nv50
->state
.rt_serialize
= false;
535 BEGIN_NV04(nv50
->base
.pushbuf
, SUBC_3D(NV50_GRAPH_SERIALIZE
), 1);
536 PUSH_DATA (nv50
->base
.pushbuf
, 0);
539 nv50_bufctx_fence(bufctx
, false);
541 nouveau_pushbuf_bufctx(nv50
->base
.pushbuf
, bufctx
);
542 ret
= nouveau_pushbuf_validate(nv50
->base
.pushbuf
);
548 nv50_state_validate_3d(struct nv50_context
*nv50
, uint32_t mask
)
552 ret
= nv50_state_validate(nv50
, mask
, validate_list_3d
,
553 ARRAY_SIZE(validate_list_3d
), &nv50
->dirty_3d
,
556 if (unlikely(nv50
->state
.flushed
)) {
557 nv50
->state
.flushed
= false;
558 nv50_bufctx_fence(nv50
->bufctx_3d
, true);