2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/format/u_format.h"
30 #include "util/u_math.h"
31 #include "util/u_surface.h"
33 #include "tgsi/tgsi_ureg.h"
35 #include "os/os_thread.h"
37 #include "nv50/nv50_context.h"
38 #include "nv50/nv50_resource.h"
40 #include "nv50/g80_defs.xml.h"
41 #include "nv50/g80_texture.xml.h"
43 /* these are used in nv50_blit.h */
44 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
45 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
47 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
48 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
50 #define NOUVEAU_DRIVER 0x50
51 #include "nv50/nv50_blit.h"
54 nv50_2d_format(enum pipe_format format
, bool dst
, bool dst_src_equal
)
56 uint8_t id
= nv50_format_table
[format
].rt
;
58 /* Hardware values for color formats range from 0xc0 to 0xff,
59 * but the 2D engine doesn't support all of them.
61 if ((id
>= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS
& (1ULL << (id
- 0xc0))))
63 assert(dst_src_equal
);
65 switch (util_format_get_blocksize(format
)) {
67 return G80_SURFACE_FORMAT_R8_UNORM
;
69 return G80_SURFACE_FORMAT_R16_UNORM
;
71 return G80_SURFACE_FORMAT_BGRA8_UNORM
;
73 return G80_SURFACE_FORMAT_RGBA16_FLOAT
;
75 return G80_SURFACE_FORMAT_RGBA32_FLOAT
;
82 nv50_2d_texture_set(struct nouveau_pushbuf
*push
, int dst
,
83 struct nv50_miptree
*mt
, unsigned level
, unsigned layer
,
84 enum pipe_format pformat
, bool dst_src_pformat_equal
)
86 struct nouveau_bo
*bo
= mt
->base
.bo
;
87 uint32_t width
, height
, depth
;
89 uint32_t mthd
= dst
? NV50_2D_DST_FORMAT
: NV50_2D_SRC_FORMAT
;
90 uint32_t offset
= mt
->level
[level
].offset
;
92 format
= nv50_2d_format(pformat
, dst
, dst_src_pformat_equal
);
94 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
95 util_format_name(pformat
));
99 width
= u_minify(mt
->base
.base
.width0
, level
) << mt
->ms_x
;
100 height
= u_minify(mt
->base
.base
.height0
, level
) << mt
->ms_y
;
101 depth
= u_minify(mt
->base
.base
.depth0
, level
);
103 offset
= mt
->level
[level
].offset
;
104 if (!mt
->layout_3d
) {
105 offset
+= mt
->layer_stride
* layer
;
110 offset
+= nv50_mt_zslice_offset(mt
, level
, layer
);
114 if (!nouveau_bo_memtype(bo
)) {
115 BEGIN_NV04(push
, SUBC_2D(mthd
), 2);
116 PUSH_DATA (push
, format
);
118 BEGIN_NV04(push
, SUBC_2D(mthd
+ 0x14), 5);
119 PUSH_DATA (push
, mt
->level
[level
].pitch
);
120 PUSH_DATA (push
, width
);
121 PUSH_DATA (push
, height
);
122 PUSH_DATAh(push
, mt
->base
.address
+ offset
);
123 PUSH_DATA (push
, mt
->base
.address
+ offset
);
125 BEGIN_NV04(push
, SUBC_2D(mthd
), 5);
126 PUSH_DATA (push
, format
);
128 PUSH_DATA (push
, mt
->level
[level
].tile_mode
);
129 PUSH_DATA (push
, depth
);
130 PUSH_DATA (push
, layer
);
131 BEGIN_NV04(push
, SUBC_2D(mthd
+ 0x18), 4);
132 PUSH_DATA (push
, width
);
133 PUSH_DATA (push
, height
);
134 PUSH_DATAh(push
, mt
->base
.address
+ offset
);
135 PUSH_DATA (push
, mt
->base
.address
+ offset
);
140 BEGIN_NV04(push
, SUBC_2D(NV50_2D_CLIP_X
), 4);
143 PUSH_DATA (push
, width
);
144 PUSH_DATA (push
, height
);
151 nv50_2d_texture_do_copy(struct nouveau_pushbuf
*push
,
152 struct nv50_miptree
*dst
, unsigned dst_level
,
153 unsigned dx
, unsigned dy
, unsigned dz
,
154 struct nv50_miptree
*src
, unsigned src_level
,
155 unsigned sx
, unsigned sy
, unsigned sz
,
156 unsigned w
, unsigned h
)
158 const enum pipe_format dfmt
= dst
->base
.base
.format
;
159 const enum pipe_format sfmt
= src
->base
.base
.format
;
161 bool eqfmt
= dfmt
== sfmt
;
163 if (!PUSH_SPACE(push
, 2 * 16 + 32))
166 ret
= nv50_2d_texture_set(push
, 1, dst
, dst_level
, dz
, dfmt
, eqfmt
);
170 ret
= nv50_2d_texture_set(push
, 0, src
, src_level
, sz
, sfmt
, eqfmt
);
174 BEGIN_NV04(push
, NV50_2D(BLIT_CONTROL
), 1);
175 PUSH_DATA (push
, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE
);
176 BEGIN_NV04(push
, NV50_2D(BLIT_DST_X
), 4);
177 PUSH_DATA (push
, dx
<< dst
->ms_x
);
178 PUSH_DATA (push
, dy
<< dst
->ms_y
);
179 PUSH_DATA (push
, w
<< dst
->ms_x
);
180 PUSH_DATA (push
, h
<< dst
->ms_y
);
181 BEGIN_NV04(push
, NV50_2D(BLIT_DU_DX_FRACT
), 4);
186 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_X_FRACT
), 4);
188 PUSH_DATA (push
, sx
<< src
->ms_x
);
190 PUSH_DATA (push
, sy
<< src
->ms_y
);
196 nv50_resource_copy_region(struct pipe_context
*pipe
,
197 struct pipe_resource
*dst
, unsigned dst_level
,
198 unsigned dstx
, unsigned dsty
, unsigned dstz
,
199 struct pipe_resource
*src
, unsigned src_level
,
200 const struct pipe_box
*src_box
)
202 struct nv50_context
*nv50
= nv50_context(pipe
);
205 unsigned dst_layer
= dstz
, src_layer
= src_box
->z
;
207 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
208 nouveau_copy_buffer(&nv50
->base
,
209 nv04_resource(dst
), dstx
,
210 nv04_resource(src
), src_box
->x
, src_box
->width
);
214 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
215 assert((src
->nr_samples
| 1) == (dst
->nr_samples
| 1));
217 m2mf
= (src
->format
== dst
->format
) ||
218 (util_format_get_blocksizebits(src
->format
) ==
219 util_format_get_blocksizebits(dst
->format
));
221 nv04_resource(dst
)->status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
224 struct nv50_miptree
*src_mt
= nv50_miptree(src
);
225 struct nv50_miptree
*dst_mt
= nv50_miptree(dst
);
226 struct nv50_m2mf_rect drect
, srect
;
228 unsigned nx
= util_format_get_nblocksx(src
->format
, src_box
->width
)
230 unsigned ny
= util_format_get_nblocksy(src
->format
, src_box
->height
)
233 nv50_m2mf_rect_setup(&drect
, dst
, dst_level
, dstx
, dsty
, dstz
);
234 nv50_m2mf_rect_setup(&srect
, src
, src_level
,
235 src_box
->x
, src_box
->y
, src_box
->z
);
237 for (i
= 0; i
< src_box
->depth
; ++i
) {
238 nv50_m2mf_transfer_rect(nv50
, &drect
, &srect
, nx
, ny
);
240 if (dst_mt
->layout_3d
)
243 drect
.base
+= dst_mt
->layer_stride
;
245 if (src_mt
->layout_3d
)
248 srect
.base
+= src_mt
->layer_stride
;
253 assert((src
->format
== dst
->format
) ||
254 (nv50_2d_src_format_faithful(src
->format
) &&
255 nv50_2d_dst_format_faithful(dst
->format
)));
257 BCTX_REFN(nv50
->bufctx
, 2D
, nv04_resource(src
), RD
);
258 BCTX_REFN(nv50
->bufctx
, 2D
, nv04_resource(dst
), WR
);
259 nouveau_pushbuf_bufctx(nv50
->base
.pushbuf
, nv50
->bufctx
);
260 nouveau_pushbuf_validate(nv50
->base
.pushbuf
);
262 for (; dst_layer
< dstz
+ src_box
->depth
; ++dst_layer
, ++src_layer
) {
263 ret
= nv50_2d_texture_do_copy(nv50
->base
.pushbuf
,
264 nv50_miptree(dst
), dst_level
,
265 dstx
, dsty
, dst_layer
,
266 nv50_miptree(src
), src_level
,
267 src_box
->x
, src_box
->y
, src_layer
,
268 src_box
->width
, src_box
->height
);
272 nouveau_bufctx_reset(nv50
->bufctx
, NV50_BIND_2D
);
276 nv50_clear_render_target(struct pipe_context
*pipe
,
277 struct pipe_surface
*dst
,
278 const union pipe_color_union
*color
,
279 unsigned dstx
, unsigned dsty
,
280 unsigned width
, unsigned height
,
281 bool render_condition_enabled
)
283 struct nv50_context
*nv50
= nv50_context(pipe
);
284 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
285 struct nv50_miptree
*mt
= nv50_miptree(dst
->texture
);
286 struct nv50_surface
*sf
= nv50_surface(dst
);
287 struct nouveau_bo
*bo
= mt
->base
.bo
;
290 assert(dst
->texture
->target
!= PIPE_BUFFER
);
292 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
293 PUSH_DATAf(push
, color
->f
[0]);
294 PUSH_DATAf(push
, color
->f
[1]);
295 PUSH_DATAf(push
, color
->f
[2]);
296 PUSH_DATAf(push
, color
->f
[3]);
298 if (nouveau_pushbuf_space(push
, 64 + sf
->depth
, 1, 0))
301 PUSH_REFN(push
, bo
, mt
->base
.domain
| NOUVEAU_BO_WR
);
303 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
304 PUSH_DATA (push
, ( width
<< 16) | dstx
);
305 PUSH_DATA (push
, (height
<< 16) | dsty
);
306 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
307 PUSH_DATA (push
, 8192 << 16);
308 PUSH_DATA (push
, 8192 << 16);
309 nv50
->scissors_dirty
|= 1;
311 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
313 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
314 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
315 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
316 PUSH_DATA (push
, nv50_format_table
[dst
->format
].rt
);
317 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
318 PUSH_DATA (push
, mt
->layer_stride
>> 2);
319 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(0)), 2);
320 if (nouveau_bo_memtype(bo
))
321 PUSH_DATA(push
, sf
->width
);
323 PUSH_DATA(push
, NV50_3D_RT_HORIZ_LINEAR
| mt
->level
[0].pitch
);
324 PUSH_DATA (push
, sf
->height
);
325 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
327 PUSH_DATA(push
, NV50_3D_RT_ARRAY_MODE_MODE_3D
| 512);
329 PUSH_DATA(push
, 512);
331 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
332 PUSH_DATA (push
, mt
->ms_mode
);
334 if (!nouveau_bo_memtype(bo
)) {
335 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
339 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
341 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
342 PUSH_DATA (push
, (width
<< 16) | dstx
);
343 PUSH_DATA (push
, (height
<< 16) | dsty
);
345 if (!render_condition_enabled
) {
346 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
347 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
350 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), sf
->depth
);
351 for (z
= 0; z
< sf
->depth
; ++z
) {
352 PUSH_DATA (push
, 0x3c |
353 (z
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
356 if (!render_condition_enabled
) {
357 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
358 PUSH_DATA (push
, nv50
->cond_condmode
);
361 nv50
->dirty_3d
|= NV50_NEW_3D_FRAMEBUFFER
| NV50_NEW_3D_SCISSOR
;
365 nv50_clear_depth_stencil(struct pipe_context
*pipe
,
366 struct pipe_surface
*dst
,
367 unsigned clear_flags
,
370 unsigned dstx
, unsigned dsty
,
371 unsigned width
, unsigned height
,
372 bool render_condition_enabled
)
374 struct nv50_context
*nv50
= nv50_context(pipe
);
375 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
376 struct nv50_miptree
*mt
= nv50_miptree(dst
->texture
);
377 struct nv50_surface
*sf
= nv50_surface(dst
);
378 struct nouveau_bo
*bo
= mt
->base
.bo
;
382 assert(dst
->texture
->target
!= PIPE_BUFFER
);
383 assert(nouveau_bo_memtype(bo
)); /* ZETA cannot be linear */
385 if (clear_flags
& PIPE_CLEAR_DEPTH
) {
386 BEGIN_NV04(push
, NV50_3D(CLEAR_DEPTH
), 1);
387 PUSH_DATAf(push
, depth
);
388 mode
|= NV50_3D_CLEAR_BUFFERS_Z
;
391 if (clear_flags
& PIPE_CLEAR_STENCIL
) {
392 BEGIN_NV04(push
, NV50_3D(CLEAR_STENCIL
), 1);
393 PUSH_DATA (push
, stencil
& 0xff);
394 mode
|= NV50_3D_CLEAR_BUFFERS_S
;
397 if (nouveau_pushbuf_space(push
, 64 + sf
->depth
, 1, 0))
400 PUSH_REFN(push
, bo
, mt
->base
.domain
| NOUVEAU_BO_WR
);
402 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
403 PUSH_DATA (push
, ( width
<< 16) | dstx
);
404 PUSH_DATA (push
, (height
<< 16) | dsty
);
405 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
406 PUSH_DATA (push
, 8192 << 16);
407 PUSH_DATA (push
, 8192 << 16);
408 nv50
->scissors_dirty
|= 1;
410 BEGIN_NV04(push
, NV50_3D(ZETA_ADDRESS_HIGH
), 5);
411 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
412 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
413 PUSH_DATA (push
, nv50_format_table
[dst
->format
].rt
);
414 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
415 PUSH_DATA (push
, mt
->layer_stride
>> 2);
416 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
418 BEGIN_NV04(push
, NV50_3D(ZETA_HORIZ
), 3);
419 PUSH_DATA (push
, sf
->width
);
420 PUSH_DATA (push
, sf
->height
);
421 PUSH_DATA (push
, (1 << 16) | 1);
423 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
424 PUSH_DATA (push
, 512);
426 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
427 PUSH_DATA (push
, mt
->ms_mode
);
429 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
430 PUSH_DATA (push
, (width
<< 16) | dstx
);
431 PUSH_DATA (push
, (height
<< 16) | dsty
);
433 if (!render_condition_enabled
) {
434 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
435 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
438 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), sf
->depth
);
439 for (z
= 0; z
< sf
->depth
; ++z
) {
440 PUSH_DATA (push
, mode
|
441 (z
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
444 if (!render_condition_enabled
) {
445 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
446 PUSH_DATA (push
, nv50
->cond_condmode
);
449 nv50
->dirty_3d
|= NV50_NEW_3D_FRAMEBUFFER
| NV50_NEW_3D_SCISSOR
;
453 nv50_clear_texture(struct pipe_context
*pipe
,
454 struct pipe_resource
*res
,
456 const struct pipe_box
*box
,
459 struct pipe_surface tmpl
= {{0}}, *sf
;
461 tmpl
.format
= res
->format
;
462 tmpl
.u
.tex
.first_layer
= box
->z
;
463 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
464 tmpl
.u
.tex
.level
= level
;
465 sf
= pipe
->create_surface(pipe
, res
, &tmpl
);
469 if (util_format_is_depth_or_stencil(res
->format
)) {
473 const struct util_format_description
*desc
=
474 util_format_description(res
->format
);
476 if (util_format_has_depth(desc
)) {
477 clear
|= PIPE_CLEAR_DEPTH
;
478 util_format_unpack_z_float(res
->format
, &depth
, data
, 1);
480 if (util_format_has_stencil(desc
)) {
481 clear
|= PIPE_CLEAR_STENCIL
;
482 util_format_unpack_s_8uint(res
->format
, &stencil
, data
, 1);
484 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
485 box
->x
, box
->y
, box
->width
, box
->height
, false);
487 union pipe_color_union color
;
489 switch (util_format_get_blocksizebits(res
->format
)) {
491 sf
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
492 memcpy(&color
.ui
, data
, 128 / 8);
495 sf
->format
= PIPE_FORMAT_R32G32_UINT
;
496 memcpy(&color
.ui
, data
, 64 / 8);
497 memset(&color
.ui
[2], 0, 64 / 8);
500 sf
->format
= PIPE_FORMAT_R32_UINT
;
501 memcpy(&color
.ui
, data
, 32 / 8);
502 memset(&color
.ui
[1], 0, 96 / 8);
505 sf
->format
= PIPE_FORMAT_R16_UINT
;
506 color
.ui
[0] = util_cpu_to_le32(
507 util_le16_to_cpu(*(unsigned short *)data
));
508 memset(&color
.ui
[1], 0, 96 / 8);
511 sf
->format
= PIPE_FORMAT_R8_UINT
;
512 color
.ui
[0] = util_cpu_to_le32(*(unsigned char *)data
);
513 memset(&color
.ui
[1], 0, 96 / 8);
516 assert(!"Unknown texel element size");
520 pipe
->clear_render_target(pipe
, sf
, &color
,
521 box
->x
, box
->y
, box
->width
, box
->height
, false);
523 pipe
->surface_destroy(pipe
, sf
);
527 nv50_clear(struct pipe_context
*pipe
, unsigned buffers
, const struct pipe_scissor_state
*scissor_state
,
528 const union pipe_color_union
*color
,
529 double depth
, unsigned stencil
)
531 struct nv50_context
*nv50
= nv50_context(pipe
);
532 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
533 struct pipe_framebuffer_state
*fb
= &nv50
->framebuffer
;
537 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
538 if (!nv50_state_validate_3d(nv50
, NV50_NEW_3D_FRAMEBUFFER
))
541 /* We have to clear ALL of the layers, not up to the min number of layers
542 * of any attachment. */
543 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
544 PUSH_DATA (push
, (nv50
->rt_array_mode
& NV50_3D_RT_ARRAY_MODE_MODE_3D
) | 512);
546 if (buffers
& PIPE_CLEAR_COLOR
&& fb
->nr_cbufs
) {
547 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
548 PUSH_DATAf(push
, color
->f
[0]);
549 PUSH_DATAf(push
, color
->f
[1]);
550 PUSH_DATAf(push
, color
->f
[2]);
551 PUSH_DATAf(push
, color
->f
[3]);
552 if (buffers
& PIPE_CLEAR_COLOR0
)
554 NV50_3D_CLEAR_BUFFERS_R
| NV50_3D_CLEAR_BUFFERS_G
|
555 NV50_3D_CLEAR_BUFFERS_B
| NV50_3D_CLEAR_BUFFERS_A
;
558 if (buffers
& PIPE_CLEAR_DEPTH
) {
559 BEGIN_NV04(push
, NV50_3D(CLEAR_DEPTH
), 1);
560 PUSH_DATA (push
, fui(depth
));
561 mode
|= NV50_3D_CLEAR_BUFFERS_Z
;
564 if (buffers
& PIPE_CLEAR_STENCIL
) {
565 BEGIN_NV04(push
, NV50_3D(CLEAR_STENCIL
), 1);
566 PUSH_DATA (push
, stencil
& 0xff);
567 mode
|= NV50_3D_CLEAR_BUFFERS_S
;
571 int zs_layers
= 0, color0_layers
= 0;
572 if (fb
->cbufs
[0] && (mode
& 0x3c))
573 color0_layers
= nv50_surface(fb
->cbufs
[0])->depth
;
574 if (fb
->zsbuf
&& (mode
& ~0x3c))
575 zs_layers
= nv50_surface(fb
->zsbuf
)->depth
;
577 for (j
= 0; j
< MIN2(zs_layers
, color0_layers
); j
++) {
578 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
579 PUSH_DATA(push
, mode
| (j
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
581 for (k
= j
; k
< zs_layers
; k
++) {
582 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
583 PUSH_DATA(push
, (mode
& ~0x3c) | (k
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
585 for (k
= j
; k
< color0_layers
; k
++) {
586 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
587 PUSH_DATA(push
, (mode
& 0x3c) | (k
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
591 for (i
= 1; i
< fb
->nr_cbufs
; i
++) {
592 struct pipe_surface
*sf
= fb
->cbufs
[i
];
593 if (!sf
|| !(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
595 for (j
= 0; j
< nv50_surface(sf
)->depth
; j
++) {
596 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
597 PUSH_DATA (push
, (i
<< 6) | 0x3c |
598 (j
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
602 /* restore the array mode */
603 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
604 PUSH_DATA (push
, nv50
->rt_array_mode
);
608 nv50_clear_buffer_push(struct pipe_context
*pipe
,
609 struct pipe_resource
*res
,
610 unsigned offset
, unsigned size
,
611 const void *data
, int data_size
)
613 struct nv50_context
*nv50
= nv50_context(pipe
);
614 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
615 struct nv04_resource
*buf
= nv04_resource(res
);
616 unsigned count
= (size
+ 3) / 4;
617 unsigned xcoord
= offset
& 0xff;
620 if (data_size
== 1) {
621 tmp
= *(unsigned char *)data
;
622 tmp
= (tmp
<< 24) | (tmp
<< 16) | (tmp
<< 8) | tmp
;
625 } else if (data_size
== 2) {
626 tmp
= *(unsigned short *)data
;
627 tmp
= (tmp
<< 16) | tmp
;
632 unsigned data_words
= data_size
/ 4;
634 nouveau_bufctx_refn(nv50
->bufctx
, 0, buf
->bo
, buf
->domain
| NOUVEAU_BO_WR
);
635 nouveau_pushbuf_bufctx(push
, nv50
->bufctx
);
636 nouveau_pushbuf_validate(push
);
640 BEGIN_NV04(push
, NV50_2D(DST_FORMAT
), 2);
641 PUSH_DATA (push
, G80_SURFACE_FORMAT_R8_UNORM
);
643 BEGIN_NV04(push
, NV50_2D(DST_PITCH
), 5);
644 PUSH_DATA (push
, 262144);
645 PUSH_DATA (push
, 65536);
647 PUSH_DATAh(push
, buf
->address
+ offset
);
648 PUSH_DATA (push
, buf
->address
+ offset
);
649 BEGIN_NV04(push
, NV50_2D(SIFC_BITMAP_ENABLE
), 2);
651 PUSH_DATA (push
, G80_SURFACE_FORMAT_R8_UNORM
);
652 BEGIN_NV04(push
, NV50_2D(SIFC_WIDTH
), 10);
653 PUSH_DATA (push
, size
);
660 PUSH_DATA (push
, xcoord
);
665 unsigned nr_data
= MIN2(count
, NV04_PFIFO_MAX_PACKET_LEN
) / data_words
;
666 unsigned nr
= nr_data
* data_words
;
668 BEGIN_NI04(push
, NV50_2D(SIFC_DATA
), nr
);
669 for (i
= 0; i
< nr_data
; i
++)
670 PUSH_DATAp(push
, data
, data_words
);
675 nv50_resource_validate(buf
, NOUVEAU_BO_WR
);
677 nouveau_bufctx_reset(nv50
->bufctx
, 0);
681 nv50_clear_buffer(struct pipe_context
*pipe
,
682 struct pipe_resource
*res
,
683 unsigned offset
, unsigned size
,
684 const void *data
, int data_size
)
686 struct nv50_context
*nv50
= nv50_context(pipe
);
687 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
688 struct nv04_resource
*buf
= (struct nv04_resource
*)res
;
689 union pipe_color_union color
;
690 enum pipe_format dst_fmt
;
691 unsigned width
, height
, elements
;
693 assert(res
->target
== PIPE_BUFFER
);
694 assert(nouveau_bo_memtype(buf
->bo
) == 0);
698 dst_fmt
= PIPE_FORMAT_R32G32B32A32_UINT
;
699 memcpy(&color
.ui
, data
, 16);
702 dst_fmt
= PIPE_FORMAT_R32G32_UINT
;
703 memcpy(&color
.ui
, data
, 8);
704 memset(&color
.ui
[2], 0, 8);
707 dst_fmt
= PIPE_FORMAT_R32_UINT
;
708 memcpy(&color
.ui
, data
, 4);
709 memset(&color
.ui
[1], 0, 12);
712 dst_fmt
= PIPE_FORMAT_R16_UINT
;
713 color
.ui
[0] = util_cpu_to_le32(
714 util_le16_to_cpu(*(unsigned short *)data
));
715 memset(&color
.ui
[1], 0, 12);
718 dst_fmt
= PIPE_FORMAT_R8_UINT
;
719 color
.ui
[0] = util_cpu_to_le32(*(unsigned char *)data
);
720 memset(&color
.ui
[1], 0, 12);
723 assert(!"Unsupported element size");
727 util_range_add(&buf
->base
, &buf
->valid_buffer_range
, offset
, offset
+ size
);
729 assert(size
% data_size
== 0);
732 unsigned fixup_size
= MIN2(size
, align(offset
, 0x100) - offset
);
733 assert(fixup_size
% data_size
== 0);
734 nv50_clear_buffer_push(pipe
, res
, offset
, fixup_size
, data
, data_size
);
735 offset
+= fixup_size
;
741 elements
= size
/ data_size
;
742 height
= (elements
+ 8191) / 8192;
743 width
= elements
/ height
;
748 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
749 PUSH_DATA (push
, color
.ui
[0]);
750 PUSH_DATA (push
, color
.ui
[1]);
751 PUSH_DATA (push
, color
.ui
[2]);
752 PUSH_DATA (push
, color
.ui
[3]);
754 if (nouveau_pushbuf_space(push
, 64, 1, 0))
757 PUSH_REFN(push
, buf
->bo
, buf
->domain
| NOUVEAU_BO_WR
);
759 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
760 PUSH_DATA (push
, width
<< 16);
761 PUSH_DATA (push
, height
<< 16);
762 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
763 PUSH_DATA (push
, 8192 << 16);
764 PUSH_DATA (push
, 8192 << 16);
765 nv50
->scissors_dirty
|= 1;
767 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
769 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
770 PUSH_DATAh(push
, buf
->address
+ offset
);
771 PUSH_DATA (push
, buf
->address
+ offset
);
772 PUSH_DATA (push
, nv50_format_table
[dst_fmt
].rt
);
775 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(0)), 2);
776 PUSH_DATA (push
, NV50_3D_RT_HORIZ_LINEAR
| align(width
* data_size
, 0x100));
777 PUSH_DATA (push
, height
);
778 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
780 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
783 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
785 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
786 PUSH_DATA (push
, (width
<< 16));
787 PUSH_DATA (push
, (height
<< 16));
789 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
790 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
792 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
793 PUSH_DATA (push
, 0x3c);
795 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
796 PUSH_DATA (push
, nv50
->cond_condmode
);
798 nv50_resource_validate(buf
, NOUVEAU_BO_WR
);
800 if (width
* height
!= elements
) {
801 offset
+= width
* height
* data_size
;
802 width
= elements
- width
* height
;
803 nv50_clear_buffer_push(pipe
, res
, offset
, width
* data_size
,
807 nv50
->dirty_3d
|= NV50_NEW_3D_FRAMEBUFFER
| NV50_NEW_3D_SCISSOR
;
810 /* =============================== BLIT CODE ===================================
815 struct nv50_program
*fp
[NV50_BLIT_MAX_TEXTURE_TYPES
][NV50_BLIT_MODES
];
816 struct nv50_program vp
;
818 struct nv50_tsc_entry sampler
[2]; /* nearest, bilinear */
825 struct nv50_context
*nv50
;
826 struct nv50_program
*fp
;
830 uint8_t render_condition_enable
;
831 enum pipe_texture_target target
;
833 struct pipe_framebuffer_state fb
;
834 struct nv50_window_rect_stateobj window_rect
;
835 struct nv50_rasterizer_stateobj
*rast
;
836 struct nv50_program
*vp
;
837 struct nv50_program
*gp
;
838 struct nv50_program
*fp
;
839 unsigned num_textures
[3];
840 unsigned num_samplers
[3];
841 struct pipe_sampler_view
*texture
[2];
842 struct nv50_tsc_entry
*sampler
[2];
843 unsigned min_samples
;
846 struct nv50_rasterizer_stateobj rast
;
850 nv50_blitter_make_vp(struct nv50_blitter
*blit
)
852 static const uint32_t code
[] =
854 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
855 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
856 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
857 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
858 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
861 blit
->vp
.type
= PIPE_SHADER_VERTEX
;
862 blit
->vp
.translated
= true;
863 blit
->vp
.code
= (uint32_t *)code
; /* const_cast */
864 blit
->vp
.code_size
= sizeof(code
);
865 blit
->vp
.max_gpr
= 4;
866 blit
->vp
.max_out
= 5;
868 blit
->vp
.out
[0].mask
= 0x3;
869 blit
->vp
.out
[0].sn
= TGSI_SEMANTIC_POSITION
;
870 blit
->vp
.out
[1].hw
= 2;
871 blit
->vp
.out
[1].mask
= 0x7;
872 blit
->vp
.out
[1].sn
= TGSI_SEMANTIC_GENERIC
;
873 blit
->vp
.out
[1].si
= 0;
874 blit
->vp
.vp
.attrs
[0] = 0x73;
875 blit
->vp
.vp
.psiz
= 0x40;
876 blit
->vp
.vp
.edgeflag
= 0x40;
880 nv50_blitter_make_fp(struct pipe_context
*pipe
,
882 enum pipe_texture_target ptarg
)
884 struct ureg_program
*ureg
;
887 struct ureg_dst data
;
889 const unsigned target
= nv50_blit_get_tgsi_texture_target(ptarg
);
891 bool tex_rgbaz
= false;
893 bool cvt_un8
= false;
895 bool int_clamp
= mode
== NV50_BLIT_MODE_INT_CLAMP
;
897 mode
= NV50_BLIT_MODE_PASS
;
899 if (mode
!= NV50_BLIT_MODE_PASS
&&
900 mode
!= NV50_BLIT_MODE_Z24X8
&&
901 mode
!= NV50_BLIT_MODE_X8Z24
)
904 if (mode
!= NV50_BLIT_MODE_X24S8
&&
905 mode
!= NV50_BLIT_MODE_S8X24
&&
906 mode
!= NV50_BLIT_MODE_XS
)
909 if (mode
!= NV50_BLIT_MODE_PASS
&&
910 mode
!= NV50_BLIT_MODE_ZS
&&
911 mode
!= NV50_BLIT_MODE_XS
)
914 ureg
= ureg_create(PIPE_SHADER_FRAGMENT
);
918 out
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_COLOR
, 0);
919 tc
= ureg_DECL_fs_input(
920 ureg
, TGSI_SEMANTIC_GENERIC
, 0, TGSI_INTERPOLATE_LINEAR
);
922 if (ptarg
== PIPE_TEXTURE_1D_ARRAY
) {
923 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
924 tc
= ureg_swizzle(tc
, TGSI_SWIZZLE_X
, TGSI_SWIZZLE_Z
,
925 TGSI_SWIZZLE_Z
, TGSI_SWIZZLE_Z
);
928 data
= ureg_DECL_temporary(ureg
);
931 ureg_TEX(ureg
, ureg_writemask(data
, TGSI_WRITEMASK_X
),
932 target
, tc
, ureg_DECL_sampler(ureg
, 1));
933 ureg_MOV(ureg
, ureg_writemask(data
, TGSI_WRITEMASK_Y
),
934 ureg_scalar(ureg_src(data
), TGSI_SWIZZLE_X
));
937 const unsigned mask
= (mode
== NV50_BLIT_MODE_PASS
) ?
938 TGSI_WRITEMASK_XYZW
: TGSI_WRITEMASK_X
;
939 ureg_TEX(ureg
, ureg_writemask(data
, mask
),
940 target
, tc
, ureg_DECL_sampler(ureg
, 0));
943 /* handle signed to unsigned integer conversions */
945 ureg_UMIN(ureg
, data
, ureg_src(data
), ureg_imm1u(ureg
, 0x7fffffff));
948 struct ureg_src mask
;
949 struct ureg_src scale
;
950 struct ureg_dst outz
;
951 struct ureg_dst outs
;
952 struct ureg_dst zdst3
= ureg_writemask(data
, TGSI_WRITEMASK_XYZ
);
953 struct ureg_dst zdst
= ureg_writemask(data
, TGSI_WRITEMASK_X
);
954 struct ureg_dst sdst
= ureg_writemask(data
, TGSI_WRITEMASK_Y
);
955 struct ureg_src zsrc3
= ureg_src(data
);
956 struct ureg_src zsrc
= ureg_scalar(zsrc3
, TGSI_SWIZZLE_X
);
957 struct ureg_src ssrc
= ureg_scalar(zsrc3
, TGSI_SWIZZLE_Y
);
958 struct ureg_src zshuf
;
960 mask
= ureg_imm3u(ureg
, 0x0000ff, 0x00ff00, 0xff0000);
961 scale
= ureg_imm4f(ureg
,
962 1.0f
/ 0x0000ff, 1.0f
/ 0x00ff00, 1.0f
/ 0xff0000,
965 if (mode
== NV50_BLIT_MODE_Z24S8
||
966 mode
== NV50_BLIT_MODE_X24S8
||
967 mode
== NV50_BLIT_MODE_Z24X8
) {
968 outz
= ureg_writemask(out
, TGSI_WRITEMASK_XYZ
);
969 outs
= ureg_writemask(out
, TGSI_WRITEMASK_W
);
970 zshuf
= ureg_src(data
);
972 outz
= ureg_writemask(out
, TGSI_WRITEMASK_YZW
);
973 outs
= ureg_writemask(out
, TGSI_WRITEMASK_X
);
974 zshuf
= ureg_swizzle(zsrc3
, TGSI_SWIZZLE_W
,
975 TGSI_SWIZZLE_X
, TGSI_SWIZZLE_Y
, TGSI_SWIZZLE_Z
);
979 ureg_I2F(ureg
, sdst
, ssrc
);
980 ureg_MUL(ureg
, outs
, ssrc
, ureg_scalar(scale
, TGSI_SWIZZLE_X
));
984 ureg_MUL(ureg
, zdst
, zsrc
, ureg_scalar(scale
, TGSI_SWIZZLE_W
));
985 ureg_F2I(ureg
, zdst
, zsrc
);
986 ureg_AND(ureg
, zdst3
, zsrc
, mask
);
987 ureg_I2F(ureg
, zdst3
, zsrc3
);
988 ureg_MUL(ureg
, zdst3
, zsrc3
, scale
);
989 ureg_MOV(ureg
, outz
, zshuf
);
992 unsigned mask
= TGSI_WRITEMASK_XYZW
;
994 if (mode
!= NV50_BLIT_MODE_PASS
) {
995 mask
&= ~TGSI_WRITEMASK_ZW
;
997 mask
= TGSI_WRITEMASK_X
;
999 mask
= TGSI_WRITEMASK_Y
;
1001 ureg_MOV(ureg
, ureg_writemask(out
, mask
), ureg_src(data
));
1005 return ureg_create_shader_and_destroy(ureg
, pipe
);
1009 nv50_blitter_make_sampler(struct nv50_blitter
*blit
)
1011 /* clamp to edge, min/max lod = 0, nearest filtering */
1013 blit
->sampler
[0].id
= -1;
1015 blit
->sampler
[0].tsc
[0] = G80_TSC_0_SRGB_CONVERSION
|
1016 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_U__SHIFT
) |
1017 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_V__SHIFT
) |
1018 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_P__SHIFT
);
1019 blit
->sampler
[0].tsc
[1] =
1020 G80_TSC_1_MAG_FILTER_NEAREST
|
1021 G80_TSC_1_MIN_FILTER_NEAREST
|
1022 G80_TSC_1_MIP_FILTER_NONE
;
1024 /* clamp to edge, min/max lod = 0, bilinear filtering */
1026 blit
->sampler
[1].id
= -1;
1028 blit
->sampler
[1].tsc
[0] = blit
->sampler
[0].tsc
[0];
1029 blit
->sampler
[1].tsc
[1] =
1030 G80_TSC_1_MAG_FILTER_LINEAR
|
1031 G80_TSC_1_MIN_FILTER_LINEAR
|
1032 G80_TSC_1_MIP_FILTER_NONE
;
1036 nv50_blit_select_mode(const struct pipe_blit_info
*info
)
1038 const unsigned mask
= info
->mask
;
1040 switch (info
->dst
.resource
->format
) {
1041 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1042 case PIPE_FORMAT_Z24X8_UNORM
:
1043 case PIPE_FORMAT_X24S8_UINT
:
1044 switch (mask
& PIPE_MASK_ZS
) {
1045 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_Z24S8
;
1046 case PIPE_MASK_Z
: return NV50_BLIT_MODE_Z24X8
;
1048 return NV50_BLIT_MODE_X24S8
;
1050 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1051 case PIPE_FORMAT_X8Z24_UNORM
:
1052 case PIPE_FORMAT_S8X24_UINT
:
1053 switch (mask
& PIPE_MASK_ZS
) {
1054 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_S8Z24
;
1055 case PIPE_MASK_Z
: return NV50_BLIT_MODE_X8Z24
;
1057 return NV50_BLIT_MODE_S8X24
;
1059 case PIPE_FORMAT_Z32_FLOAT
:
1060 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1061 case PIPE_FORMAT_X32_S8X24_UINT
:
1062 switch (mask
& PIPE_MASK_ZS
) {
1063 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_ZS
;
1064 case PIPE_MASK_Z
: return NV50_BLIT_MODE_PASS
;
1066 return NV50_BLIT_MODE_XS
;
1069 if (util_format_is_pure_uint(info
->src
.format
) &&
1070 util_format_is_pure_sint(info
->dst
.format
))
1071 return NV50_BLIT_MODE_INT_CLAMP
;
1072 return NV50_BLIT_MODE_PASS
;
1077 nv50_blit_select_fp(struct nv50_blitctx
*ctx
, const struct pipe_blit_info
*info
)
1079 struct nv50_blitter
*blitter
= ctx
->nv50
->screen
->blitter
;
1081 const enum pipe_texture_target ptarg
=
1082 nv50_blit_reinterpret_pipe_texture_target(info
->src
.resource
->target
);
1084 const unsigned targ
= nv50_blit_texture_type(ptarg
);
1085 const unsigned mode
= ctx
->mode
;
1087 if (!blitter
->fp
[targ
][mode
]) {
1088 mtx_lock(&blitter
->mutex
);
1089 if (!blitter
->fp
[targ
][mode
])
1090 blitter
->fp
[targ
][mode
] =
1091 nv50_blitter_make_fp(&ctx
->nv50
->base
.pipe
, mode
, ptarg
);
1092 mtx_unlock(&blitter
->mutex
);
1094 ctx
->fp
= blitter
->fp
[targ
][mode
];
1098 nv50_blit_set_dst(struct nv50_blitctx
*ctx
,
1099 struct pipe_resource
*res
, unsigned level
, unsigned layer
,
1100 enum pipe_format format
)
1102 struct nv50_context
*nv50
= ctx
->nv50
;
1103 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
1104 struct pipe_surface templ
;
1106 if (util_format_is_depth_or_stencil(format
))
1107 templ
.format
= nv50_blit_zeta_to_colour_format(format
);
1109 templ
.format
= format
;
1111 templ
.u
.tex
.level
= level
;
1112 templ
.u
.tex
.first_layer
= templ
.u
.tex
.last_layer
= layer
;
1115 templ
.u
.tex
.first_layer
= 0;
1116 templ
.u
.tex
.last_layer
=
1117 (res
->target
== PIPE_TEXTURE_3D
? res
->depth0
: res
->array_size
) - 1;
1120 nv50
->framebuffer
.cbufs
[0] = nv50_miptree_surface_new(pipe
, res
, &templ
);
1121 nv50
->framebuffer
.nr_cbufs
= 1;
1122 nv50
->framebuffer
.zsbuf
= NULL
;
1123 nv50
->framebuffer
.width
= nv50
->framebuffer
.cbufs
[0]->width
;
1124 nv50
->framebuffer
.height
= nv50
->framebuffer
.cbufs
[0]->height
;
1128 nv50_blit_set_src(struct nv50_blitctx
*blit
,
1129 struct pipe_resource
*res
, unsigned level
, unsigned layer
,
1130 enum pipe_format format
, const uint8_t filter
)
1132 struct nv50_context
*nv50
= blit
->nv50
;
1133 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
1134 struct pipe_sampler_view templ
;
1136 enum pipe_texture_target target
;
1138 target
= nv50_blit_reinterpret_pipe_texture_target(res
->target
);
1140 templ
.format
= format
;
1141 templ
.u
.tex
.first_level
= templ
.u
.tex
.last_level
= level
;
1142 templ
.u
.tex
.first_layer
= templ
.u
.tex
.last_layer
= layer
;
1143 templ
.swizzle_r
= PIPE_SWIZZLE_X
;
1144 templ
.swizzle_g
= PIPE_SWIZZLE_Y
;
1145 templ
.swizzle_b
= PIPE_SWIZZLE_Z
;
1146 templ
.swizzle_a
= PIPE_SWIZZLE_W
;
1149 templ
.u
.tex
.first_layer
= 0;
1150 templ
.u
.tex
.last_layer
=
1151 (res
->target
== PIPE_TEXTURE_3D
? res
->depth0
: res
->array_size
) - 1;
1154 flags
= res
->last_level
? 0 : NV50_TEXVIEW_SCALED_COORDS
;
1155 flags
|= NV50_TEXVIEW_ACCESS_RESOLVE
;
1156 if (filter
&& res
->nr_samples
== 8)
1157 flags
|= NV50_TEXVIEW_FILTER_MSAA8
;
1159 nv50
->textures
[2][0] = nv50_create_texture_view(
1160 pipe
, res
, &templ
, flags
, target
);
1161 nv50
->textures
[2][1] = NULL
;
1163 nv50
->num_textures
[0] = nv50
->num_textures
[1] = 0;
1164 nv50
->num_textures
[2] = 1;
1166 templ
.format
= nv50_zs_to_s_format(format
);
1167 if (templ
.format
!= res
->format
) {
1168 nv50
->textures
[2][1] = nv50_create_texture_view(
1169 pipe
, res
, &templ
, flags
, target
);
1170 nv50
->num_textures
[2] = 2;
1175 nv50_blitctx_prepare_state(struct nv50_blitctx
*blit
)
1177 struct nouveau_pushbuf
*push
= blit
->nv50
->base
.pushbuf
;
1179 if (blit
->nv50
->cond_query
&& !blit
->render_condition_enable
) {
1180 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
1181 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
1185 BEGIN_NV04(push
, NV50_3D(COLOR_MASK(0)), 1);
1186 PUSH_DATA (push
, blit
->color_mask
);
1187 BEGIN_NV04(push
, NV50_3D(BLEND_ENABLE(0)), 1);
1188 PUSH_DATA (push
, 0);
1189 BEGIN_NV04(push
, NV50_3D(LOGIC_OP_ENABLE
), 1);
1190 PUSH_DATA (push
, 0);
1192 /* rasterizer state */
1193 #ifndef NV50_SCISSORS_CLIPPING
1194 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(0)), 1);
1195 PUSH_DATA (push
, 1);
1197 BEGIN_NV04(push
, NV50_3D(VERTEX_TWO_SIDE_ENABLE
), 1);
1198 PUSH_DATA (push
, 0);
1199 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
1200 PUSH_DATA (push
, 0);
1201 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
1202 PUSH_DATA (push
, 0);
1203 BEGIN_NV04(push
, NV50_3D(MSAA_MASK(0)), 4);
1204 PUSH_DATA (push
, 0xffff);
1205 PUSH_DATA (push
, 0xffff);
1206 PUSH_DATA (push
, 0xffff);
1207 PUSH_DATA (push
, 0xffff);
1208 BEGIN_NV04(push
, NV50_3D(POLYGON_MODE_FRONT
), 3);
1209 PUSH_DATA (push
, NV50_3D_POLYGON_MODE_FRONT_FILL
);
1210 PUSH_DATA (push
, NV50_3D_POLYGON_MODE_BACK_FILL
);
1211 PUSH_DATA (push
, 0);
1212 BEGIN_NV04(push
, NV50_3D(CULL_FACE_ENABLE
), 1);
1213 PUSH_DATA (push
, 0);
1214 BEGIN_NV04(push
, NV50_3D(POLYGON_STIPPLE_ENABLE
), 1);
1215 PUSH_DATA (push
, 0);
1216 BEGIN_NV04(push
, NV50_3D(POLYGON_OFFSET_FILL_ENABLE
), 1);
1217 PUSH_DATA (push
, 0);
1220 BEGIN_NV04(push
, NV50_3D(DEPTH_TEST_ENABLE
), 1);
1221 PUSH_DATA (push
, 0);
1222 BEGIN_NV04(push
, NV50_3D(DEPTH_BOUNDS_EN
), 1);
1223 PUSH_DATA (push
, 0);
1224 BEGIN_NV04(push
, NV50_3D(STENCIL_ENABLE
), 1);
1225 PUSH_DATA (push
, 0);
1226 BEGIN_NV04(push
, NV50_3D(ALPHA_TEST_ENABLE
), 1);
1227 PUSH_DATA (push
, 0);
1231 nv50_blitctx_pre_blit(struct nv50_blitctx
*ctx
,
1232 const struct pipe_blit_info
*info
)
1234 struct nv50_context
*nv50
= ctx
->nv50
;
1235 struct nv50_blitter
*blitter
= nv50
->screen
->blitter
;
1238 ctx
->saved
.fb
.width
= nv50
->framebuffer
.width
;
1239 ctx
->saved
.fb
.height
= nv50
->framebuffer
.height
;
1240 ctx
->saved
.fb
.nr_cbufs
= nv50
->framebuffer
.nr_cbufs
;
1241 ctx
->saved
.fb
.cbufs
[0] = nv50
->framebuffer
.cbufs
[0];
1242 ctx
->saved
.fb
.zsbuf
= nv50
->framebuffer
.zsbuf
;
1244 ctx
->saved
.rast
= nv50
->rast
;
1246 ctx
->saved
.vp
= nv50
->vertprog
;
1247 ctx
->saved
.gp
= nv50
->gmtyprog
;
1248 ctx
->saved
.fp
= nv50
->fragprog
;
1250 ctx
->saved
.min_samples
= nv50
->min_samples
;
1251 ctx
->saved
.window_rect
= nv50
->window_rect
;
1253 nv50
->rast
= &ctx
->rast
;
1255 nv50
->vertprog
= &blitter
->vp
;
1256 nv50
->gmtyprog
= NULL
;
1257 nv50
->fragprog
= ctx
->fp
;
1259 nv50
->window_rect
.rects
=
1260 MIN2(info
->num_window_rectangles
, NV50_MAX_WINDOW_RECTANGLES
);
1261 nv50
->window_rect
.inclusive
= info
->window_rectangle_include
;
1262 if (nv50
->window_rect
.rects
)
1263 memcpy(nv50
->window_rect
.rect
, info
->window_rectangles
,
1264 sizeof(struct pipe_scissor_state
) * nv50
->window_rect
.rects
);
1266 for (s
= 0; s
< 3; ++s
) {
1267 ctx
->saved
.num_textures
[s
] = nv50
->num_textures
[s
];
1268 ctx
->saved
.num_samplers
[s
] = nv50
->num_samplers
[s
];
1270 ctx
->saved
.texture
[0] = nv50
->textures
[2][0];
1271 ctx
->saved
.texture
[1] = nv50
->textures
[2][1];
1272 ctx
->saved
.sampler
[0] = nv50
->samplers
[2][0];
1273 ctx
->saved
.sampler
[1] = nv50
->samplers
[2][1];
1275 nv50
->samplers
[2][0] = &blitter
->sampler
[ctx
->filter
];
1276 nv50
->samplers
[2][1] = &blitter
->sampler
[ctx
->filter
];
1278 nv50
->num_samplers
[0] = nv50
->num_samplers
[1] = 0;
1279 nv50
->num_samplers
[2] = 2;
1281 nv50
->min_samples
= 1;
1283 ctx
->saved
.dirty_3d
= nv50
->dirty_3d
;
1285 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_3D_FB
);
1286 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_3D_TEXTURES
);
1289 NV50_NEW_3D_FRAMEBUFFER
| NV50_NEW_3D_MIN_SAMPLES
|
1290 NV50_NEW_3D_VERTPROG
| NV50_NEW_3D_FRAGPROG
| NV50_NEW_3D_GMTYPROG
|
1291 NV50_NEW_3D_TEXTURES
| NV50_NEW_3D_SAMPLERS
| NV50_NEW_3D_WINDOW_RECTS
;
1295 nv50_blitctx_post_blit(struct nv50_blitctx
*blit
)
1297 struct nv50_context
*nv50
= blit
->nv50
;
1300 pipe_surface_reference(&nv50
->framebuffer
.cbufs
[0], NULL
);
1302 nv50
->framebuffer
.width
= blit
->saved
.fb
.width
;
1303 nv50
->framebuffer
.height
= blit
->saved
.fb
.height
;
1304 nv50
->framebuffer
.nr_cbufs
= blit
->saved
.fb
.nr_cbufs
;
1305 nv50
->framebuffer
.cbufs
[0] = blit
->saved
.fb
.cbufs
[0];
1306 nv50
->framebuffer
.zsbuf
= blit
->saved
.fb
.zsbuf
;
1308 nv50
->rast
= blit
->saved
.rast
;
1310 nv50
->vertprog
= blit
->saved
.vp
;
1311 nv50
->gmtyprog
= blit
->saved
.gp
;
1312 nv50
->fragprog
= blit
->saved
.fp
;
1314 nv50
->min_samples
= blit
->saved
.min_samples
;
1315 nv50
->window_rect
= blit
->saved
.window_rect
;
1317 pipe_sampler_view_reference(&nv50
->textures
[2][0], NULL
);
1318 pipe_sampler_view_reference(&nv50
->textures
[2][1], NULL
);
1320 for (s
= 0; s
< 3; ++s
) {
1321 nv50
->num_textures
[s
] = blit
->saved
.num_textures
[s
];
1322 nv50
->num_samplers
[s
] = blit
->saved
.num_samplers
[s
];
1324 nv50
->textures
[2][0] = blit
->saved
.texture
[0];
1325 nv50
->textures
[2][1] = blit
->saved
.texture
[1];
1326 nv50
->samplers
[2][0] = blit
->saved
.sampler
[0];
1327 nv50
->samplers
[2][1] = blit
->saved
.sampler
[1];
1329 if (nv50
->cond_query
&& !blit
->render_condition_enable
)
1330 nv50
->base
.pipe
.render_condition(&nv50
->base
.pipe
, nv50
->cond_query
,
1331 nv50
->cond_cond
, nv50
->cond_mode
);
1333 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_3D_FB
);
1334 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_3D_TEXTURES
);
1336 nv50
->dirty_3d
= blit
->saved
.dirty_3d
|
1337 (NV50_NEW_3D_FRAMEBUFFER
| NV50_NEW_3D_SCISSOR
| NV50_NEW_3D_SAMPLE_MASK
|
1338 NV50_NEW_3D_RASTERIZER
| NV50_NEW_3D_ZSA
| NV50_NEW_3D_BLEND
|
1339 NV50_NEW_3D_TEXTURES
| NV50_NEW_3D_SAMPLERS
| NV50_NEW_3D_WINDOW_RECTS
|
1340 NV50_NEW_3D_VERTPROG
| NV50_NEW_3D_GMTYPROG
| NV50_NEW_3D_FRAGPROG
);
1341 nv50
->scissors_dirty
|= 1;
1343 nv50
->base
.pipe
.set_min_samples(&nv50
->base
.pipe
, blit
->saved
.min_samples
);
1348 nv50_blit_3d(struct nv50_context
*nv50
, const struct pipe_blit_info
*info
)
1350 struct nv50_blitctx
*blit
= nv50
->blit
;
1351 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
1352 struct pipe_resource
*src
= info
->src
.resource
;
1353 struct pipe_resource
*dst
= info
->dst
.resource
;
1354 int32_t minx
, maxx
, miny
, maxy
;
1356 float x0
, x1
, y0
, y1
, z
;
1358 float x_range
, y_range
;
1360 blit
->mode
= nv50_blit_select_mode(info
);
1361 blit
->color_mask
= nv50_blit_derive_color_mask(info
);
1362 blit
->filter
= nv50_blit_get_filter(info
);
1363 blit
->render_condition_enable
= info
->render_condition_enable
;
1365 nv50_blit_select_fp(blit
, info
);
1366 nv50_blitctx_pre_blit(blit
, info
);
1368 nv50_blit_set_dst(blit
, dst
, info
->dst
.level
, -1, info
->dst
.format
);
1369 nv50_blit_set_src(blit
, src
, info
->src
.level
, -1, info
->src
.format
,
1372 nv50_blitctx_prepare_state(blit
);
1374 nv50_state_validate_3d(nv50
, ~0);
1376 x_range
= (float)info
->src
.box
.width
/ (float)info
->dst
.box
.width
;
1377 y_range
= (float)info
->src
.box
.height
/ (float)info
->dst
.box
.height
;
1379 x0
= (float)info
->src
.box
.x
- x_range
* (float)info
->dst
.box
.x
;
1380 y0
= (float)info
->src
.box
.y
- y_range
* (float)info
->dst
.box
.y
;
1382 x1
= x0
+ 16384.0f
* x_range
;
1383 y1
= y0
+ 16384.0f
* y_range
;
1385 x0
*= (float)(1 << nv50_miptree(src
)->ms_x
);
1386 x1
*= (float)(1 << nv50_miptree(src
)->ms_x
);
1387 y0
*= (float)(1 << nv50_miptree(src
)->ms_y
);
1388 y1
*= (float)(1 << nv50_miptree(src
)->ms_y
);
1390 /* XXX: multiply by 6 for cube arrays ? */
1391 dz
= (float)info
->src
.box
.depth
/ (float)info
->dst
.box
.depth
;
1392 z
= (float)info
->src
.box
.z
;
1393 if (nv50_miptree(src
)->layout_3d
)
1396 if (src
->last_level
> 0) {
1397 /* If there are mip maps, GPU always assumes normalized coordinates. */
1398 const unsigned l
= info
->src
.level
;
1399 const float fh
= u_minify(src
->width0
<< nv50_miptree(src
)->ms_x
, l
);
1400 const float fv
= u_minify(src
->height0
<< nv50_miptree(src
)->ms_y
, l
);
1405 if (nv50_miptree(src
)->layout_3d
) {
1406 z
/= u_minify(src
->depth0
, l
);
1407 dz
/= u_minify(src
->depth0
, l
);
1411 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
1412 PUSH_DATA (push
, 0);
1413 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
1414 PUSH_DATA (push
, 0x1);
1416 /* Draw a large triangle in screen coordinates covering the whole
1417 * render target, with scissors defining the destination region.
1418 * The vertex is supplied with non-normalized texture coordinates
1419 * arranged in a way to yield the desired offset and scale.
1422 minx
= info
->dst
.box
.x
;
1423 maxx
= info
->dst
.box
.x
+ info
->dst
.box
.width
;
1424 miny
= info
->dst
.box
.y
;
1425 maxy
= info
->dst
.box
.y
+ info
->dst
.box
.height
;
1426 if (info
->scissor_enable
) {
1427 minx
= MAX2(minx
, info
->scissor
.minx
);
1428 maxx
= MIN2(maxx
, info
->scissor
.maxx
);
1429 miny
= MAX2(miny
, info
->scissor
.miny
);
1430 maxy
= MIN2(maxy
, info
->scissor
.maxy
);
1432 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
1433 PUSH_DATA (push
, (maxx
<< 16) | minx
);
1434 PUSH_DATA (push
, (maxy
<< 16) | miny
);
1436 for (i
= 0; i
< info
->dst
.box
.depth
; ++i
, z
+= dz
) {
1437 if (info
->dst
.box
.z
+ i
) {
1438 BEGIN_NV04(push
, NV50_3D(LAYER
), 1);
1439 PUSH_DATA (push
, info
->dst
.box
.z
+ i
);
1441 PUSH_SPACE(push
, 32);
1442 BEGIN_NV04(push
, NV50_3D(VERTEX_BEGIN_GL
), 1);
1443 PUSH_DATA (push
, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES
);
1444 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1445 PUSH_DATAf(push
, x0
);
1446 PUSH_DATAf(push
, y0
);
1447 PUSH_DATAf(push
, z
);
1448 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1449 PUSH_DATAf(push
, 0.0f
);
1450 PUSH_DATAf(push
, 0.0f
);
1451 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1452 PUSH_DATAf(push
, x1
);
1453 PUSH_DATAf(push
, y0
);
1454 PUSH_DATAf(push
, z
);
1455 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1456 PUSH_DATAf(push
, 16384.0f
);
1457 PUSH_DATAf(push
, 0.0f
);
1458 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1459 PUSH_DATAf(push
, x0
);
1460 PUSH_DATAf(push
, y1
);
1461 PUSH_DATAf(push
, z
);
1462 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1463 PUSH_DATAf(push
, 0.0f
);
1464 PUSH_DATAf(push
, 16384.0f
);
1465 BEGIN_NV04(push
, NV50_3D(VERTEX_END_GL
), 1);
1466 PUSH_DATA (push
, 0);
1468 if (info
->dst
.box
.z
+ info
->dst
.box
.depth
- 1) {
1469 BEGIN_NV04(push
, NV50_3D(LAYER
), 1);
1470 PUSH_DATA (push
, 0);
1473 /* re-enable normally constant state */
1475 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
1476 PUSH_DATA (push
, 1);
1478 nv50_blitctx_post_blit(blit
);
1482 nv50_blit_eng2d(struct nv50_context
*nv50
, const struct pipe_blit_info
*info
)
1484 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
1485 struct nv50_miptree
*dst
= nv50_miptree(info
->dst
.resource
);
1486 struct nv50_miptree
*src
= nv50_miptree(info
->src
.resource
);
1487 const int32_t srcx_adj
= info
->src
.box
.width
< 0 ? -1 : 0;
1488 const int32_t srcy_adj
= info
->src
.box
.height
< 0 ? -1 : 0;
1489 const int32_t dz
= info
->dst
.box
.z
;
1490 const int32_t sz
= info
->src
.box
.z
;
1491 uint32_t dstw
, dsth
;
1494 int64_t du_dx
, dv_dy
;
1497 uint32_t mask
= nv50_blit_eng2d_get_mask(info
);
1500 mode
= nv50_blit_get_filter(info
) ?
1501 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR
:
1502 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE
;
1503 mode
|= (src
->base
.base
.nr_samples
> dst
->base
.base
.nr_samples
) ?
1504 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER
: NV50_2D_BLIT_CONTROL_ORIGIN_CENTER
;
1506 du_dx
= ((int64_t)info
->src
.box
.width
<< 32) / info
->dst
.box
.width
;
1507 dv_dy
= ((int64_t)info
->src
.box
.height
<< 32) / info
->dst
.box
.height
;
1509 b
= info
->dst
.format
== info
->src
.format
;
1510 nv50_2d_texture_set(push
, 1, dst
, info
->dst
.level
, dz
, info
->dst
.format
, b
);
1511 nv50_2d_texture_set(push
, 0, src
, info
->src
.level
, sz
, info
->src
.format
, b
);
1513 if (info
->scissor_enable
) {
1514 BEGIN_NV04(push
, NV50_2D(CLIP_X
), 5);
1515 PUSH_DATA (push
, info
->scissor
.minx
<< dst
->ms_x
);
1516 PUSH_DATA (push
, info
->scissor
.miny
<< dst
->ms_y
);
1517 PUSH_DATA (push
, (info
->scissor
.maxx
- info
->scissor
.minx
) << dst
->ms_x
);
1518 PUSH_DATA (push
, (info
->scissor
.maxy
- info
->scissor
.miny
) << dst
->ms_y
);
1519 PUSH_DATA (push
, 1); /* enable */
1522 if (nv50
->cond_query
&& info
->render_condition_enable
) {
1523 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
1524 PUSH_DATA (push
, nv50
->cond_condmode
);
1527 if (mask
!= 0xffffffff) {
1528 BEGIN_NV04(push
, NV50_2D(ROP
), 1);
1529 PUSH_DATA (push
, 0xca); /* DPSDxax */
1530 BEGIN_NV04(push
, NV50_2D(PATTERN_COLOR_FORMAT
), 1);
1531 PUSH_DATA (push
, NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8
);
1532 BEGIN_NV04(push
, NV50_2D(PATTERN_BITMAP_COLOR(0)), 4);
1533 PUSH_DATA (push
, 0x00000000);
1534 PUSH_DATA (push
, mask
);
1535 PUSH_DATA (push
, 0xffffffff);
1536 PUSH_DATA (push
, 0xffffffff);
1537 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
1538 PUSH_DATA (push
, NV50_2D_OPERATION_ROP
);
1540 if (info
->src
.format
!= info
->dst
.format
) {
1541 if (info
->src
.format
== PIPE_FORMAT_R8_UNORM
||
1542 info
->src
.format
== PIPE_FORMAT_R16_UNORM
||
1543 info
->src
.format
== PIPE_FORMAT_R16_FLOAT
||
1544 info
->src
.format
== PIPE_FORMAT_R32_FLOAT
) {
1545 mask
= 0xffff0000; /* also makes condition for OPERATION reset true */
1546 BEGIN_NV04(push
, NV50_2D(BETA4
), 2);
1547 PUSH_DATA (push
, mask
);
1548 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY_PREMULT
);
1552 if (src
->ms_x
> dst
->ms_x
|| src
->ms_y
> dst
->ms_y
) {
1553 /* ms_x is always >= ms_y */
1554 du_dx
<<= src
->ms_x
- dst
->ms_x
;
1555 dv_dy
<<= src
->ms_y
- dst
->ms_y
;
1557 du_dx
>>= dst
->ms_x
- src
->ms_x
;
1558 dv_dy
>>= dst
->ms_y
- src
->ms_y
;
1561 srcx
= (int64_t)(info
->src
.box
.x
+ srcx_adj
) << (src
->ms_x
+ 32);
1562 srcy
= (int64_t)(info
->src
.box
.y
+ srcy_adj
) << (src
->ms_y
+ 32);
1564 if (src
->base
.base
.nr_samples
> dst
->base
.base
.nr_samples
) {
1565 /* center src coorinates for proper MS resolve filtering */
1566 srcx
+= (int64_t)1 << (src
->ms_x
+ 31);
1567 srcy
+= (int64_t)1 << (src
->ms_y
+ 31);
1570 dstx
= info
->dst
.box
.x
<< dst
->ms_x
;
1571 dsty
= info
->dst
.box
.y
<< dst
->ms_y
;
1573 dstw
= info
->dst
.box
.width
<< dst
->ms_x
;
1574 dsth
= info
->dst
.box
.height
<< dst
->ms_y
;
1578 srcx
-= du_dx
* dstx
;
1583 srcy
-= dv_dy
* dsty
;
1587 BEGIN_NV04(push
, NV50_2D(BLIT_CONTROL
), 1);
1588 PUSH_DATA (push
, mode
);
1589 BEGIN_NV04(push
, NV50_2D(BLIT_DST_X
), 4);
1590 PUSH_DATA (push
, dstx
);
1591 PUSH_DATA (push
, dsty
);
1592 PUSH_DATA (push
, dstw
);
1593 PUSH_DATA (push
, dsth
);
1594 BEGIN_NV04(push
, NV50_2D(BLIT_DU_DX_FRACT
), 4);
1595 PUSH_DATA (push
, du_dx
);
1596 PUSH_DATA (push
, du_dx
>> 32);
1597 PUSH_DATA (push
, dv_dy
);
1598 PUSH_DATA (push
, dv_dy
>> 32);
1600 BCTX_REFN(nv50
->bufctx
, 2D
, &dst
->base
, WR
);
1601 BCTX_REFN(nv50
->bufctx
, 2D
, &src
->base
, RD
);
1602 nouveau_pushbuf_bufctx(nv50
->base
.pushbuf
, nv50
->bufctx
);
1603 if (nouveau_pushbuf_validate(nv50
->base
.pushbuf
))
1606 for (i
= 0; i
< info
->dst
.box
.depth
; ++i
) {
1608 /* no scaling in z-direction possible for eng2d blits */
1609 if (dst
->layout_3d
) {
1610 BEGIN_NV04(push
, NV50_2D(DST_LAYER
), 1);
1611 PUSH_DATA (push
, info
->dst
.box
.z
+ i
);
1613 const unsigned z
= info
->dst
.box
.z
+ i
;
1614 const uint64_t address
= dst
->base
.address
+
1615 dst
->level
[info
->dst
.level
].offset
+
1616 z
* dst
->layer_stride
;
1617 BEGIN_NV04(push
, NV50_2D(DST_ADDRESS_HIGH
), 2);
1618 PUSH_DATAh(push
, address
);
1619 PUSH_DATA (push
, address
);
1621 if (src
->layout_3d
) {
1622 /* not possible because of depth tiling */
1625 const unsigned z
= info
->src
.box
.z
+ i
;
1626 const uint64_t address
= src
->base
.address
+
1627 src
->level
[info
->src
.level
].offset
+
1628 z
* src
->layer_stride
;
1629 BEGIN_NV04(push
, NV50_2D(SRC_ADDRESS_HIGH
), 2);
1630 PUSH_DATAh(push
, address
);
1631 PUSH_DATA (push
, address
);
1633 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_Y_INT
), 1); /* trigger */
1634 PUSH_DATA (push
, srcy
>> 32);
1636 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_X_FRACT
), 4);
1637 PUSH_DATA (push
, srcx
);
1638 PUSH_DATA (push
, srcx
>> 32);
1639 PUSH_DATA (push
, srcy
);
1640 PUSH_DATA (push
, srcy
>> 32);
1643 nv50_bufctx_fence(nv50
->bufctx
, false);
1645 nouveau_bufctx_reset(nv50
->bufctx
, NV50_BIND_2D
);
1647 if (info
->scissor_enable
) {
1648 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
1649 PUSH_DATA (push
, 0);
1651 if (mask
!= 0xffffffff) {
1652 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
1653 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
1655 if (nv50
->cond_query
&& info
->render_condition_enable
) {
1656 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
1657 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
1662 nv50_blit(struct pipe_context
*pipe
, const struct pipe_blit_info
*info
)
1664 struct nv50_context
*nv50
= nv50_context(pipe
);
1665 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
1668 if (info
->src
.box
.width
== 0 || info
->src
.box
.height
== 0 ||
1669 info
->dst
.box
.width
== 0 || info
->dst
.box
.height
== 0) {
1670 pipe_debug_message(&nv50
->base
.debug
, ERROR
,
1671 "Blit with zero-size src or dst box");
1675 if (util_format_is_depth_or_stencil(info
->dst
.resource
->format
)) {
1676 if (!(info
->mask
& PIPE_MASK_ZS
))
1678 if (info
->dst
.resource
->format
== PIPE_FORMAT_Z32_FLOAT
||
1679 info
->dst
.resource
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)
1681 if (info
->filter
!= PIPE_TEX_FILTER_NEAREST
)
1684 if (!(info
->mask
& PIPE_MASK_RGBA
))
1686 if (info
->mask
!= PIPE_MASK_RGBA
)
1690 if (nv50_miptree(info
->src
.resource
)->layout_3d
) {
1693 if (info
->src
.box
.depth
!= info
->dst
.box
.depth
) {
1695 debug_printf("blit: cannot filter array or cube textures in z direction");
1698 if (!eng3d
&& info
->dst
.format
!= info
->src
.format
) {
1699 if (!nv50_2d_dst_format_faithful(info
->dst
.format
) ||
1700 !nv50_2d_src_format_faithful(info
->src
.format
)) {
1703 if (!nv50_2d_src_format_faithful(info
->src
.format
)) {
1704 if (!util_format_is_luminance(info
->src
.format
)) {
1705 if (util_format_is_intensity(info
->src
.format
))
1708 if (!nv50_2d_dst_format_ops_supported(info
->dst
.format
))
1711 eng3d
= !nv50_2d_format_supported(info
->src
.format
);
1714 if (util_format_is_luminance_alpha(info
->src
.format
))
1718 if (info
->src
.resource
->nr_samples
== 8 &&
1719 info
->dst
.resource
->nr_samples
<= 1)
1722 if (info
->num_window_rectangles
> 0 || info
->window_rectangle_include
)
1725 /* FIXME: can't make this work with eng2d anymore */
1726 if ((info
->src
.resource
->nr_samples
| 1) !=
1727 (info
->dst
.resource
->nr_samples
| 1))
1730 /* FIXME: find correct src coordinate adjustments */
1731 if ((info
->src
.box
.width
!= info
->dst
.box
.width
&&
1732 info
->src
.box
.width
!= -info
->dst
.box
.width
) ||
1733 (info
->src
.box
.height
!= info
->dst
.box
.height
&&
1734 info
->src
.box
.height
!= -info
->dst
.box
.height
))
1737 if (nv50
->screen
->num_occlusion_queries_active
) {
1738 BEGIN_NV04(push
, NV50_3D(SAMPLECNT_ENABLE
), 1);
1739 PUSH_DATA (push
, 0);
1743 nv50_blit_eng2d(nv50
, info
);
1745 nv50_blit_3d(nv50
, info
);
1747 if (nv50
->screen
->num_occlusion_queries_active
) {
1748 BEGIN_NV04(push
, NV50_3D(SAMPLECNT_ENABLE
), 1);
1749 PUSH_DATA (push
, 1);
1754 nv50_flush_resource(struct pipe_context
*ctx
,
1755 struct pipe_resource
*resource
)
1760 nv50_blitter_create(struct nv50_screen
*screen
)
1762 screen
->blitter
= CALLOC_STRUCT(nv50_blitter
);
1763 if (!screen
->blitter
) {
1764 NOUVEAU_ERR("failed to allocate blitter struct\n");
1768 (void) mtx_init(&screen
->blitter
->mutex
, mtx_plain
);
1770 nv50_blitter_make_vp(screen
->blitter
);
1771 nv50_blitter_make_sampler(screen
->blitter
);
1777 nv50_blitter_destroy(struct nv50_screen
*screen
)
1779 struct nv50_blitter
*blitter
= screen
->blitter
;
1782 for (i
= 0; i
< NV50_BLIT_MAX_TEXTURE_TYPES
; ++i
) {
1783 for (m
= 0; m
< NV50_BLIT_MODES
; ++m
) {
1784 struct nv50_program
*prog
= blitter
->fp
[i
][m
];
1786 nv50_program_destroy(NULL
, prog
);
1787 FREE((void *)prog
->pipe
.tokens
);
1793 mtx_destroy(&blitter
->mutex
);
1798 nv50_blitctx_create(struct nv50_context
*nv50
)
1800 nv50
->blit
= CALLOC_STRUCT(nv50_blitctx
);
1802 NOUVEAU_ERR("failed to allocate blit context\n");
1806 nv50
->blit
->nv50
= nv50
;
1808 nv50
->blit
->rast
.pipe
.half_pixel_center
= 1;
1814 nv50_init_surface_functions(struct nv50_context
*nv50
)
1816 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
1818 pipe
->resource_copy_region
= nv50_resource_copy_region
;
1819 pipe
->blit
= nv50_blit
;
1820 pipe
->flush_resource
= nv50_flush_resource
;
1821 pipe
->clear_texture
= nv50_clear_texture
;
1822 pipe
->clear_render_target
= nv50_clear_render_target
;
1823 pipe
->clear_depth_stencil
= nv50_clear_depth_stencil
;
1824 pipe
->clear_buffer
= nv50_clear_buffer
;