2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_math.h"
31 #include "util/u_surface.h"
33 #include "tgsi/tgsi_ureg.h"
35 #include "os/os_thread.h"
37 #include "nv50/nv50_context.h"
38 #include "nv50/nv50_resource.h"
40 #include "nv50/g80_defs.xml.h"
41 #include "nv50/g80_texture.xml.h"
43 /* these are used in nv50_blit.h */
44 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
45 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
47 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
48 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
50 #define NOUVEAU_DRIVER 0x50
51 #include "nv50/nv50_blit.h"
54 nv50_2d_format(enum pipe_format format
, bool dst
, bool dst_src_equal
)
56 uint8_t id
= nv50_format_table
[format
].rt
;
58 /* Hardware values for color formats range from 0xc0 to 0xff,
59 * but the 2D engine doesn't support all of them.
61 if ((id
>= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS
& (1ULL << (id
- 0xc0))))
63 assert(dst_src_equal
);
65 switch (util_format_get_blocksize(format
)) {
67 return G80_SURFACE_FORMAT_R8_UNORM
;
69 return G80_SURFACE_FORMAT_R16_UNORM
;
71 return G80_SURFACE_FORMAT_BGRA8_UNORM
;
73 return G80_SURFACE_FORMAT_RGBA16_FLOAT
;
75 return G80_SURFACE_FORMAT_RGBA32_FLOAT
;
82 nv50_2d_texture_set(struct nouveau_pushbuf
*push
, int dst
,
83 struct nv50_miptree
*mt
, unsigned level
, unsigned layer
,
84 enum pipe_format pformat
, bool dst_src_pformat_equal
)
86 struct nouveau_bo
*bo
= mt
->base
.bo
;
87 uint32_t width
, height
, depth
;
89 uint32_t mthd
= dst
? NV50_2D_DST_FORMAT
: NV50_2D_SRC_FORMAT
;
90 uint32_t offset
= mt
->level
[level
].offset
;
92 format
= nv50_2d_format(pformat
, dst
, dst_src_pformat_equal
);
94 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
95 util_format_name(pformat
));
99 width
= u_minify(mt
->base
.base
.width0
, level
) << mt
->ms_x
;
100 height
= u_minify(mt
->base
.base
.height0
, level
) << mt
->ms_y
;
101 depth
= u_minify(mt
->base
.base
.depth0
, level
);
103 offset
= mt
->level
[level
].offset
;
104 if (!mt
->layout_3d
) {
105 offset
+= mt
->layer_stride
* layer
;
110 offset
+= nv50_mt_zslice_offset(mt
, level
, layer
);
114 if (!nouveau_bo_memtype(bo
)) {
115 BEGIN_NV04(push
, SUBC_2D(mthd
), 2);
116 PUSH_DATA (push
, format
);
118 BEGIN_NV04(push
, SUBC_2D(mthd
+ 0x14), 5);
119 PUSH_DATA (push
, mt
->level
[level
].pitch
);
120 PUSH_DATA (push
, width
);
121 PUSH_DATA (push
, height
);
122 PUSH_DATAh(push
, mt
->base
.address
+ offset
);
123 PUSH_DATA (push
, mt
->base
.address
+ offset
);
125 BEGIN_NV04(push
, SUBC_2D(mthd
), 5);
126 PUSH_DATA (push
, format
);
128 PUSH_DATA (push
, mt
->level
[level
].tile_mode
);
129 PUSH_DATA (push
, depth
);
130 PUSH_DATA (push
, layer
);
131 BEGIN_NV04(push
, SUBC_2D(mthd
+ 0x18), 4);
132 PUSH_DATA (push
, width
);
133 PUSH_DATA (push
, height
);
134 PUSH_DATAh(push
, mt
->base
.address
+ offset
);
135 PUSH_DATA (push
, mt
->base
.address
+ offset
);
140 BEGIN_NV04(push
, SUBC_2D(NV50_2D_CLIP_X
), 4);
143 PUSH_DATA (push
, width
);
144 PUSH_DATA (push
, height
);
151 nv50_2d_texture_do_copy(struct nouveau_pushbuf
*push
,
152 struct nv50_miptree
*dst
, unsigned dst_level
,
153 unsigned dx
, unsigned dy
, unsigned dz
,
154 struct nv50_miptree
*src
, unsigned src_level
,
155 unsigned sx
, unsigned sy
, unsigned sz
,
156 unsigned w
, unsigned h
)
158 const enum pipe_format dfmt
= dst
->base
.base
.format
;
159 const enum pipe_format sfmt
= src
->base
.base
.format
;
161 bool eqfmt
= dfmt
== sfmt
;
163 if (!PUSH_SPACE(push
, 2 * 16 + 32))
166 ret
= nv50_2d_texture_set(push
, 1, dst
, dst_level
, dz
, dfmt
, eqfmt
);
170 ret
= nv50_2d_texture_set(push
, 0, src
, src_level
, sz
, sfmt
, eqfmt
);
174 BEGIN_NV04(push
, NV50_2D(BLIT_CONTROL
), 1);
175 PUSH_DATA (push
, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE
);
176 BEGIN_NV04(push
, NV50_2D(BLIT_DST_X
), 4);
177 PUSH_DATA (push
, dx
<< dst
->ms_x
);
178 PUSH_DATA (push
, dy
<< dst
->ms_y
);
179 PUSH_DATA (push
, w
<< dst
->ms_x
);
180 PUSH_DATA (push
, h
<< dst
->ms_y
);
181 BEGIN_NV04(push
, NV50_2D(BLIT_DU_DX_FRACT
), 4);
186 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_X_FRACT
), 4);
188 PUSH_DATA (push
, sx
<< src
->ms_x
);
190 PUSH_DATA (push
, sy
<< src
->ms_y
);
196 nv50_resource_copy_region(struct pipe_context
*pipe
,
197 struct pipe_resource
*dst
, unsigned dst_level
,
198 unsigned dstx
, unsigned dsty
, unsigned dstz
,
199 struct pipe_resource
*src
, unsigned src_level
,
200 const struct pipe_box
*src_box
)
202 struct nv50_context
*nv50
= nv50_context(pipe
);
205 unsigned dst_layer
= dstz
, src_layer
= src_box
->z
;
207 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
208 nouveau_copy_buffer(&nv50
->base
,
209 nv04_resource(dst
), dstx
,
210 nv04_resource(src
), src_box
->x
, src_box
->width
);
214 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
215 assert((src
->nr_samples
| 1) == (dst
->nr_samples
| 1));
217 m2mf
= (src
->format
== dst
->format
) ||
218 (util_format_get_blocksizebits(src
->format
) ==
219 util_format_get_blocksizebits(dst
->format
));
221 nv04_resource(dst
)->status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
224 struct nv50_miptree
*src_mt
= nv50_miptree(src
);
225 struct nv50_miptree
*dst_mt
= nv50_miptree(dst
);
226 struct nv50_m2mf_rect drect
, srect
;
228 unsigned nx
= util_format_get_nblocksx(src
->format
, src_box
->width
)
230 unsigned ny
= util_format_get_nblocksy(src
->format
, src_box
->height
)
233 nv50_m2mf_rect_setup(&drect
, dst
, dst_level
, dstx
, dsty
, dstz
);
234 nv50_m2mf_rect_setup(&srect
, src
, src_level
,
235 src_box
->x
, src_box
->y
, src_box
->z
);
237 for (i
= 0; i
< src_box
->depth
; ++i
) {
238 nv50_m2mf_transfer_rect(nv50
, &drect
, &srect
, nx
, ny
);
240 if (dst_mt
->layout_3d
)
243 drect
.base
+= dst_mt
->layer_stride
;
245 if (src_mt
->layout_3d
)
248 srect
.base
+= src_mt
->layer_stride
;
253 assert((src
->format
== dst
->format
) ||
254 (nv50_2d_src_format_faithful(src
->format
) &&
255 nv50_2d_dst_format_faithful(dst
->format
)));
257 BCTX_REFN(nv50
->bufctx
, 2D
, nv04_resource(src
), RD
);
258 BCTX_REFN(nv50
->bufctx
, 2D
, nv04_resource(dst
), WR
);
259 nouveau_pushbuf_bufctx(nv50
->base
.pushbuf
, nv50
->bufctx
);
260 nouveau_pushbuf_validate(nv50
->base
.pushbuf
);
262 for (; dst_layer
< dstz
+ src_box
->depth
; ++dst_layer
, ++src_layer
) {
263 ret
= nv50_2d_texture_do_copy(nv50
->base
.pushbuf
,
264 nv50_miptree(dst
), dst_level
,
265 dstx
, dsty
, dst_layer
,
266 nv50_miptree(src
), src_level
,
267 src_box
->x
, src_box
->y
, src_layer
,
268 src_box
->width
, src_box
->height
);
272 nouveau_bufctx_reset(nv50
->bufctx
, NV50_BIND_2D
);
276 nv50_clear_render_target(struct pipe_context
*pipe
,
277 struct pipe_surface
*dst
,
278 const union pipe_color_union
*color
,
279 unsigned dstx
, unsigned dsty
,
280 unsigned width
, unsigned height
)
282 struct nv50_context
*nv50
= nv50_context(pipe
);
283 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
284 struct nv50_miptree
*mt
= nv50_miptree(dst
->texture
);
285 struct nv50_surface
*sf
= nv50_surface(dst
);
286 struct nouveau_bo
*bo
= mt
->base
.bo
;
289 assert(dst
->texture
->target
!= PIPE_BUFFER
);
291 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
292 PUSH_DATAf(push
, color
->f
[0]);
293 PUSH_DATAf(push
, color
->f
[1]);
294 PUSH_DATAf(push
, color
->f
[2]);
295 PUSH_DATAf(push
, color
->f
[3]);
297 if (nouveau_pushbuf_space(push
, 32 + sf
->depth
, 1, 0))
300 PUSH_REFN(push
, bo
, mt
->base
.domain
| NOUVEAU_BO_WR
);
302 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
303 PUSH_DATA (push
, ( width
<< 16) | dstx
);
304 PUSH_DATA (push
, (height
<< 16) | dsty
);
305 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
306 PUSH_DATA (push
, 8192 << 16);
307 PUSH_DATA (push
, 8192 << 16);
308 nv50
->scissors_dirty
|= 1;
310 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
312 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
313 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
314 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
315 PUSH_DATA (push
, nv50_format_table
[dst
->format
].rt
);
316 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
317 PUSH_DATA (push
, mt
->layer_stride
>> 2);
318 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(0)), 2);
319 if (nouveau_bo_memtype(bo
))
320 PUSH_DATA(push
, sf
->width
);
322 PUSH_DATA(push
, NV50_3D_RT_HORIZ_LINEAR
| mt
->level
[0].pitch
);
323 PUSH_DATA (push
, sf
->height
);
324 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
326 PUSH_DATA(push
, NV50_3D_RT_ARRAY_MODE_MODE_3D
| 512);
328 PUSH_DATA(push
, 512);
330 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
331 PUSH_DATA (push
, mt
->ms_mode
);
333 if (!nouveau_bo_memtype(bo
)) {
334 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
338 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
340 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
341 PUSH_DATA (push
, (width
<< 16) | dstx
);
342 PUSH_DATA (push
, (height
<< 16) | dsty
);
344 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
345 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
347 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), sf
->depth
);
348 for (z
= 0; z
< sf
->depth
; ++z
) {
349 PUSH_DATA (push
, 0x3c |
350 (z
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
353 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
354 PUSH_DATA (push
, nv50
->cond_condmode
);
356 nv50
->dirty
|= NV50_NEW_FRAMEBUFFER
| NV50_NEW_SCISSOR
;
360 nv50_clear_depth_stencil(struct pipe_context
*pipe
,
361 struct pipe_surface
*dst
,
362 unsigned clear_flags
,
365 unsigned dstx
, unsigned dsty
,
366 unsigned width
, unsigned height
)
368 struct nv50_context
*nv50
= nv50_context(pipe
);
369 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
370 struct nv50_miptree
*mt
= nv50_miptree(dst
->texture
);
371 struct nv50_surface
*sf
= nv50_surface(dst
);
372 struct nouveau_bo
*bo
= mt
->base
.bo
;
376 assert(dst
->texture
->target
!= PIPE_BUFFER
);
377 assert(nouveau_bo_memtype(bo
)); /* ZETA cannot be linear */
379 if (clear_flags
& PIPE_CLEAR_DEPTH
) {
380 BEGIN_NV04(push
, NV50_3D(CLEAR_DEPTH
), 1);
381 PUSH_DATAf(push
, depth
);
382 mode
|= NV50_3D_CLEAR_BUFFERS_Z
;
385 if (clear_flags
& PIPE_CLEAR_STENCIL
) {
386 BEGIN_NV04(push
, NV50_3D(CLEAR_STENCIL
), 1);
387 PUSH_DATA (push
, stencil
& 0xff);
388 mode
|= NV50_3D_CLEAR_BUFFERS_S
;
391 if (nouveau_pushbuf_space(push
, 32 + sf
->depth
, 1, 0))
394 PUSH_REFN(push
, bo
, mt
->base
.domain
| NOUVEAU_BO_WR
);
396 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
397 PUSH_DATA (push
, ( width
<< 16) | dstx
);
398 PUSH_DATA (push
, (height
<< 16) | dsty
);
399 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
400 PUSH_DATA (push
, 8192 << 16);
401 PUSH_DATA (push
, 8192 << 16);
402 nv50
->scissors_dirty
|= 1;
404 BEGIN_NV04(push
, NV50_3D(ZETA_ADDRESS_HIGH
), 5);
405 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
406 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
407 PUSH_DATA (push
, nv50_format_table
[dst
->format
].rt
);
408 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
409 PUSH_DATA (push
, mt
->layer_stride
>> 2);
410 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
412 BEGIN_NV04(push
, NV50_3D(ZETA_HORIZ
), 3);
413 PUSH_DATA (push
, sf
->width
);
414 PUSH_DATA (push
, sf
->height
);
415 PUSH_DATA (push
, (1 << 16) | 1);
417 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
418 PUSH_DATA (push
, 512);
420 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
421 PUSH_DATA (push
, mt
->ms_mode
);
423 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
424 PUSH_DATA (push
, (width
<< 16) | dstx
);
425 PUSH_DATA (push
, (height
<< 16) | dsty
);
427 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
428 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
430 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), sf
->depth
);
431 for (z
= 0; z
< sf
->depth
; ++z
) {
432 PUSH_DATA (push
, mode
|
433 (z
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
436 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
437 PUSH_DATA (push
, nv50
->cond_condmode
);
439 nv50
->dirty
|= NV50_NEW_FRAMEBUFFER
| NV50_NEW_SCISSOR
;
443 nv50_clear_texture(struct pipe_context
*pipe
,
444 struct pipe_resource
*res
,
446 const struct pipe_box
*box
,
449 struct pipe_surface tmpl
= {{0}}, *sf
;
451 tmpl
.format
= res
->format
;
452 tmpl
.u
.tex
.first_layer
= box
->z
;
453 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
454 tmpl
.u
.tex
.level
= level
;
455 sf
= pipe
->create_surface(pipe
, res
, &tmpl
);
459 if (util_format_is_depth_or_stencil(res
->format
)) {
463 const struct util_format_description
*desc
=
464 util_format_description(res
->format
);
466 if (util_format_has_depth(desc
)) {
467 clear
|= PIPE_CLEAR_DEPTH
;
468 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
470 if (util_format_has_stencil(desc
)) {
471 clear
|= PIPE_CLEAR_STENCIL
;
472 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
474 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
475 box
->x
, box
->y
, box
->width
, box
->height
);
477 union pipe_color_union color
;
479 switch (util_format_get_blocksizebits(res
->format
)) {
481 sf
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
482 memcpy(&color
.ui
, data
, 128 / 8);
485 sf
->format
= PIPE_FORMAT_R32G32_UINT
;
486 memcpy(&color
.ui
, data
, 64 / 8);
487 memset(&color
.ui
[2], 0, 64 / 8);
490 sf
->format
= PIPE_FORMAT_R32_UINT
;
491 memcpy(&color
.ui
, data
, 32 / 8);
492 memset(&color
.ui
[1], 0, 96 / 8);
495 sf
->format
= PIPE_FORMAT_R16_UINT
;
496 color
.ui
[0] = util_cpu_to_le32(
497 util_le16_to_cpu(*(unsigned short *)data
));
498 memset(&color
.ui
[1], 0, 96 / 8);
501 sf
->format
= PIPE_FORMAT_R8_UINT
;
502 color
.ui
[0] = util_cpu_to_le32(*(unsigned char *)data
);
503 memset(&color
.ui
[1], 0, 96 / 8);
506 assert(!"Unknown texel element size");
510 pipe
->clear_render_target(pipe
, sf
, &color
,
511 box
->x
, box
->y
, box
->width
, box
->height
);
513 pipe
->surface_destroy(pipe
, sf
);
517 nv50_clear(struct pipe_context
*pipe
, unsigned buffers
,
518 const union pipe_color_union
*color
,
519 double depth
, unsigned stencil
)
521 struct nv50_context
*nv50
= nv50_context(pipe
);
522 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
523 struct pipe_framebuffer_state
*fb
= &nv50
->framebuffer
;
527 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
528 if (!nv50_state_validate(nv50
, NV50_NEW_FRAMEBUFFER
))
531 /* We have to clear ALL of the layers, not up to the min number of layers
532 * of any attachment. */
533 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
534 PUSH_DATA (push
, (nv50
->rt_array_mode
& NV50_3D_RT_ARRAY_MODE_MODE_3D
) | 512);
536 if (buffers
& PIPE_CLEAR_COLOR
&& fb
->nr_cbufs
) {
537 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
538 PUSH_DATAf(push
, color
->f
[0]);
539 PUSH_DATAf(push
, color
->f
[1]);
540 PUSH_DATAf(push
, color
->f
[2]);
541 PUSH_DATAf(push
, color
->f
[3]);
542 if (buffers
& PIPE_CLEAR_COLOR0
)
544 NV50_3D_CLEAR_BUFFERS_R
| NV50_3D_CLEAR_BUFFERS_G
|
545 NV50_3D_CLEAR_BUFFERS_B
| NV50_3D_CLEAR_BUFFERS_A
;
548 if (buffers
& PIPE_CLEAR_DEPTH
) {
549 BEGIN_NV04(push
, NV50_3D(CLEAR_DEPTH
), 1);
550 PUSH_DATA (push
, fui(depth
));
551 mode
|= NV50_3D_CLEAR_BUFFERS_Z
;
554 if (buffers
& PIPE_CLEAR_STENCIL
) {
555 BEGIN_NV04(push
, NV50_3D(CLEAR_STENCIL
), 1);
556 PUSH_DATA (push
, stencil
& 0xff);
557 mode
|= NV50_3D_CLEAR_BUFFERS_S
;
561 int zs_layers
= 0, color0_layers
= 0;
562 if (fb
->cbufs
[0] && (mode
& 0x3c))
563 color0_layers
= nv50_surface(fb
->cbufs
[0])->depth
;
564 if (fb
->zsbuf
&& (mode
& ~0x3c))
565 zs_layers
= nv50_surface(fb
->zsbuf
)->depth
;
567 for (j
= 0; j
< MIN2(zs_layers
, color0_layers
); j
++) {
568 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
569 PUSH_DATA(push
, mode
| (j
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
571 for (k
= j
; k
< zs_layers
; k
++) {
572 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
573 PUSH_DATA(push
, (mode
& ~0x3c) | (k
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
575 for (k
= j
; k
< color0_layers
; k
++) {
576 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
577 PUSH_DATA(push
, (mode
& 0x3c) | (k
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
581 for (i
= 1; i
< fb
->nr_cbufs
; i
++) {
582 struct pipe_surface
*sf
= fb
->cbufs
[i
];
583 if (!sf
|| !(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
585 for (j
= 0; j
< nv50_surface(sf
)->depth
; j
++) {
586 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
587 PUSH_DATA (push
, (i
<< 6) | 0x3c |
588 (j
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
592 /* restore the array mode */
593 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
594 PUSH_DATA (push
, nv50
->rt_array_mode
);
598 nv50_clear_buffer_push(struct pipe_context
*pipe
,
599 struct pipe_resource
*res
,
600 unsigned offset
, unsigned size
,
601 const void *data
, int data_size
)
603 struct nv50_context
*nv50
= nv50_context(pipe
);
604 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
605 struct nv04_resource
*buf
= nv04_resource(res
);
606 unsigned count
= (size
+ 3) / 4;
607 unsigned xcoord
= offset
& 0xff;
610 if (data_size
== 1) {
611 tmp
= *(unsigned char *)data
;
612 tmp
= (tmp
<< 24) | (tmp
<< 16) | (tmp
<< 8) | tmp
;
615 } else if (data_size
== 2) {
616 tmp
= *(unsigned short *)data
;
617 tmp
= (tmp
<< 16) | tmp
;
622 unsigned data_words
= data_size
/ 4;
624 nouveau_bufctx_refn(nv50
->bufctx
, 0, buf
->bo
, buf
->domain
| NOUVEAU_BO_WR
);
625 nouveau_pushbuf_bufctx(push
, nv50
->bufctx
);
626 nouveau_pushbuf_validate(push
);
630 BEGIN_NV04(push
, NV50_2D(DST_FORMAT
), 2);
631 PUSH_DATA (push
, G80_SURFACE_FORMAT_R8_UNORM
);
633 BEGIN_NV04(push
, NV50_2D(DST_PITCH
), 5);
634 PUSH_DATA (push
, 262144);
635 PUSH_DATA (push
, 65536);
637 PUSH_DATAh(push
, buf
->address
+ offset
);
638 PUSH_DATA (push
, buf
->address
+ offset
);
639 BEGIN_NV04(push
, NV50_2D(SIFC_BITMAP_ENABLE
), 2);
641 PUSH_DATA (push
, G80_SURFACE_FORMAT_R8_UNORM
);
642 BEGIN_NV04(push
, NV50_2D(SIFC_WIDTH
), 10);
643 PUSH_DATA (push
, size
);
650 PUSH_DATA (push
, xcoord
);
655 unsigned nr_data
= MIN2(count
, NV04_PFIFO_MAX_PACKET_LEN
) / data_words
;
656 unsigned nr
= nr_data
* data_words
;
658 BEGIN_NI04(push
, NV50_2D(SIFC_DATA
), nr
);
659 for (i
= 0; i
< nr_data
; i
++)
660 PUSH_DATAp(push
, data
, data_words
);
666 nouveau_fence_ref(nv50
->screen
->base
.fence
.current
, &buf
->fence
);
667 nouveau_fence_ref(nv50
->screen
->base
.fence
.current
, &buf
->fence_wr
);
670 nouveau_bufctx_reset(nv50
->bufctx
, 0);
674 nv50_clear_buffer(struct pipe_context
*pipe
,
675 struct pipe_resource
*res
,
676 unsigned offset
, unsigned size
,
677 const void *data
, int data_size
)
679 struct nv50_context
*nv50
= nv50_context(pipe
);
680 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
681 struct nv04_resource
*buf
= (struct nv04_resource
*)res
;
682 union pipe_color_union color
;
683 enum pipe_format dst_fmt
;
684 unsigned width
, height
, elements
;
686 assert(res
->target
== PIPE_BUFFER
);
687 assert(nouveau_bo_memtype(buf
->bo
) == 0);
691 dst_fmt
= PIPE_FORMAT_R32G32B32A32_UINT
;
692 memcpy(&color
.ui
, data
, 16);
695 dst_fmt
= PIPE_FORMAT_R32G32_UINT
;
696 memcpy(&color
.ui
, data
, 8);
697 memset(&color
.ui
[2], 0, 8);
700 dst_fmt
= PIPE_FORMAT_R32_UINT
;
701 memcpy(&color
.ui
, data
, 4);
702 memset(&color
.ui
[1], 0, 12);
705 dst_fmt
= PIPE_FORMAT_R16_UINT
;
706 color
.ui
[0] = util_cpu_to_le32(
707 util_le16_to_cpu(*(unsigned short *)data
));
708 memset(&color
.ui
[1], 0, 12);
711 dst_fmt
= PIPE_FORMAT_R8_UINT
;
712 color
.ui
[0] = util_cpu_to_le32(*(unsigned char *)data
);
713 memset(&color
.ui
[1], 0, 12);
716 assert(!"Unsupported element size");
720 assert(size
% data_size
== 0);
723 unsigned fixup_size
= MIN2(size
, align(offset
, 0x100) - offset
);
724 assert(fixup_size
% data_size
== 0);
725 nv50_clear_buffer_push(pipe
, res
, offset
, fixup_size
, data
, data_size
);
726 offset
+= fixup_size
;
732 elements
= size
/ data_size
;
733 height
= (elements
+ 8191) / 8192;
734 width
= elements
/ height
;
739 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
740 PUSH_DATAf(push
, color
.f
[0]);
741 PUSH_DATAf(push
, color
.f
[1]);
742 PUSH_DATAf(push
, color
.f
[2]);
743 PUSH_DATAf(push
, color
.f
[3]);
745 if (nouveau_pushbuf_space(push
, 32, 1, 0))
748 PUSH_REFN(push
, buf
->bo
, buf
->domain
| NOUVEAU_BO_WR
);
750 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
751 PUSH_DATA (push
, width
<< 16);
752 PUSH_DATA (push
, height
<< 16);
753 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
754 PUSH_DATA (push
, 8192 << 16);
755 PUSH_DATA (push
, 8192 << 16);
756 nv50
->scissors_dirty
|= 1;
758 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
760 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
761 PUSH_DATAh(push
, buf
->address
+ offset
);
762 PUSH_DATA (push
, buf
->address
+ offset
);
763 PUSH_DATA (push
, nv50_format_table
[dst_fmt
].rt
);
766 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(0)), 2);
767 PUSH_DATA (push
, NV50_3D_RT_HORIZ_LINEAR
| align(width
* data_size
, 0x100));
768 PUSH_DATA (push
, height
);
769 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
771 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
774 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
776 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
777 PUSH_DATA (push
, (width
<< 16));
778 PUSH_DATA (push
, (height
<< 16));
780 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
781 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
783 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
784 PUSH_DATA (push
, 0x3c);
786 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
787 PUSH_DATA (push
, nv50
->cond_condmode
);
790 nouveau_fence_ref(nv50
->screen
->base
.fence
.current
, &buf
->fence
);
791 nouveau_fence_ref(nv50
->screen
->base
.fence
.current
, &buf
->fence_wr
);
794 if (width
* height
!= elements
) {
795 offset
+= width
* height
* data_size
;
796 width
= elements
- width
* height
;
797 nv50_clear_buffer_push(pipe
, res
, offset
, width
* data_size
,
801 nv50
->dirty
|= NV50_NEW_FRAMEBUFFER
| NV50_NEW_SCISSOR
;
804 /* =============================== BLIT CODE ===================================
809 struct nv50_program
*fp
[NV50_BLIT_MAX_TEXTURE_TYPES
][NV50_BLIT_MODES
];
810 struct nv50_program vp
;
812 struct nv50_tsc_entry sampler
[2]; /* nearest, bilinear */
819 struct nv50_context
*nv50
;
820 struct nv50_program
*fp
;
824 uint8_t render_condition_enable
;
825 enum pipe_texture_target target
;
827 struct pipe_framebuffer_state fb
;
828 struct nv50_rasterizer_stateobj
*rast
;
829 struct nv50_program
*vp
;
830 struct nv50_program
*gp
;
831 struct nv50_program
*fp
;
832 unsigned num_textures
[3];
833 unsigned num_samplers
[3];
834 struct pipe_sampler_view
*texture
[2];
835 struct nv50_tsc_entry
*sampler
[2];
836 unsigned min_samples
;
839 struct nv50_rasterizer_stateobj rast
;
843 nv50_blitter_make_vp(struct nv50_blitter
*blit
)
845 static const uint32_t code
[] =
847 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
848 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
849 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
850 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
851 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
854 blit
->vp
.type
= PIPE_SHADER_VERTEX
;
855 blit
->vp
.translated
= true;
856 blit
->vp
.code
= (uint32_t *)code
; /* const_cast */
857 blit
->vp
.code_size
= sizeof(code
);
858 blit
->vp
.max_gpr
= 4;
859 blit
->vp
.max_out
= 5;
861 blit
->vp
.out
[0].mask
= 0x3;
862 blit
->vp
.out
[0].sn
= TGSI_SEMANTIC_POSITION
;
863 blit
->vp
.out
[1].hw
= 2;
864 blit
->vp
.out
[1].mask
= 0x7;
865 blit
->vp
.out
[1].sn
= TGSI_SEMANTIC_GENERIC
;
866 blit
->vp
.out
[1].si
= 0;
867 blit
->vp
.vp
.attrs
[0] = 0x73;
868 blit
->vp
.vp
.psiz
= 0x40;
869 blit
->vp
.vp
.edgeflag
= 0x40;
873 nv50_blitter_make_fp(struct pipe_context
*pipe
,
875 enum pipe_texture_target ptarg
)
877 struct ureg_program
*ureg
;
880 struct ureg_dst data
;
882 const unsigned target
= nv50_blit_get_tgsi_texture_target(ptarg
);
884 bool tex_rgbaz
= false;
886 bool cvt_un8
= false;
888 if (mode
!= NV50_BLIT_MODE_PASS
&&
889 mode
!= NV50_BLIT_MODE_Z24X8
&&
890 mode
!= NV50_BLIT_MODE_X8Z24
)
893 if (mode
!= NV50_BLIT_MODE_X24S8
&&
894 mode
!= NV50_BLIT_MODE_S8X24
&&
895 mode
!= NV50_BLIT_MODE_XS
)
898 if (mode
!= NV50_BLIT_MODE_PASS
&&
899 mode
!= NV50_BLIT_MODE_ZS
&&
900 mode
!= NV50_BLIT_MODE_XS
)
903 ureg
= ureg_create(TGSI_PROCESSOR_FRAGMENT
);
907 out
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_COLOR
, 0);
908 tc
= ureg_DECL_fs_input(
909 ureg
, TGSI_SEMANTIC_GENERIC
, 0, TGSI_INTERPOLATE_LINEAR
);
911 if (ptarg
== PIPE_TEXTURE_1D_ARRAY
) {
912 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
913 tc
= ureg_swizzle(tc
, TGSI_SWIZZLE_X
, TGSI_SWIZZLE_Z
,
914 TGSI_SWIZZLE_Z
, TGSI_SWIZZLE_Z
);
917 data
= ureg_DECL_temporary(ureg
);
920 ureg_TEX(ureg
, ureg_writemask(data
, TGSI_WRITEMASK_X
),
921 target
, tc
, ureg_DECL_sampler(ureg
, 1));
922 ureg_MOV(ureg
, ureg_writemask(data
, TGSI_WRITEMASK_Y
),
923 ureg_scalar(ureg_src(data
), TGSI_SWIZZLE_X
));
926 const unsigned mask
= (mode
== NV50_BLIT_MODE_PASS
) ?
927 TGSI_WRITEMASK_XYZW
: TGSI_WRITEMASK_X
;
928 ureg_TEX(ureg
, ureg_writemask(data
, mask
),
929 target
, tc
, ureg_DECL_sampler(ureg
, 0));
933 struct ureg_src mask
;
934 struct ureg_src scale
;
935 struct ureg_dst outz
;
936 struct ureg_dst outs
;
937 struct ureg_dst zdst3
= ureg_writemask(data
, TGSI_WRITEMASK_XYZ
);
938 struct ureg_dst zdst
= ureg_writemask(data
, TGSI_WRITEMASK_X
);
939 struct ureg_dst sdst
= ureg_writemask(data
, TGSI_WRITEMASK_Y
);
940 struct ureg_src zsrc3
= ureg_src(data
);
941 struct ureg_src zsrc
= ureg_scalar(zsrc3
, TGSI_SWIZZLE_X
);
942 struct ureg_src ssrc
= ureg_scalar(zsrc3
, TGSI_SWIZZLE_Y
);
943 struct ureg_src zshuf
;
945 mask
= ureg_imm3u(ureg
, 0x0000ff, 0x00ff00, 0xff0000);
946 scale
= ureg_imm4f(ureg
,
947 1.0f
/ 0x0000ff, 1.0f
/ 0x00ff00, 1.0f
/ 0xff0000,
950 if (mode
== NV50_BLIT_MODE_Z24S8
||
951 mode
== NV50_BLIT_MODE_X24S8
||
952 mode
== NV50_BLIT_MODE_Z24X8
) {
953 outz
= ureg_writemask(out
, TGSI_WRITEMASK_XYZ
);
954 outs
= ureg_writemask(out
, TGSI_WRITEMASK_W
);
955 zshuf
= ureg_src(data
);
957 outz
= ureg_writemask(out
, TGSI_WRITEMASK_YZW
);
958 outs
= ureg_writemask(out
, TGSI_WRITEMASK_X
);
959 zshuf
= ureg_swizzle(zsrc3
, TGSI_SWIZZLE_W
,
960 TGSI_SWIZZLE_X
, TGSI_SWIZZLE_Y
, TGSI_SWIZZLE_Z
);
964 ureg_I2F(ureg
, sdst
, ssrc
);
965 ureg_MUL(ureg
, outs
, ssrc
, ureg_scalar(scale
, TGSI_SWIZZLE_X
));
969 ureg_MUL(ureg
, zdst
, zsrc
, ureg_scalar(scale
, TGSI_SWIZZLE_W
));
970 ureg_F2I(ureg
, zdst
, zsrc
);
971 ureg_AND(ureg
, zdst3
, zsrc
, mask
);
972 ureg_I2F(ureg
, zdst3
, zsrc3
);
973 ureg_MUL(ureg
, zdst3
, zsrc3
, scale
);
974 ureg_MOV(ureg
, outz
, zshuf
);
977 unsigned mask
= TGSI_WRITEMASK_XYZW
;
979 if (mode
!= NV50_BLIT_MODE_PASS
) {
980 mask
&= ~TGSI_WRITEMASK_ZW
;
982 mask
= TGSI_WRITEMASK_X
;
984 mask
= TGSI_WRITEMASK_Y
;
986 ureg_MOV(ureg
, ureg_writemask(out
, mask
), ureg_src(data
));
990 return ureg_create_shader_and_destroy(ureg
, pipe
);
994 nv50_blitter_make_sampler(struct nv50_blitter
*blit
)
996 /* clamp to edge, min/max lod = 0, nearest filtering */
998 blit
->sampler
[0].id
= -1;
1000 blit
->sampler
[0].tsc
[0] = G80_TSC_0_SRGB_CONVERSION
|
1001 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_U__SHIFT
) |
1002 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_V__SHIFT
) |
1003 (G80_TSC_WRAP_CLAMP_TO_EDGE
<< G80_TSC_0_ADDRESS_P__SHIFT
);
1004 blit
->sampler
[0].tsc
[1] =
1005 G80_TSC_1_MAG_FILTER_NEAREST
|
1006 G80_TSC_1_MIN_FILTER_NEAREST
|
1007 G80_TSC_1_MIP_FILTER_NONE
;
1009 /* clamp to edge, min/max lod = 0, bilinear filtering */
1011 blit
->sampler
[1].id
= -1;
1013 blit
->sampler
[1].tsc
[0] = blit
->sampler
[0].tsc
[0];
1014 blit
->sampler
[1].tsc
[1] =
1015 G80_TSC_1_MAG_FILTER_LINEAR
|
1016 G80_TSC_1_MIN_FILTER_LINEAR
|
1017 G80_TSC_1_MIP_FILTER_NONE
;
1021 nv50_blit_select_mode(const struct pipe_blit_info
*info
)
1023 const unsigned mask
= info
->mask
;
1025 switch (info
->dst
.resource
->format
) {
1026 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1027 case PIPE_FORMAT_Z24X8_UNORM
:
1028 case PIPE_FORMAT_X24S8_UINT
:
1029 switch (mask
& PIPE_MASK_ZS
) {
1030 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_Z24S8
;
1031 case PIPE_MASK_Z
: return NV50_BLIT_MODE_Z24X8
;
1033 return NV50_BLIT_MODE_X24S8
;
1035 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1036 case PIPE_FORMAT_X8Z24_UNORM
:
1037 case PIPE_FORMAT_S8X24_UINT
:
1038 switch (mask
& PIPE_MASK_ZS
) {
1039 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_S8Z24
;
1040 case PIPE_MASK_Z
: return NV50_BLIT_MODE_X8Z24
;
1042 return NV50_BLIT_MODE_S8X24
;
1044 case PIPE_FORMAT_Z32_FLOAT
:
1045 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1046 case PIPE_FORMAT_X32_S8X24_UINT
:
1047 switch (mask
& PIPE_MASK_ZS
) {
1048 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_ZS
;
1049 case PIPE_MASK_Z
: return NV50_BLIT_MODE_PASS
;
1051 return NV50_BLIT_MODE_XS
;
1054 return NV50_BLIT_MODE_PASS
;
1059 nv50_blit_select_fp(struct nv50_blitctx
*ctx
, const struct pipe_blit_info
*info
)
1061 struct nv50_blitter
*blitter
= ctx
->nv50
->screen
->blitter
;
1063 const enum pipe_texture_target ptarg
=
1064 nv50_blit_reinterpret_pipe_texture_target(info
->src
.resource
->target
);
1066 const unsigned targ
= nv50_blit_texture_type(ptarg
);
1067 const unsigned mode
= ctx
->mode
;
1069 if (!blitter
->fp
[targ
][mode
]) {
1070 pipe_mutex_lock(blitter
->mutex
);
1071 if (!blitter
->fp
[targ
][mode
])
1072 blitter
->fp
[targ
][mode
] =
1073 nv50_blitter_make_fp(&ctx
->nv50
->base
.pipe
, mode
, ptarg
);
1074 pipe_mutex_unlock(blitter
->mutex
);
1076 ctx
->fp
= blitter
->fp
[targ
][mode
];
1080 nv50_blit_set_dst(struct nv50_blitctx
*ctx
,
1081 struct pipe_resource
*res
, unsigned level
, unsigned layer
,
1082 enum pipe_format format
)
1084 struct nv50_context
*nv50
= ctx
->nv50
;
1085 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
1086 struct pipe_surface templ
;
1088 if (util_format_is_depth_or_stencil(format
))
1089 templ
.format
= nv50_blit_zeta_to_colour_format(format
);
1091 templ
.format
= format
;
1093 templ
.u
.tex
.level
= level
;
1094 templ
.u
.tex
.first_layer
= templ
.u
.tex
.last_layer
= layer
;
1097 templ
.u
.tex
.first_layer
= 0;
1098 templ
.u
.tex
.last_layer
=
1099 (res
->target
== PIPE_TEXTURE_3D
? res
->depth0
: res
->array_size
) - 1;
1102 nv50
->framebuffer
.cbufs
[0] = nv50_miptree_surface_new(pipe
, res
, &templ
);
1103 nv50
->framebuffer
.nr_cbufs
= 1;
1104 nv50
->framebuffer
.zsbuf
= NULL
;
1105 nv50
->framebuffer
.width
= nv50
->framebuffer
.cbufs
[0]->width
;
1106 nv50
->framebuffer
.height
= nv50
->framebuffer
.cbufs
[0]->height
;
1110 nv50_blit_set_src(struct nv50_blitctx
*blit
,
1111 struct pipe_resource
*res
, unsigned level
, unsigned layer
,
1112 enum pipe_format format
, const uint8_t filter
)
1114 struct nv50_context
*nv50
= blit
->nv50
;
1115 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
1116 struct pipe_sampler_view templ
;
1118 enum pipe_texture_target target
;
1120 target
= nv50_blit_reinterpret_pipe_texture_target(res
->target
);
1122 templ
.format
= format
;
1123 templ
.u
.tex
.first_level
= templ
.u
.tex
.last_level
= level
;
1124 templ
.u
.tex
.first_layer
= templ
.u
.tex
.last_layer
= layer
;
1125 templ
.swizzle_r
= PIPE_SWIZZLE_RED
;
1126 templ
.swizzle_g
= PIPE_SWIZZLE_GREEN
;
1127 templ
.swizzle_b
= PIPE_SWIZZLE_BLUE
;
1128 templ
.swizzle_a
= PIPE_SWIZZLE_ALPHA
;
1131 templ
.u
.tex
.first_layer
= 0;
1132 templ
.u
.tex
.last_layer
=
1133 (res
->target
== PIPE_TEXTURE_3D
? res
->depth0
: res
->array_size
) - 1;
1136 flags
= res
->last_level
? 0 : NV50_TEXVIEW_SCALED_COORDS
;
1137 flags
|= NV50_TEXVIEW_ACCESS_RESOLVE
;
1138 if (filter
&& res
->nr_samples
== 8)
1139 flags
|= NV50_TEXVIEW_FILTER_MSAA8
;
1141 nv50
->textures
[2][0] = nv50_create_texture_view(
1142 pipe
, res
, &templ
, flags
, target
);
1143 nv50
->textures
[2][1] = NULL
;
1145 nv50
->num_textures
[0] = nv50
->num_textures
[1] = 0;
1146 nv50
->num_textures
[2] = 1;
1148 templ
.format
= nv50_zs_to_s_format(format
);
1149 if (templ
.format
!= res
->format
) {
1150 nv50
->textures
[2][1] = nv50_create_texture_view(
1151 pipe
, res
, &templ
, flags
, target
);
1152 nv50
->num_textures
[2] = 2;
1157 nv50_blitctx_prepare_state(struct nv50_blitctx
*blit
)
1159 struct nouveau_pushbuf
*push
= blit
->nv50
->base
.pushbuf
;
1161 if (blit
->nv50
->cond_query
&& !blit
->render_condition_enable
) {
1162 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
1163 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
1167 BEGIN_NV04(push
, NV50_3D(COLOR_MASK(0)), 1);
1168 PUSH_DATA (push
, blit
->color_mask
);
1169 BEGIN_NV04(push
, NV50_3D(BLEND_ENABLE(0)), 1);
1170 PUSH_DATA (push
, 0);
1171 BEGIN_NV04(push
, NV50_3D(LOGIC_OP_ENABLE
), 1);
1172 PUSH_DATA (push
, 0);
1174 /* rasterizer state */
1175 #ifndef NV50_SCISSORS_CLIPPING
1176 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(0)), 1);
1177 PUSH_DATA (push
, 1);
1179 BEGIN_NV04(push
, NV50_3D(VERTEX_TWO_SIDE_ENABLE
), 1);
1180 PUSH_DATA (push
, 0);
1181 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
1182 PUSH_DATA (push
, 0);
1183 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
1184 PUSH_DATA (push
, 0);
1185 BEGIN_NV04(push
, NV50_3D(MSAA_MASK(0)), 4);
1186 PUSH_DATA (push
, 0xffff);
1187 PUSH_DATA (push
, 0xffff);
1188 PUSH_DATA (push
, 0xffff);
1189 PUSH_DATA (push
, 0xffff);
1190 BEGIN_NV04(push
, NV50_3D(POLYGON_MODE_FRONT
), 3);
1191 PUSH_DATA (push
, NV50_3D_POLYGON_MODE_FRONT_FILL
);
1192 PUSH_DATA (push
, NV50_3D_POLYGON_MODE_BACK_FILL
);
1193 PUSH_DATA (push
, 0);
1194 BEGIN_NV04(push
, NV50_3D(CULL_FACE_ENABLE
), 1);
1195 PUSH_DATA (push
, 0);
1196 BEGIN_NV04(push
, NV50_3D(POLYGON_STIPPLE_ENABLE
), 1);
1197 PUSH_DATA (push
, 0);
1198 BEGIN_NV04(push
, NV50_3D(POLYGON_OFFSET_FILL_ENABLE
), 1);
1199 PUSH_DATA (push
, 0);
1202 BEGIN_NV04(push
, NV50_3D(DEPTH_TEST_ENABLE
), 1);
1203 PUSH_DATA (push
, 0);
1204 BEGIN_NV04(push
, NV50_3D(DEPTH_BOUNDS_EN
), 1);
1205 PUSH_DATA (push
, 0);
1206 BEGIN_NV04(push
, NV50_3D(STENCIL_ENABLE
), 1);
1207 PUSH_DATA (push
, 0);
1208 BEGIN_NV04(push
, NV50_3D(ALPHA_TEST_ENABLE
), 1);
1209 PUSH_DATA (push
, 0);
1213 nv50_blitctx_pre_blit(struct nv50_blitctx
*ctx
)
1215 struct nv50_context
*nv50
= ctx
->nv50
;
1216 struct nv50_blitter
*blitter
= nv50
->screen
->blitter
;
1219 ctx
->saved
.fb
.width
= nv50
->framebuffer
.width
;
1220 ctx
->saved
.fb
.height
= nv50
->framebuffer
.height
;
1221 ctx
->saved
.fb
.nr_cbufs
= nv50
->framebuffer
.nr_cbufs
;
1222 ctx
->saved
.fb
.cbufs
[0] = nv50
->framebuffer
.cbufs
[0];
1223 ctx
->saved
.fb
.zsbuf
= nv50
->framebuffer
.zsbuf
;
1225 ctx
->saved
.rast
= nv50
->rast
;
1227 ctx
->saved
.vp
= nv50
->vertprog
;
1228 ctx
->saved
.gp
= nv50
->gmtyprog
;
1229 ctx
->saved
.fp
= nv50
->fragprog
;
1231 ctx
->saved
.min_samples
= nv50
->min_samples
;
1233 nv50
->rast
= &ctx
->rast
;
1235 nv50
->vertprog
= &blitter
->vp
;
1236 nv50
->gmtyprog
= NULL
;
1237 nv50
->fragprog
= ctx
->fp
;
1239 for (s
= 0; s
< 3; ++s
) {
1240 ctx
->saved
.num_textures
[s
] = nv50
->num_textures
[s
];
1241 ctx
->saved
.num_samplers
[s
] = nv50
->num_samplers
[s
];
1243 ctx
->saved
.texture
[0] = nv50
->textures
[2][0];
1244 ctx
->saved
.texture
[1] = nv50
->textures
[2][1];
1245 ctx
->saved
.sampler
[0] = nv50
->samplers
[2][0];
1246 ctx
->saved
.sampler
[1] = nv50
->samplers
[2][1];
1248 nv50
->samplers
[2][0] = &blitter
->sampler
[ctx
->filter
];
1249 nv50
->samplers
[2][1] = &blitter
->sampler
[ctx
->filter
];
1251 nv50
->num_samplers
[0] = nv50
->num_samplers
[1] = 0;
1252 nv50
->num_samplers
[2] = 2;
1254 nv50
->min_samples
= 1;
1256 ctx
->saved
.dirty
= nv50
->dirty
;
1258 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_FB
);
1259 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_TEXTURES
);
1262 NV50_NEW_FRAMEBUFFER
| NV50_NEW_MIN_SAMPLES
|
1263 NV50_NEW_VERTPROG
| NV50_NEW_FRAGPROG
| NV50_NEW_GMTYPROG
|
1264 NV50_NEW_TEXTURES
| NV50_NEW_SAMPLERS
;
1268 nv50_blitctx_post_blit(struct nv50_blitctx
*blit
)
1270 struct nv50_context
*nv50
= blit
->nv50
;
1273 pipe_surface_reference(&nv50
->framebuffer
.cbufs
[0], NULL
);
1275 nv50
->framebuffer
.width
= blit
->saved
.fb
.width
;
1276 nv50
->framebuffer
.height
= blit
->saved
.fb
.height
;
1277 nv50
->framebuffer
.nr_cbufs
= blit
->saved
.fb
.nr_cbufs
;
1278 nv50
->framebuffer
.cbufs
[0] = blit
->saved
.fb
.cbufs
[0];
1279 nv50
->framebuffer
.zsbuf
= blit
->saved
.fb
.zsbuf
;
1281 nv50
->rast
= blit
->saved
.rast
;
1283 nv50
->vertprog
= blit
->saved
.vp
;
1284 nv50
->gmtyprog
= blit
->saved
.gp
;
1285 nv50
->fragprog
= blit
->saved
.fp
;
1287 nv50
->min_samples
= blit
->saved
.min_samples
;
1289 pipe_sampler_view_reference(&nv50
->textures
[2][0], NULL
);
1290 pipe_sampler_view_reference(&nv50
->textures
[2][1], NULL
);
1292 for (s
= 0; s
< 3; ++s
) {
1293 nv50
->num_textures
[s
] = blit
->saved
.num_textures
[s
];
1294 nv50
->num_samplers
[s
] = blit
->saved
.num_samplers
[s
];
1296 nv50
->textures
[2][0] = blit
->saved
.texture
[0];
1297 nv50
->textures
[2][1] = blit
->saved
.texture
[1];
1298 nv50
->samplers
[2][0] = blit
->saved
.sampler
[0];
1299 nv50
->samplers
[2][1] = blit
->saved
.sampler
[1];
1301 if (nv50
->cond_query
&& !blit
->render_condition_enable
)
1302 nv50
->base
.pipe
.render_condition(&nv50
->base
.pipe
, nv50
->cond_query
,
1303 nv50
->cond_cond
, nv50
->cond_mode
);
1305 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_FB
);
1306 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_TEXTURES
);
1308 nv50
->dirty
= blit
->saved
.dirty
|
1309 (NV50_NEW_FRAMEBUFFER
| NV50_NEW_SCISSOR
| NV50_NEW_SAMPLE_MASK
|
1310 NV50_NEW_RASTERIZER
| NV50_NEW_ZSA
| NV50_NEW_BLEND
|
1311 NV50_NEW_TEXTURES
| NV50_NEW_SAMPLERS
|
1312 NV50_NEW_VERTPROG
| NV50_NEW_GMTYPROG
| NV50_NEW_FRAGPROG
);
1313 nv50
->scissors_dirty
|= 1;
1315 nv50
->base
.pipe
.set_min_samples(&nv50
->base
.pipe
, blit
->saved
.min_samples
);
1320 nv50_blit_3d(struct nv50_context
*nv50
, const struct pipe_blit_info
*info
)
1322 struct nv50_blitctx
*blit
= nv50
->blit
;
1323 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
1324 struct pipe_resource
*src
= info
->src
.resource
;
1325 struct pipe_resource
*dst
= info
->dst
.resource
;
1326 int32_t minx
, maxx
, miny
, maxy
;
1328 float x0
, x1
, y0
, y1
, z
;
1330 float x_range
, y_range
;
1333 blit
->mode
= nv50_blit_select_mode(info
);
1334 blit
->color_mask
= nv50_blit_derive_color_mask(info
);
1335 blit
->filter
= nv50_blit_get_filter(info
);
1336 blit
->render_condition_enable
= info
->render_condition_enable
;
1338 nv50_blit_select_fp(blit
, info
);
1339 nv50_blitctx_pre_blit(blit
);
1341 nv50_blit_set_dst(blit
, dst
, info
->dst
.level
, -1, info
->dst
.format
);
1342 nv50_blit_set_src(blit
, src
, info
->src
.level
, -1, info
->src
.format
,
1345 nv50_blitctx_prepare_state(blit
);
1347 nv50_state_validate(nv50
, ~0);
1349 x_range
= (float)info
->src
.box
.width
/ (float)info
->dst
.box
.width
;
1350 y_range
= (float)info
->src
.box
.height
/ (float)info
->dst
.box
.height
;
1352 tri_x
= 16384 << nv50_miptree(dst
)->ms_x
;
1353 tri_y
= 16384 << nv50_miptree(dst
)->ms_y
;
1355 x0
= (float)info
->src
.box
.x
- x_range
* (float)info
->dst
.box
.x
;
1356 y0
= (float)info
->src
.box
.y
- y_range
* (float)info
->dst
.box
.y
;
1358 x1
= x0
+ tri_x
* x_range
;
1359 y1
= y0
+ tri_y
* y_range
;
1361 x0
*= (float)(1 << nv50_miptree(src
)->ms_x
);
1362 x1
*= (float)(1 << nv50_miptree(src
)->ms_x
);
1363 y0
*= (float)(1 << nv50_miptree(src
)->ms_y
);
1364 y1
*= (float)(1 << nv50_miptree(src
)->ms_y
);
1366 /* XXX: multiply by 6 for cube arrays ? */
1367 dz
= (float)info
->src
.box
.depth
/ (float)info
->dst
.box
.depth
;
1368 z
= (float)info
->src
.box
.z
;
1369 if (nv50_miptree(src
)->layout_3d
)
1372 if (src
->last_level
> 0) {
1373 /* If there are mip maps, GPU always assumes normalized coordinates. */
1374 const unsigned l
= info
->src
.level
;
1375 const float fh
= u_minify(src
->width0
<< nv50_miptree(src
)->ms_x
, l
);
1376 const float fv
= u_minify(src
->height0
<< nv50_miptree(src
)->ms_y
, l
);
1381 if (nv50_miptree(src
)->layout_3d
) {
1382 z
/= u_minify(src
->depth0
, l
);
1383 dz
/= u_minify(src
->depth0
, l
);
1387 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
1388 PUSH_DATA (push
, 0);
1389 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
1390 PUSH_DATA (push
, 0x1);
1392 /* Draw a large triangle in screen coordinates covering the whole
1393 * render target, with scissors defining the destination region.
1394 * The vertex is supplied with non-normalized texture coordinates
1395 * arranged in a way to yield the desired offset and scale.
1398 minx
= info
->dst
.box
.x
;
1399 maxx
= info
->dst
.box
.x
+ info
->dst
.box
.width
;
1400 miny
= info
->dst
.box
.y
;
1401 maxy
= info
->dst
.box
.y
+ info
->dst
.box
.height
;
1402 if (info
->scissor_enable
) {
1403 minx
= MAX2(minx
, info
->scissor
.minx
);
1404 maxx
= MIN2(maxx
, info
->scissor
.maxx
);
1405 miny
= MAX2(miny
, info
->scissor
.miny
);
1406 maxy
= MIN2(maxy
, info
->scissor
.maxy
);
1408 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
1409 PUSH_DATA (push
, (maxx
<< 16) | minx
);
1410 PUSH_DATA (push
, (maxy
<< 16) | miny
);
1412 for (i
= 0; i
< info
->dst
.box
.depth
; ++i
, z
+= dz
) {
1413 if (info
->dst
.box
.z
+ i
) {
1414 BEGIN_NV04(push
, NV50_3D(LAYER
), 1);
1415 PUSH_DATA (push
, info
->dst
.box
.z
+ i
);
1417 PUSH_SPACE(push
, 32);
1418 BEGIN_NV04(push
, NV50_3D(VERTEX_BEGIN_GL
), 1);
1419 PUSH_DATA (push
, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES
);
1420 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1421 PUSH_DATAf(push
, x0
);
1422 PUSH_DATAf(push
, y0
);
1423 PUSH_DATAf(push
, z
);
1424 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1425 PUSH_DATAf(push
, 0.0f
);
1426 PUSH_DATAf(push
, 0.0f
);
1427 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1428 PUSH_DATAf(push
, x1
);
1429 PUSH_DATAf(push
, y0
);
1430 PUSH_DATAf(push
, z
);
1431 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1432 PUSH_DATAf(push
, tri_x
);
1433 PUSH_DATAf(push
, 0.0f
);
1434 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1435 PUSH_DATAf(push
, x0
);
1436 PUSH_DATAf(push
, y1
);
1437 PUSH_DATAf(push
, z
);
1438 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1439 PUSH_DATAf(push
, 0.0f
);
1440 PUSH_DATAf(push
, tri_y
);
1441 BEGIN_NV04(push
, NV50_3D(VERTEX_END_GL
), 1);
1442 PUSH_DATA (push
, 0);
1444 if (info
->dst
.box
.z
+ info
->dst
.box
.depth
- 1) {
1445 BEGIN_NV04(push
, NV50_3D(LAYER
), 1);
1446 PUSH_DATA (push
, 0);
1449 /* re-enable normally constant state */
1451 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
1452 PUSH_DATA (push
, 1);
1454 nv50_blitctx_post_blit(blit
);
1458 nv50_blit_eng2d(struct nv50_context
*nv50
, const struct pipe_blit_info
*info
)
1460 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
1461 struct nv50_miptree
*dst
= nv50_miptree(info
->dst
.resource
);
1462 struct nv50_miptree
*src
= nv50_miptree(info
->src
.resource
);
1463 const int32_t srcx_adj
= info
->src
.box
.width
< 0 ? -1 : 0;
1464 const int32_t srcy_adj
= info
->src
.box
.height
< 0 ? -1 : 0;
1465 const int32_t dz
= info
->dst
.box
.z
;
1466 const int32_t sz
= info
->src
.box
.z
;
1467 uint32_t dstw
, dsth
;
1470 int64_t du_dx
, dv_dy
;
1473 uint32_t mask
= nv50_blit_eng2d_get_mask(info
);
1476 mode
= nv50_blit_get_filter(info
) ?
1477 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR
:
1478 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE
;
1479 mode
|= (src
->base
.base
.nr_samples
> dst
->base
.base
.nr_samples
) ?
1480 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER
: NV50_2D_BLIT_CONTROL_ORIGIN_CENTER
;
1482 du_dx
= ((int64_t)info
->src
.box
.width
<< 32) / info
->dst
.box
.width
;
1483 dv_dy
= ((int64_t)info
->src
.box
.height
<< 32) / info
->dst
.box
.height
;
1485 b
= info
->dst
.format
== info
->src
.format
;
1486 nv50_2d_texture_set(push
, 1, dst
, info
->dst
.level
, dz
, info
->dst
.format
, b
);
1487 nv50_2d_texture_set(push
, 0, src
, info
->src
.level
, sz
, info
->src
.format
, b
);
1489 if (info
->scissor_enable
) {
1490 BEGIN_NV04(push
, NV50_2D(CLIP_X
), 5);
1491 PUSH_DATA (push
, info
->scissor
.minx
<< dst
->ms_x
);
1492 PUSH_DATA (push
, info
->scissor
.miny
<< dst
->ms_y
);
1493 PUSH_DATA (push
, (info
->scissor
.maxx
- info
->scissor
.minx
) << dst
->ms_x
);
1494 PUSH_DATA (push
, (info
->scissor
.maxy
- info
->scissor
.miny
) << dst
->ms_y
);
1495 PUSH_DATA (push
, 1); /* enable */
1498 if (nv50
->cond_query
&& info
->render_condition_enable
) {
1499 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
1500 PUSH_DATA (push
, nv50
->cond_condmode
);
1503 if (mask
!= 0xffffffff) {
1504 BEGIN_NV04(push
, NV50_2D(ROP
), 1);
1505 PUSH_DATA (push
, 0xca); /* DPSDxax */
1506 BEGIN_NV04(push
, NV50_2D(PATTERN_COLOR_FORMAT
), 1);
1507 PUSH_DATA (push
, NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8
);
1508 BEGIN_NV04(push
, NV50_2D(PATTERN_BITMAP_COLOR(0)), 4);
1509 PUSH_DATA (push
, 0x00000000);
1510 PUSH_DATA (push
, mask
);
1511 PUSH_DATA (push
, 0xffffffff);
1512 PUSH_DATA (push
, 0xffffffff);
1513 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
1514 PUSH_DATA (push
, NV50_2D_OPERATION_ROP
);
1516 if (info
->src
.format
!= info
->dst
.format
) {
1517 if (info
->src
.format
== PIPE_FORMAT_R8_UNORM
||
1518 info
->src
.format
== PIPE_FORMAT_R16_UNORM
||
1519 info
->src
.format
== PIPE_FORMAT_R16_FLOAT
||
1520 info
->src
.format
== PIPE_FORMAT_R32_FLOAT
) {
1521 mask
= 0xffff0000; /* also makes condition for OPERATION reset true */
1522 BEGIN_NV04(push
, NV50_2D(BETA4
), 2);
1523 PUSH_DATA (push
, mask
);
1524 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY_PREMULT
);
1528 if (src
->ms_x
> dst
->ms_x
|| src
->ms_y
> dst
->ms_y
) {
1529 /* ms_x is always >= ms_y */
1530 du_dx
<<= src
->ms_x
- dst
->ms_x
;
1531 dv_dy
<<= src
->ms_y
- dst
->ms_y
;
1533 du_dx
>>= dst
->ms_x
- src
->ms_x
;
1534 dv_dy
>>= dst
->ms_y
- src
->ms_y
;
1537 srcx
= (int64_t)(info
->src
.box
.x
+ srcx_adj
) << (src
->ms_x
+ 32);
1538 srcy
= (int64_t)(info
->src
.box
.y
+ srcy_adj
) << (src
->ms_y
+ 32);
1540 if (src
->base
.base
.nr_samples
> dst
->base
.base
.nr_samples
) {
1541 /* center src coorinates for proper MS resolve filtering */
1542 srcx
+= (int64_t)1 << (src
->ms_x
+ 31);
1543 srcy
+= (int64_t)1 << (src
->ms_y
+ 31);
1546 dstx
= info
->dst
.box
.x
<< dst
->ms_x
;
1547 dsty
= info
->dst
.box
.y
<< dst
->ms_y
;
1549 dstw
= info
->dst
.box
.width
<< dst
->ms_x
;
1550 dsth
= info
->dst
.box
.height
<< dst
->ms_y
;
1554 srcx
-= du_dx
* dstx
;
1559 srcy
-= dv_dy
* dsty
;
1563 BEGIN_NV04(push
, NV50_2D(BLIT_CONTROL
), 1);
1564 PUSH_DATA (push
, mode
);
1565 BEGIN_NV04(push
, NV50_2D(BLIT_DST_X
), 4);
1566 PUSH_DATA (push
, dstx
);
1567 PUSH_DATA (push
, dsty
);
1568 PUSH_DATA (push
, dstw
);
1569 PUSH_DATA (push
, dsth
);
1570 BEGIN_NV04(push
, NV50_2D(BLIT_DU_DX_FRACT
), 4);
1571 PUSH_DATA (push
, du_dx
);
1572 PUSH_DATA (push
, du_dx
>> 32);
1573 PUSH_DATA (push
, dv_dy
);
1574 PUSH_DATA (push
, dv_dy
>> 32);
1576 BCTX_REFN(nv50
->bufctx
, 2D
, &dst
->base
, WR
);
1577 BCTX_REFN(nv50
->bufctx
, 2D
, &src
->base
, RD
);
1578 nouveau_pushbuf_bufctx(nv50
->base
.pushbuf
, nv50
->bufctx
);
1579 if (nouveau_pushbuf_validate(nv50
->base
.pushbuf
))
1582 for (i
= 0; i
< info
->dst
.box
.depth
; ++i
) {
1584 /* no scaling in z-direction possible for eng2d blits */
1585 if (dst
->layout_3d
) {
1586 BEGIN_NV04(push
, NV50_2D(DST_LAYER
), 1);
1587 PUSH_DATA (push
, info
->dst
.box
.z
+ i
);
1589 const unsigned z
= info
->dst
.box
.z
+ i
;
1590 const uint64_t address
= dst
->base
.address
+
1591 dst
->level
[info
->dst
.level
].offset
+
1592 z
* dst
->layer_stride
;
1593 BEGIN_NV04(push
, NV50_2D(DST_ADDRESS_HIGH
), 2);
1594 PUSH_DATAh(push
, address
);
1595 PUSH_DATA (push
, address
);
1597 if (src
->layout_3d
) {
1598 /* not possible because of depth tiling */
1601 const unsigned z
= info
->src
.box
.z
+ i
;
1602 const uint64_t address
= src
->base
.address
+
1603 src
->level
[info
->src
.level
].offset
+
1604 z
* src
->layer_stride
;
1605 BEGIN_NV04(push
, NV50_2D(SRC_ADDRESS_HIGH
), 2);
1606 PUSH_DATAh(push
, address
);
1607 PUSH_DATA (push
, address
);
1609 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_Y_INT
), 1); /* trigger */
1610 PUSH_DATA (push
, srcy
>> 32);
1612 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_X_FRACT
), 4);
1613 PUSH_DATA (push
, srcx
);
1614 PUSH_DATA (push
, srcx
>> 32);
1615 PUSH_DATA (push
, srcy
);
1616 PUSH_DATA (push
, srcy
>> 32);
1619 nv50_bufctx_fence(nv50
->bufctx
, false);
1621 nouveau_bufctx_reset(nv50
->bufctx
, NV50_BIND_2D
);
1623 if (info
->scissor_enable
) {
1624 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
1625 PUSH_DATA (push
, 0);
1627 if (mask
!= 0xffffffff) {
1628 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
1629 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
1631 if (nv50
->cond_query
&& info
->render_condition_enable
) {
1632 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
1633 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
1638 nv50_blit(struct pipe_context
*pipe
, const struct pipe_blit_info
*info
)
1640 struct nv50_context
*nv50
= nv50_context(pipe
);
1641 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
1644 if (util_format_is_depth_or_stencil(info
->dst
.resource
->format
)) {
1645 if (!(info
->mask
& PIPE_MASK_ZS
))
1647 if (info
->dst
.resource
->format
== PIPE_FORMAT_Z32_FLOAT
||
1648 info
->dst
.resource
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)
1650 if (info
->filter
!= PIPE_TEX_FILTER_NEAREST
)
1653 if (!(info
->mask
& PIPE_MASK_RGBA
))
1655 if (info
->mask
!= PIPE_MASK_RGBA
)
1659 if (nv50_miptree(info
->src
.resource
)->layout_3d
) {
1662 if (info
->src
.box
.depth
!= info
->dst
.box
.depth
) {
1664 debug_printf("blit: cannot filter array or cube textures in z direction");
1667 if (!eng3d
&& info
->dst
.format
!= info
->src
.format
) {
1668 if (!nv50_2d_dst_format_faithful(info
->dst
.format
) ||
1669 !nv50_2d_src_format_faithful(info
->src
.format
)) {
1672 if (!nv50_2d_src_format_faithful(info
->src
.format
)) {
1673 if (!util_format_is_luminance(info
->src
.format
)) {
1674 if (util_format_is_intensity(info
->src
.format
))
1677 if (!nv50_2d_dst_format_ops_supported(info
->dst
.format
))
1680 eng3d
= !nv50_2d_format_supported(info
->src
.format
);
1683 if (util_format_is_luminance_alpha(info
->src
.format
))
1687 if (info
->src
.resource
->nr_samples
== 8 &&
1688 info
->dst
.resource
->nr_samples
<= 1)
1691 /* FIXME: can't make this work with eng2d anymore */
1692 if ((info
->src
.resource
->nr_samples
| 1) !=
1693 (info
->dst
.resource
->nr_samples
| 1))
1696 /* FIXME: find correct src coordinate adjustments */
1697 if ((info
->src
.box
.width
!= info
->dst
.box
.width
&&
1698 info
->src
.box
.width
!= -info
->dst
.box
.width
) ||
1699 (info
->src
.box
.height
!= info
->dst
.box
.height
&&
1700 info
->src
.box
.height
!= -info
->dst
.box
.height
))
1703 if (nv50
->screen
->num_occlusion_queries_active
) {
1704 BEGIN_NV04(push
, NV50_3D(SAMPLECNT_ENABLE
), 1);
1705 PUSH_DATA (push
, 0);
1709 nv50_blit_eng2d(nv50
, info
);
1711 nv50_blit_3d(nv50
, info
);
1713 if (nv50
->screen
->num_occlusion_queries_active
) {
1714 BEGIN_NV04(push
, NV50_3D(SAMPLECNT_ENABLE
), 1);
1715 PUSH_DATA (push
, 1);
1720 nv50_flush_resource(struct pipe_context
*ctx
,
1721 struct pipe_resource
*resource
)
1726 nv50_blitter_create(struct nv50_screen
*screen
)
1728 screen
->blitter
= CALLOC_STRUCT(nv50_blitter
);
1729 if (!screen
->blitter
) {
1730 NOUVEAU_ERR("failed to allocate blitter struct\n");
1734 pipe_mutex_init(screen
->blitter
->mutex
);
1736 nv50_blitter_make_vp(screen
->blitter
);
1737 nv50_blitter_make_sampler(screen
->blitter
);
1743 nv50_blitter_destroy(struct nv50_screen
*screen
)
1745 struct nv50_blitter
*blitter
= screen
->blitter
;
1748 for (i
= 0; i
< NV50_BLIT_MAX_TEXTURE_TYPES
; ++i
) {
1749 for (m
= 0; m
< NV50_BLIT_MODES
; ++m
) {
1750 struct nv50_program
*prog
= blitter
->fp
[i
][m
];
1752 nv50_program_destroy(NULL
, prog
);
1753 FREE((void *)prog
->pipe
.tokens
);
1763 nv50_blitctx_create(struct nv50_context
*nv50
)
1765 nv50
->blit
= CALLOC_STRUCT(nv50_blitctx
);
1767 NOUVEAU_ERR("failed to allocate blit context\n");
1771 nv50
->blit
->nv50
= nv50
;
1773 nv50
->blit
->rast
.pipe
.half_pixel_center
= 1;
1779 nv50_init_surface_functions(struct nv50_context
*nv50
)
1781 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
1783 pipe
->resource_copy_region
= nv50_resource_copy_region
;
1784 pipe
->blit
= nv50_blit
;
1785 pipe
->flush_resource
= nv50_flush_resource
;
1786 pipe
->clear_texture
= nv50_clear_texture
;
1787 pipe
->clear_render_target
= nv50_clear_render_target
;
1788 pipe
->clear_depth_stencil
= nv50_clear_depth_stencil
;
1789 pipe
->clear_buffer
= nv50_clear_buffer
;