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gallium/util: replace pipe_mutex_unlock() with mtx_unlock()
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_math.h"
31 #include "util/u_surface.h"
32
33 #include "tgsi/tgsi_ureg.h"
34
35 #include "os/os_thread.h"
36
37 #include "nv50/nv50_context.h"
38 #include "nv50/nv50_resource.h"
39
40 #include "nv50/g80_defs.xml.h"
41 #include "nv50/g80_texture.xml.h"
42
43 /* these are used in nv50_blit.h */
44 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
45 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
47 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
48 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
49
50 #define NOUVEAU_DRIVER 0x50
51 #include "nv50/nv50_blit.h"
52
53 static inline uint8_t
54 nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
55 {
56 uint8_t id = nv50_format_table[format].rt;
57
58 /* Hardware values for color formats range from 0xc0 to 0xff,
59 * but the 2D engine doesn't support all of them.
60 */
61 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
62 return id;
63 assert(dst_src_equal);
64
65 switch (util_format_get_blocksize(format)) {
66 case 1:
67 return G80_SURFACE_FORMAT_R8_UNORM;
68 case 2:
69 return G80_SURFACE_FORMAT_R16_UNORM;
70 case 4:
71 return G80_SURFACE_FORMAT_BGRA8_UNORM;
72 case 8:
73 return G80_SURFACE_FORMAT_RGBA16_FLOAT;
74 case 16:
75 return G80_SURFACE_FORMAT_RGBA32_FLOAT;
76 default:
77 return 0;
78 }
79 }
80
81 static int
82 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
83 struct nv50_miptree *mt, unsigned level, unsigned layer,
84 enum pipe_format pformat, bool dst_src_pformat_equal)
85 {
86 struct nouveau_bo *bo = mt->base.bo;
87 uint32_t width, height, depth;
88 uint32_t format;
89 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
90 uint32_t offset = mt->level[level].offset;
91
92 format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
93 if (!format) {
94 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
95 util_format_name(pformat));
96 return 1;
97 }
98
99 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
100 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
101 depth = u_minify(mt->base.base.depth0, level);
102
103 offset = mt->level[level].offset;
104 if (!mt->layout_3d) {
105 offset += mt->layer_stride * layer;
106 depth = 1;
107 layer = 0;
108 } else
109 if (!dst) {
110 offset += nv50_mt_zslice_offset(mt, level, layer);
111 layer = 0;
112 }
113
114 if (!nouveau_bo_memtype(bo)) {
115 BEGIN_NV04(push, SUBC_2D(mthd), 2);
116 PUSH_DATA (push, format);
117 PUSH_DATA (push, 1);
118 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
119 PUSH_DATA (push, mt->level[level].pitch);
120 PUSH_DATA (push, width);
121 PUSH_DATA (push, height);
122 PUSH_DATAh(push, mt->base.address + offset);
123 PUSH_DATA (push, mt->base.address + offset);
124 } else {
125 BEGIN_NV04(push, SUBC_2D(mthd), 5);
126 PUSH_DATA (push, format);
127 PUSH_DATA (push, 0);
128 PUSH_DATA (push, mt->level[level].tile_mode);
129 PUSH_DATA (push, depth);
130 PUSH_DATA (push, layer);
131 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
132 PUSH_DATA (push, width);
133 PUSH_DATA (push, height);
134 PUSH_DATAh(push, mt->base.address + offset);
135 PUSH_DATA (push, mt->base.address + offset);
136 }
137
138 #if 0
139 if (dst) {
140 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
141 PUSH_DATA (push, 0);
142 PUSH_DATA (push, 0);
143 PUSH_DATA (push, width);
144 PUSH_DATA (push, height);
145 }
146 #endif
147 return 0;
148 }
149
150 static int
151 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
152 struct nv50_miptree *dst, unsigned dst_level,
153 unsigned dx, unsigned dy, unsigned dz,
154 struct nv50_miptree *src, unsigned src_level,
155 unsigned sx, unsigned sy, unsigned sz,
156 unsigned w, unsigned h)
157 {
158 const enum pipe_format dfmt = dst->base.base.format;
159 const enum pipe_format sfmt = src->base.base.format;
160 int ret;
161 bool eqfmt = dfmt == sfmt;
162
163 if (!PUSH_SPACE(push, 2 * 16 + 32))
164 return PIPE_ERROR;
165
166 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
167 if (ret)
168 return ret;
169
170 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
171 if (ret)
172 return ret;
173
174 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
175 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
176 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
177 PUSH_DATA (push, dx << dst->ms_x);
178 PUSH_DATA (push, dy << dst->ms_y);
179 PUSH_DATA (push, w << dst->ms_x);
180 PUSH_DATA (push, h << dst->ms_y);
181 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
182 PUSH_DATA (push, 0);
183 PUSH_DATA (push, 1);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, 1);
186 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
187 PUSH_DATA (push, 0);
188 PUSH_DATA (push, sx << src->ms_x);
189 PUSH_DATA (push, 0);
190 PUSH_DATA (push, sy << src->ms_y);
191
192 return 0;
193 }
194
195 static void
196 nv50_resource_copy_region(struct pipe_context *pipe,
197 struct pipe_resource *dst, unsigned dst_level,
198 unsigned dstx, unsigned dsty, unsigned dstz,
199 struct pipe_resource *src, unsigned src_level,
200 const struct pipe_box *src_box)
201 {
202 struct nv50_context *nv50 = nv50_context(pipe);
203 int ret;
204 bool m2mf;
205 unsigned dst_layer = dstz, src_layer = src_box->z;
206
207 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
208 nouveau_copy_buffer(&nv50->base,
209 nv04_resource(dst), dstx,
210 nv04_resource(src), src_box->x, src_box->width);
211 return;
212 }
213
214 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
215 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
216
217 m2mf = (src->format == dst->format) ||
218 (util_format_get_blocksizebits(src->format) ==
219 util_format_get_blocksizebits(dst->format));
220
221 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
222
223 if (m2mf) {
224 struct nv50_miptree *src_mt = nv50_miptree(src);
225 struct nv50_miptree *dst_mt = nv50_miptree(dst);
226 struct nv50_m2mf_rect drect, srect;
227 unsigned i;
228 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
229 << src_mt->ms_x;
230 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
231 << src_mt->ms_y;
232
233 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
234 nv50_m2mf_rect_setup(&srect, src, src_level,
235 src_box->x, src_box->y, src_box->z);
236
237 for (i = 0; i < src_box->depth; ++i) {
238 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
239
240 if (dst_mt->layout_3d)
241 drect.z++;
242 else
243 drect.base += dst_mt->layer_stride;
244
245 if (src_mt->layout_3d)
246 srect.z++;
247 else
248 srect.base += src_mt->layer_stride;
249 }
250 return;
251 }
252
253 assert((src->format == dst->format) ||
254 (nv50_2d_src_format_faithful(src->format) &&
255 nv50_2d_dst_format_faithful(dst->format)));
256
257 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
258 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
259 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
260 nouveau_pushbuf_validate(nv50->base.pushbuf);
261
262 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
263 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
264 nv50_miptree(dst), dst_level,
265 dstx, dsty, dst_layer,
266 nv50_miptree(src), src_level,
267 src_box->x, src_box->y, src_layer,
268 src_box->width, src_box->height);
269 if (ret)
270 break;
271 }
272 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
273 }
274
275 static void
276 nv50_clear_render_target(struct pipe_context *pipe,
277 struct pipe_surface *dst,
278 const union pipe_color_union *color,
279 unsigned dstx, unsigned dsty,
280 unsigned width, unsigned height,
281 bool render_condition_enabled)
282 {
283 struct nv50_context *nv50 = nv50_context(pipe);
284 struct nouveau_pushbuf *push = nv50->base.pushbuf;
285 struct nv50_miptree *mt = nv50_miptree(dst->texture);
286 struct nv50_surface *sf = nv50_surface(dst);
287 struct nouveau_bo *bo = mt->base.bo;
288 unsigned z;
289
290 assert(dst->texture->target != PIPE_BUFFER);
291
292 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
293 PUSH_DATAf(push, color->f[0]);
294 PUSH_DATAf(push, color->f[1]);
295 PUSH_DATAf(push, color->f[2]);
296 PUSH_DATAf(push, color->f[3]);
297
298 if (nouveau_pushbuf_space(push, 64 + sf->depth, 1, 0))
299 return;
300
301 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
302
303 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
304 PUSH_DATA (push, ( width << 16) | dstx);
305 PUSH_DATA (push, (height << 16) | dsty);
306 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
307 PUSH_DATA (push, 8192 << 16);
308 PUSH_DATA (push, 8192 << 16);
309 nv50->scissors_dirty |= 1;
310
311 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
312 PUSH_DATA (push, 1);
313 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
314 PUSH_DATAh(push, mt->base.address + sf->offset);
315 PUSH_DATA (push, mt->base.address + sf->offset);
316 PUSH_DATA (push, nv50_format_table[dst->format].rt);
317 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
318 PUSH_DATA (push, mt->layer_stride >> 2);
319 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
320 if (nouveau_bo_memtype(bo))
321 PUSH_DATA(push, sf->width);
322 else
323 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
324 PUSH_DATA (push, sf->height);
325 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
326 if (mt->layout_3d)
327 PUSH_DATA(push, NV50_3D_RT_ARRAY_MODE_MODE_3D | 512);
328 else
329 PUSH_DATA(push, 512);
330
331 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
332 PUSH_DATA (push, mt->ms_mode);
333
334 if (!nouveau_bo_memtype(bo)) {
335 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
336 PUSH_DATA (push, 0);
337 }
338
339 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
340
341 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
342 PUSH_DATA (push, (width << 16) | dstx);
343 PUSH_DATA (push, (height << 16) | dsty);
344
345 if (!render_condition_enabled) {
346 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
347 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
348 }
349
350 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
351 for (z = 0; z < sf->depth; ++z) {
352 PUSH_DATA (push, 0x3c |
353 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
354 }
355
356 if (!render_condition_enabled) {
357 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
358 PUSH_DATA (push, nv50->cond_condmode);
359 }
360
361 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
362 }
363
364 static void
365 nv50_clear_depth_stencil(struct pipe_context *pipe,
366 struct pipe_surface *dst,
367 unsigned clear_flags,
368 double depth,
369 unsigned stencil,
370 unsigned dstx, unsigned dsty,
371 unsigned width, unsigned height,
372 bool render_condition_enabled)
373 {
374 struct nv50_context *nv50 = nv50_context(pipe);
375 struct nouveau_pushbuf *push = nv50->base.pushbuf;
376 struct nv50_miptree *mt = nv50_miptree(dst->texture);
377 struct nv50_surface *sf = nv50_surface(dst);
378 struct nouveau_bo *bo = mt->base.bo;
379 uint32_t mode = 0;
380 unsigned z;
381
382 assert(dst->texture->target != PIPE_BUFFER);
383 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
384
385 if (clear_flags & PIPE_CLEAR_DEPTH) {
386 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
387 PUSH_DATAf(push, depth);
388 mode |= NV50_3D_CLEAR_BUFFERS_Z;
389 }
390
391 if (clear_flags & PIPE_CLEAR_STENCIL) {
392 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
393 PUSH_DATA (push, stencil & 0xff);
394 mode |= NV50_3D_CLEAR_BUFFERS_S;
395 }
396
397 if (nouveau_pushbuf_space(push, 64 + sf->depth, 1, 0))
398 return;
399
400 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
401
402 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
403 PUSH_DATA (push, ( width << 16) | dstx);
404 PUSH_DATA (push, (height << 16) | dsty);
405 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
406 PUSH_DATA (push, 8192 << 16);
407 PUSH_DATA (push, 8192 << 16);
408 nv50->scissors_dirty |= 1;
409
410 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
411 PUSH_DATAh(push, mt->base.address + sf->offset);
412 PUSH_DATA (push, mt->base.address + sf->offset);
413 PUSH_DATA (push, nv50_format_table[dst->format].rt);
414 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
415 PUSH_DATA (push, mt->layer_stride >> 2);
416 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
417 PUSH_DATA (push, 1);
418 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
419 PUSH_DATA (push, sf->width);
420 PUSH_DATA (push, sf->height);
421 PUSH_DATA (push, (1 << 16) | 1);
422
423 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
424 PUSH_DATA (push, 512);
425
426 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
427 PUSH_DATA (push, mt->ms_mode);
428
429 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
430 PUSH_DATA (push, (width << 16) | dstx);
431 PUSH_DATA (push, (height << 16) | dsty);
432
433 if (!render_condition_enabled) {
434 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
435 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
436 }
437
438 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
439 for (z = 0; z < sf->depth; ++z) {
440 PUSH_DATA (push, mode |
441 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
442 }
443
444 if (!render_condition_enabled) {
445 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
446 PUSH_DATA (push, nv50->cond_condmode);
447 }
448
449 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
450 }
451
452 void
453 nv50_clear_texture(struct pipe_context *pipe,
454 struct pipe_resource *res,
455 unsigned level,
456 const struct pipe_box *box,
457 const void *data)
458 {
459 struct pipe_surface tmpl = {{0}}, *sf;
460
461 tmpl.format = res->format;
462 tmpl.u.tex.first_layer = box->z;
463 tmpl.u.tex.last_layer = box->z + box->depth - 1;
464 tmpl.u.tex.level = level;
465 sf = pipe->create_surface(pipe, res, &tmpl);
466 if (!sf)
467 return;
468
469 if (util_format_is_depth_or_stencil(res->format)) {
470 float depth = 0;
471 uint8_t stencil = 0;
472 unsigned clear = 0;
473 const struct util_format_description *desc =
474 util_format_description(res->format);
475
476 if (util_format_has_depth(desc)) {
477 clear |= PIPE_CLEAR_DEPTH;
478 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
479 }
480 if (util_format_has_stencil(desc)) {
481 clear |= PIPE_CLEAR_STENCIL;
482 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
483 }
484 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
485 box->x, box->y, box->width, box->height, false);
486 } else {
487 union pipe_color_union color;
488
489 switch (util_format_get_blocksizebits(res->format)) {
490 case 128:
491 sf->format = PIPE_FORMAT_R32G32B32A32_UINT;
492 memcpy(&color.ui, data, 128 / 8);
493 break;
494 case 64:
495 sf->format = PIPE_FORMAT_R32G32_UINT;
496 memcpy(&color.ui, data, 64 / 8);
497 memset(&color.ui[2], 0, 64 / 8);
498 break;
499 case 32:
500 sf->format = PIPE_FORMAT_R32_UINT;
501 memcpy(&color.ui, data, 32 / 8);
502 memset(&color.ui[1], 0, 96 / 8);
503 break;
504 case 16:
505 sf->format = PIPE_FORMAT_R16_UINT;
506 color.ui[0] = util_cpu_to_le32(
507 util_le16_to_cpu(*(unsigned short *)data));
508 memset(&color.ui[1], 0, 96 / 8);
509 break;
510 case 8:
511 sf->format = PIPE_FORMAT_R8_UINT;
512 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
513 memset(&color.ui[1], 0, 96 / 8);
514 break;
515 default:
516 assert(!"Unknown texel element size");
517 return;
518 }
519
520 pipe->clear_render_target(pipe, sf, &color,
521 box->x, box->y, box->width, box->height, false);
522 }
523 pipe->surface_destroy(pipe, sf);
524 }
525
526 void
527 nv50_clear(struct pipe_context *pipe, unsigned buffers,
528 const union pipe_color_union *color,
529 double depth, unsigned stencil)
530 {
531 struct nv50_context *nv50 = nv50_context(pipe);
532 struct nouveau_pushbuf *push = nv50->base.pushbuf;
533 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
534 unsigned i, j, k;
535 uint32_t mode = 0;
536
537 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
538 if (!nv50_state_validate_3d(nv50, NV50_NEW_3D_FRAMEBUFFER))
539 return;
540
541 /* We have to clear ALL of the layers, not up to the min number of layers
542 * of any attachment. */
543 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
544 PUSH_DATA (push, (nv50->rt_array_mode & NV50_3D_RT_ARRAY_MODE_MODE_3D) | 512);
545
546 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
547 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
548 PUSH_DATAf(push, color->f[0]);
549 PUSH_DATAf(push, color->f[1]);
550 PUSH_DATAf(push, color->f[2]);
551 PUSH_DATAf(push, color->f[3]);
552 if (buffers & PIPE_CLEAR_COLOR0)
553 mode =
554 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
555 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
556 }
557
558 if (buffers & PIPE_CLEAR_DEPTH) {
559 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
560 PUSH_DATA (push, fui(depth));
561 mode |= NV50_3D_CLEAR_BUFFERS_Z;
562 }
563
564 if (buffers & PIPE_CLEAR_STENCIL) {
565 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
566 PUSH_DATA (push, stencil & 0xff);
567 mode |= NV50_3D_CLEAR_BUFFERS_S;
568 }
569
570 if (mode) {
571 int zs_layers = 0, color0_layers = 0;
572 if (fb->cbufs[0] && (mode & 0x3c))
573 color0_layers = nv50_surface(fb->cbufs[0])->depth;
574 if (fb->zsbuf && (mode & ~0x3c))
575 zs_layers = nv50_surface(fb->zsbuf)->depth;
576
577 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
578 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
579 PUSH_DATA(push, mode | (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
580 }
581 for (k = j; k < zs_layers; k++) {
582 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
583 PUSH_DATA(push, (mode & ~0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
584 }
585 for (k = j; k < color0_layers; k++) {
586 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
587 PUSH_DATA(push, (mode & 0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
588 }
589 }
590
591 for (i = 1; i < fb->nr_cbufs; i++) {
592 struct pipe_surface *sf = fb->cbufs[i];
593 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
594 continue;
595 for (j = 0; j < nv50_surface(sf)->depth; j++) {
596 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
597 PUSH_DATA (push, (i << 6) | 0x3c |
598 (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
599 }
600 }
601
602 /* restore the array mode */
603 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
604 PUSH_DATA (push, nv50->rt_array_mode);
605 }
606
607 static void
608 nv50_clear_buffer_push(struct pipe_context *pipe,
609 struct pipe_resource *res,
610 unsigned offset, unsigned size,
611 const void *data, int data_size)
612 {
613 struct nv50_context *nv50 = nv50_context(pipe);
614 struct nouveau_pushbuf *push = nv50->base.pushbuf;
615 struct nv04_resource *buf = nv04_resource(res);
616 unsigned count = (size + 3) / 4;
617 unsigned xcoord = offset & 0xff;
618 unsigned tmp, i;
619
620 if (data_size == 1) {
621 tmp = *(unsigned char *)data;
622 tmp = (tmp << 24) | (tmp << 16) | (tmp << 8) | tmp;
623 data = &tmp;
624 data_size = 4;
625 } else if (data_size == 2) {
626 tmp = *(unsigned short *)data;
627 tmp = (tmp << 16) | tmp;
628 data = &tmp;
629 data_size = 4;
630 }
631
632 unsigned data_words = data_size / 4;
633
634 nouveau_bufctx_refn(nv50->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
635 nouveau_pushbuf_bufctx(push, nv50->bufctx);
636 nouveau_pushbuf_validate(push);
637
638 offset &= ~0xff;
639
640 BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
641 PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
642 PUSH_DATA (push, 1);
643 BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
644 PUSH_DATA (push, 262144);
645 PUSH_DATA (push, 65536);
646 PUSH_DATA (push, 1);
647 PUSH_DATAh(push, buf->address + offset);
648 PUSH_DATA (push, buf->address + offset);
649 BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
650 PUSH_DATA (push, 0);
651 PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
652 BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
653 PUSH_DATA (push, size);
654 PUSH_DATA (push, 1);
655 PUSH_DATA (push, 0);
656 PUSH_DATA (push, 1);
657 PUSH_DATA (push, 0);
658 PUSH_DATA (push, 1);
659 PUSH_DATA (push, 0);
660 PUSH_DATA (push, xcoord);
661 PUSH_DATA (push, 0);
662 PUSH_DATA (push, 0);
663
664 while (count) {
665 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
666 unsigned nr = nr_data * data_words;
667
668 BEGIN_NI04(push, NV50_2D(SIFC_DATA), nr);
669 for (i = 0; i < nr_data; i++)
670 PUSH_DATAp(push, data, data_words);
671
672 count -= nr;
673 }
674
675 if (buf->mm) {
676 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
677 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
678 }
679
680 nouveau_bufctx_reset(nv50->bufctx, 0);
681 }
682
683 static void
684 nv50_clear_buffer(struct pipe_context *pipe,
685 struct pipe_resource *res,
686 unsigned offset, unsigned size,
687 const void *data, int data_size)
688 {
689 struct nv50_context *nv50 = nv50_context(pipe);
690 struct nouveau_pushbuf *push = nv50->base.pushbuf;
691 struct nv04_resource *buf = (struct nv04_resource *)res;
692 union pipe_color_union color;
693 enum pipe_format dst_fmt;
694 unsigned width, height, elements;
695
696 assert(res->target == PIPE_BUFFER);
697 assert(nouveau_bo_memtype(buf->bo) == 0);
698
699 switch (data_size) {
700 case 16:
701 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
702 memcpy(&color.ui, data, 16);
703 break;
704 case 8:
705 dst_fmt = PIPE_FORMAT_R32G32_UINT;
706 memcpy(&color.ui, data, 8);
707 memset(&color.ui[2], 0, 8);
708 break;
709 case 4:
710 dst_fmt = PIPE_FORMAT_R32_UINT;
711 memcpy(&color.ui, data, 4);
712 memset(&color.ui[1], 0, 12);
713 break;
714 case 2:
715 dst_fmt = PIPE_FORMAT_R16_UINT;
716 color.ui[0] = util_cpu_to_le32(
717 util_le16_to_cpu(*(unsigned short *)data));
718 memset(&color.ui[1], 0, 12);
719 break;
720 case 1:
721 dst_fmt = PIPE_FORMAT_R8_UINT;
722 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
723 memset(&color.ui[1], 0, 12);
724 break;
725 default:
726 assert(!"Unsupported element size");
727 return;
728 }
729
730 assert(size % data_size == 0);
731
732 if (offset & 0xff) {
733 unsigned fixup_size = MIN2(size, align(offset, 0x100) - offset);
734 assert(fixup_size % data_size == 0);
735 nv50_clear_buffer_push(pipe, res, offset, fixup_size, data, data_size);
736 offset += fixup_size;
737 size -= fixup_size;
738 if (!size)
739 return;
740 }
741
742 elements = size / data_size;
743 height = (elements + 8191) / 8192;
744 width = elements / height;
745 if (height > 1)
746 width &= ~0xff;
747 assert(width > 0);
748
749 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
750 PUSH_DATAf(push, color.f[0]);
751 PUSH_DATAf(push, color.f[1]);
752 PUSH_DATAf(push, color.f[2]);
753 PUSH_DATAf(push, color.f[3]);
754
755 if (nouveau_pushbuf_space(push, 64, 1, 0))
756 return;
757
758 PUSH_REFN(push, buf->bo, buf->domain | NOUVEAU_BO_WR);
759
760 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
761 PUSH_DATA (push, width << 16);
762 PUSH_DATA (push, height << 16);
763 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
764 PUSH_DATA (push, 8192 << 16);
765 PUSH_DATA (push, 8192 << 16);
766 nv50->scissors_dirty |= 1;
767
768 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
769 PUSH_DATA (push, 1);
770 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
771 PUSH_DATAh(push, buf->address + offset);
772 PUSH_DATA (push, buf->address + offset);
773 PUSH_DATA (push, nv50_format_table[dst_fmt].rt);
774 PUSH_DATA (push, 0);
775 PUSH_DATA (push, 0);
776 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
777 PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | align(width * data_size, 0x100));
778 PUSH_DATA (push, height);
779 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
780 PUSH_DATA (push, 0);
781 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
782 PUSH_DATA (push, 0);
783
784 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
785
786 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
787 PUSH_DATA (push, (width << 16));
788 PUSH_DATA (push, (height << 16));
789
790 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
791 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
792
793 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
794 PUSH_DATA (push, 0x3c);
795
796 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
797 PUSH_DATA (push, nv50->cond_condmode);
798
799 if (buf->mm) {
800 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
801 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
802 }
803
804 if (width * height != elements) {
805 offset += width * height * data_size;
806 width = elements - width * height;
807 nv50_clear_buffer_push(pipe, res, offset, width * data_size,
808 data, data_size);
809 }
810
811 nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR;
812 }
813
814 /* =============================== BLIT CODE ===================================
815 */
816
817 struct nv50_blitter
818 {
819 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
820 struct nv50_program vp;
821
822 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
823
824 mtx_t mutex;
825 };
826
827 struct nv50_blitctx
828 {
829 struct nv50_context *nv50;
830 struct nv50_program *fp;
831 uint8_t mode;
832 uint16_t color_mask;
833 uint8_t filter;
834 uint8_t render_condition_enable;
835 enum pipe_texture_target target;
836 struct {
837 struct pipe_framebuffer_state fb;
838 struct nv50_window_rect_stateobj window_rect;
839 struct nv50_rasterizer_stateobj *rast;
840 struct nv50_program *vp;
841 struct nv50_program *gp;
842 struct nv50_program *fp;
843 unsigned num_textures[3];
844 unsigned num_samplers[3];
845 struct pipe_sampler_view *texture[2];
846 struct nv50_tsc_entry *sampler[2];
847 unsigned min_samples;
848 uint32_t dirty_3d;
849 } saved;
850 struct nv50_rasterizer_stateobj rast;
851 };
852
853 static void
854 nv50_blitter_make_vp(struct nv50_blitter *blit)
855 {
856 static const uint32_t code[] =
857 {
858 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
859 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
860 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
861 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
862 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
863 };
864
865 blit->vp.type = PIPE_SHADER_VERTEX;
866 blit->vp.translated = true;
867 blit->vp.code = (uint32_t *)code; /* const_cast */
868 blit->vp.code_size = sizeof(code);
869 blit->vp.max_gpr = 4;
870 blit->vp.max_out = 5;
871 blit->vp.out_nr = 2;
872 blit->vp.out[0].mask = 0x3;
873 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
874 blit->vp.out[1].hw = 2;
875 blit->vp.out[1].mask = 0x7;
876 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
877 blit->vp.out[1].si = 0;
878 blit->vp.vp.attrs[0] = 0x73;
879 blit->vp.vp.psiz = 0x40;
880 blit->vp.vp.edgeflag = 0x40;
881 }
882
883 void *
884 nv50_blitter_make_fp(struct pipe_context *pipe,
885 unsigned mode,
886 enum pipe_texture_target ptarg)
887 {
888 struct ureg_program *ureg;
889 struct ureg_src tc;
890 struct ureg_dst out;
891 struct ureg_dst data;
892
893 const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
894
895 bool tex_rgbaz = false;
896 bool tex_s = false;
897 bool cvt_un8 = false;
898
899 if (mode != NV50_BLIT_MODE_PASS &&
900 mode != NV50_BLIT_MODE_Z24X8 &&
901 mode != NV50_BLIT_MODE_X8Z24)
902 tex_s = true;
903
904 if (mode != NV50_BLIT_MODE_X24S8 &&
905 mode != NV50_BLIT_MODE_S8X24 &&
906 mode != NV50_BLIT_MODE_XS)
907 tex_rgbaz = true;
908
909 if (mode != NV50_BLIT_MODE_PASS &&
910 mode != NV50_BLIT_MODE_ZS &&
911 mode != NV50_BLIT_MODE_XS)
912 cvt_un8 = true;
913
914 ureg = ureg_create(PIPE_SHADER_FRAGMENT);
915 if (!ureg)
916 return NULL;
917
918 out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
919 tc = ureg_DECL_fs_input(
920 ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
921
922 if (ptarg == PIPE_TEXTURE_1D_ARRAY) {
923 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
924 tc = ureg_swizzle(tc, TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
925 TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Z);
926 }
927
928 data = ureg_DECL_temporary(ureg);
929
930 if (tex_s) {
931 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
932 target, tc, ureg_DECL_sampler(ureg, 1));
933 ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
934 ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
935 }
936 if (tex_rgbaz) {
937 const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
938 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
939 ureg_TEX(ureg, ureg_writemask(data, mask),
940 target, tc, ureg_DECL_sampler(ureg, 0));
941 }
942
943 if (cvt_un8) {
944 struct ureg_src mask;
945 struct ureg_src scale;
946 struct ureg_dst outz;
947 struct ureg_dst outs;
948 struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
949 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
950 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
951 struct ureg_src zsrc3 = ureg_src(data);
952 struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
953 struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
954 struct ureg_src zshuf;
955
956 mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
957 scale = ureg_imm4f(ureg,
958 1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
959 (1 << 24) - 1);
960
961 if (mode == NV50_BLIT_MODE_Z24S8 ||
962 mode == NV50_BLIT_MODE_X24S8 ||
963 mode == NV50_BLIT_MODE_Z24X8) {
964 outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
965 outs = ureg_writemask(out, TGSI_WRITEMASK_W);
966 zshuf = ureg_src(data);
967 } else {
968 outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
969 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
970 zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
971 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
972 }
973
974 if (tex_s) {
975 ureg_I2F(ureg, sdst, ssrc);
976 ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
977 }
978
979 if (tex_rgbaz) {
980 ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
981 ureg_F2I(ureg, zdst, zsrc);
982 ureg_AND(ureg, zdst3, zsrc, mask);
983 ureg_I2F(ureg, zdst3, zsrc3);
984 ureg_MUL(ureg, zdst3, zsrc3, scale);
985 ureg_MOV(ureg, outz, zshuf);
986 }
987 } else {
988 unsigned mask = TGSI_WRITEMASK_XYZW;
989
990 if (mode != NV50_BLIT_MODE_PASS) {
991 mask &= ~TGSI_WRITEMASK_ZW;
992 if (!tex_s)
993 mask = TGSI_WRITEMASK_X;
994 if (!tex_rgbaz)
995 mask = TGSI_WRITEMASK_Y;
996 }
997 ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
998 }
999 ureg_END(ureg);
1000
1001 return ureg_create_shader_and_destroy(ureg, pipe);
1002 }
1003
1004 static void
1005 nv50_blitter_make_sampler(struct nv50_blitter *blit)
1006 {
1007 /* clamp to edge, min/max lod = 0, nearest filtering */
1008
1009 blit->sampler[0].id = -1;
1010
1011 blit->sampler[0].tsc[0] = G80_TSC_0_SRGB_CONVERSION |
1012 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_U__SHIFT) |
1013 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_V__SHIFT) |
1014 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_P__SHIFT);
1015 blit->sampler[0].tsc[1] =
1016 G80_TSC_1_MAG_FILTER_NEAREST |
1017 G80_TSC_1_MIN_FILTER_NEAREST |
1018 G80_TSC_1_MIP_FILTER_NONE;
1019
1020 /* clamp to edge, min/max lod = 0, bilinear filtering */
1021
1022 blit->sampler[1].id = -1;
1023
1024 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
1025 blit->sampler[1].tsc[1] =
1026 G80_TSC_1_MAG_FILTER_LINEAR |
1027 G80_TSC_1_MIN_FILTER_LINEAR |
1028 G80_TSC_1_MIP_FILTER_NONE;
1029 }
1030
1031 unsigned
1032 nv50_blit_select_mode(const struct pipe_blit_info *info)
1033 {
1034 const unsigned mask = info->mask;
1035
1036 switch (info->dst.resource->format) {
1037 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1038 case PIPE_FORMAT_Z24X8_UNORM:
1039 case PIPE_FORMAT_X24S8_UINT:
1040 switch (mask & PIPE_MASK_ZS) {
1041 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
1042 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
1043 default:
1044 return NV50_BLIT_MODE_X24S8;
1045 }
1046 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1047 case PIPE_FORMAT_X8Z24_UNORM:
1048 case PIPE_FORMAT_S8X24_UINT:
1049 switch (mask & PIPE_MASK_ZS) {
1050 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
1051 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
1052 default:
1053 return NV50_BLIT_MODE_S8X24;
1054 }
1055 case PIPE_FORMAT_Z32_FLOAT:
1056 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1057 case PIPE_FORMAT_X32_S8X24_UINT:
1058 switch (mask & PIPE_MASK_ZS) {
1059 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
1060 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
1061 default:
1062 return NV50_BLIT_MODE_XS;
1063 }
1064 default:
1065 return NV50_BLIT_MODE_PASS;
1066 }
1067 }
1068
1069 static void
1070 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
1071 {
1072 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
1073
1074 const enum pipe_texture_target ptarg =
1075 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
1076
1077 const unsigned targ = nv50_blit_texture_type(ptarg);
1078 const unsigned mode = ctx->mode;
1079
1080 if (!blitter->fp[targ][mode]) {
1081 mtx_lock(&blitter->mutex);
1082 if (!blitter->fp[targ][mode])
1083 blitter->fp[targ][mode] =
1084 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
1085 mtx_unlock(&blitter->mutex);
1086 }
1087 ctx->fp = blitter->fp[targ][mode];
1088 }
1089
1090 static void
1091 nv50_blit_set_dst(struct nv50_blitctx *ctx,
1092 struct pipe_resource *res, unsigned level, unsigned layer,
1093 enum pipe_format format)
1094 {
1095 struct nv50_context *nv50 = ctx->nv50;
1096 struct pipe_context *pipe = &nv50->base.pipe;
1097 struct pipe_surface templ;
1098
1099 if (util_format_is_depth_or_stencil(format))
1100 templ.format = nv50_blit_zeta_to_colour_format(format);
1101 else
1102 templ.format = format;
1103
1104 templ.u.tex.level = level;
1105 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
1106
1107 if (layer == -1) {
1108 templ.u.tex.first_layer = 0;
1109 templ.u.tex.last_layer =
1110 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
1111 }
1112
1113 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
1114 nv50->framebuffer.nr_cbufs = 1;
1115 nv50->framebuffer.zsbuf = NULL;
1116 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
1117 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
1118 }
1119
1120 static void
1121 nv50_blit_set_src(struct nv50_blitctx *blit,
1122 struct pipe_resource *res, unsigned level, unsigned layer,
1123 enum pipe_format format, const uint8_t filter)
1124 {
1125 struct nv50_context *nv50 = blit->nv50;
1126 struct pipe_context *pipe = &nv50->base.pipe;
1127 struct pipe_sampler_view templ;
1128 uint32_t flags;
1129 enum pipe_texture_target target;
1130
1131 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
1132
1133 templ.format = format;
1134 templ.u.tex.first_level = templ.u.tex.last_level = level;
1135 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
1136 templ.swizzle_r = PIPE_SWIZZLE_X;
1137 templ.swizzle_g = PIPE_SWIZZLE_Y;
1138 templ.swizzle_b = PIPE_SWIZZLE_Z;
1139 templ.swizzle_a = PIPE_SWIZZLE_W;
1140
1141 if (layer == -1) {
1142 templ.u.tex.first_layer = 0;
1143 templ.u.tex.last_layer =
1144 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
1145 }
1146
1147 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
1148 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
1149 if (filter && res->nr_samples == 8)
1150 flags |= NV50_TEXVIEW_FILTER_MSAA8;
1151
1152 nv50->textures[2][0] = nv50_create_texture_view(
1153 pipe, res, &templ, flags, target);
1154 nv50->textures[2][1] = NULL;
1155
1156 nv50->num_textures[0] = nv50->num_textures[1] = 0;
1157 nv50->num_textures[2] = 1;
1158
1159 templ.format = nv50_zs_to_s_format(format);
1160 if (templ.format != res->format) {
1161 nv50->textures[2][1] = nv50_create_texture_view(
1162 pipe, res, &templ, flags, target);
1163 nv50->num_textures[2] = 2;
1164 }
1165 }
1166
1167 static void
1168 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
1169 {
1170 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
1171
1172 if (blit->nv50->cond_query && !blit->render_condition_enable) {
1173 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
1174 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
1175 }
1176
1177 /* blend state */
1178 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
1179 PUSH_DATA (push, blit->color_mask);
1180 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
1181 PUSH_DATA (push, 0);
1182 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
1183 PUSH_DATA (push, 0);
1184
1185 /* rasterizer state */
1186 #ifndef NV50_SCISSORS_CLIPPING
1187 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
1188 PUSH_DATA (push, 1);
1189 #endif
1190 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
1191 PUSH_DATA (push, 0);
1192 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
1193 PUSH_DATA (push, 0);
1194 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
1195 PUSH_DATA (push, 0);
1196 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
1197 PUSH_DATA (push, 0xffff);
1198 PUSH_DATA (push, 0xffff);
1199 PUSH_DATA (push, 0xffff);
1200 PUSH_DATA (push, 0xffff);
1201 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
1202 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
1203 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
1204 PUSH_DATA (push, 0);
1205 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
1206 PUSH_DATA (push, 0);
1207 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
1208 PUSH_DATA (push, 0);
1209 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
1210 PUSH_DATA (push, 0);
1211
1212 /* zsa state */
1213 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
1214 PUSH_DATA (push, 0);
1215 BEGIN_NV04(push, NV50_3D(DEPTH_BOUNDS_EN), 1);
1216 PUSH_DATA (push, 0);
1217 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
1218 PUSH_DATA (push, 0);
1219 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
1220 PUSH_DATA (push, 0);
1221 }
1222
1223 static void
1224 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx,
1225 const struct pipe_blit_info *info)
1226 {
1227 struct nv50_context *nv50 = ctx->nv50;
1228 struct nv50_blitter *blitter = nv50->screen->blitter;
1229 int s;
1230
1231 ctx->saved.fb.width = nv50->framebuffer.width;
1232 ctx->saved.fb.height = nv50->framebuffer.height;
1233 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
1234 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
1235 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
1236
1237 ctx->saved.rast = nv50->rast;
1238
1239 ctx->saved.vp = nv50->vertprog;
1240 ctx->saved.gp = nv50->gmtyprog;
1241 ctx->saved.fp = nv50->fragprog;
1242
1243 ctx->saved.min_samples = nv50->min_samples;
1244 ctx->saved.window_rect = nv50->window_rect;
1245
1246 nv50->rast = &ctx->rast;
1247
1248 nv50->vertprog = &blitter->vp;
1249 nv50->gmtyprog = NULL;
1250 nv50->fragprog = ctx->fp;
1251
1252 nv50->window_rect.rects =
1253 MIN2(info->num_window_rectangles, NV50_MAX_WINDOW_RECTANGLES);
1254 nv50->window_rect.inclusive = info->window_rectangle_include;
1255 if (nv50->window_rect.rects)
1256 memcpy(nv50->window_rect.rect, info->window_rectangles,
1257 sizeof(struct pipe_scissor_state) * nv50->window_rect.rects);
1258
1259 for (s = 0; s < 3; ++s) {
1260 ctx->saved.num_textures[s] = nv50->num_textures[s];
1261 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
1262 }
1263 ctx->saved.texture[0] = nv50->textures[2][0];
1264 ctx->saved.texture[1] = nv50->textures[2][1];
1265 ctx->saved.sampler[0] = nv50->samplers[2][0];
1266 ctx->saved.sampler[1] = nv50->samplers[2][1];
1267
1268 nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
1269 nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
1270
1271 nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
1272 nv50->num_samplers[2] = 2;
1273
1274 nv50->min_samples = 1;
1275
1276 ctx->saved.dirty_3d = nv50->dirty_3d;
1277
1278 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
1279 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
1280
1281 nv50->dirty_3d =
1282 NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_MIN_SAMPLES |
1283 NV50_NEW_3D_VERTPROG | NV50_NEW_3D_FRAGPROG | NV50_NEW_3D_GMTYPROG |
1284 NV50_NEW_3D_TEXTURES | NV50_NEW_3D_SAMPLERS | NV50_NEW_3D_WINDOW_RECTS;
1285 }
1286
1287 static void
1288 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
1289 {
1290 struct nv50_context *nv50 = blit->nv50;
1291 int s;
1292
1293 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
1294
1295 nv50->framebuffer.width = blit->saved.fb.width;
1296 nv50->framebuffer.height = blit->saved.fb.height;
1297 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1298 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1299 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1300
1301 nv50->rast = blit->saved.rast;
1302
1303 nv50->vertprog = blit->saved.vp;
1304 nv50->gmtyprog = blit->saved.gp;
1305 nv50->fragprog = blit->saved.fp;
1306
1307 nv50->min_samples = blit->saved.min_samples;
1308 nv50->window_rect = blit->saved.window_rect;
1309
1310 pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
1311 pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
1312
1313 for (s = 0; s < 3; ++s) {
1314 nv50->num_textures[s] = blit->saved.num_textures[s];
1315 nv50->num_samplers[s] = blit->saved.num_samplers[s];
1316 }
1317 nv50->textures[2][0] = blit->saved.texture[0];
1318 nv50->textures[2][1] = blit->saved.texture[1];
1319 nv50->samplers[2][0] = blit->saved.sampler[0];
1320 nv50->samplers[2][1] = blit->saved.sampler[1];
1321
1322 if (nv50->cond_query && !blit->render_condition_enable)
1323 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
1324 nv50->cond_cond, nv50->cond_mode);
1325
1326 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
1327 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
1328
1329 nv50->dirty_3d = blit->saved.dirty_3d |
1330 (NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_SCISSOR | NV50_NEW_3D_SAMPLE_MASK |
1331 NV50_NEW_3D_RASTERIZER | NV50_NEW_3D_ZSA | NV50_NEW_3D_BLEND |
1332 NV50_NEW_3D_TEXTURES | NV50_NEW_3D_SAMPLERS | NV50_NEW_3D_WINDOW_RECTS |
1333 NV50_NEW_3D_VERTPROG | NV50_NEW_3D_GMTYPROG | NV50_NEW_3D_FRAGPROG);
1334 nv50->scissors_dirty |= 1;
1335
1336 nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
1337 }
1338
1339
1340 static void
1341 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1342 {
1343 struct nv50_blitctx *blit = nv50->blit;
1344 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1345 struct pipe_resource *src = info->src.resource;
1346 struct pipe_resource *dst = info->dst.resource;
1347 int32_t minx, maxx, miny, maxy;
1348 int32_t i;
1349 float x0, x1, y0, y1, z;
1350 float dz;
1351 float x_range, y_range;
1352 float tri_x, tri_y;
1353
1354 blit->mode = nv50_blit_select_mode(info);
1355 blit->color_mask = nv50_blit_derive_color_mask(info);
1356 blit->filter = nv50_blit_get_filter(info);
1357 blit->render_condition_enable = info->render_condition_enable;
1358
1359 nv50_blit_select_fp(blit, info);
1360 nv50_blitctx_pre_blit(blit, info);
1361
1362 nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1363 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1364 blit->filter);
1365
1366 nv50_blitctx_prepare_state(blit);
1367
1368 nv50_state_validate_3d(nv50, ~0);
1369
1370 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1371 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1372
1373 tri_x = 16384 << nv50_miptree(dst)->ms_x;
1374 tri_y = 16384 << nv50_miptree(dst)->ms_y;
1375
1376 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1377 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1378
1379 x1 = x0 + tri_x * x_range;
1380 y1 = y0 + tri_y * y_range;
1381
1382 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1383 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1384 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1385 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1386
1387 /* XXX: multiply by 6 for cube arrays ? */
1388 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1389 z = (float)info->src.box.z;
1390 if (nv50_miptree(src)->layout_3d)
1391 z += 0.5f * dz;
1392
1393 if (src->last_level > 0) {
1394 /* If there are mip maps, GPU always assumes normalized coordinates. */
1395 const unsigned l = info->src.level;
1396 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1397 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1398 x0 /= fh;
1399 x1 /= fh;
1400 y0 /= fv;
1401 y1 /= fv;
1402 if (nv50_miptree(src)->layout_3d) {
1403 z /= u_minify(src->depth0, l);
1404 dz /= u_minify(src->depth0, l);
1405 }
1406 }
1407
1408 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1409 PUSH_DATA (push, 0);
1410 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1411 PUSH_DATA (push, 0x1);
1412
1413 /* Draw a large triangle in screen coordinates covering the whole
1414 * render target, with scissors defining the destination region.
1415 * The vertex is supplied with non-normalized texture coordinates
1416 * arranged in a way to yield the desired offset and scale.
1417 */
1418
1419 minx = info->dst.box.x;
1420 maxx = info->dst.box.x + info->dst.box.width;
1421 miny = info->dst.box.y;
1422 maxy = info->dst.box.y + info->dst.box.height;
1423 if (info->scissor_enable) {
1424 minx = MAX2(minx, info->scissor.minx);
1425 maxx = MIN2(maxx, info->scissor.maxx);
1426 miny = MAX2(miny, info->scissor.miny);
1427 maxy = MIN2(maxy, info->scissor.maxy);
1428 }
1429 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
1430 PUSH_DATA (push, (maxx << 16) | minx);
1431 PUSH_DATA (push, (maxy << 16) | miny);
1432
1433 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1434 if (info->dst.box.z + i) {
1435 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1436 PUSH_DATA (push, info->dst.box.z + i);
1437 }
1438 PUSH_SPACE(push, 32);
1439 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1440 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1441 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1442 PUSH_DATAf(push, x0);
1443 PUSH_DATAf(push, y0);
1444 PUSH_DATAf(push, z);
1445 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1446 PUSH_DATAf(push, 0.0f);
1447 PUSH_DATAf(push, 0.0f);
1448 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1449 PUSH_DATAf(push, x1);
1450 PUSH_DATAf(push, y0);
1451 PUSH_DATAf(push, z);
1452 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1453 PUSH_DATAf(push, tri_x);
1454 PUSH_DATAf(push, 0.0f);
1455 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1456 PUSH_DATAf(push, x0);
1457 PUSH_DATAf(push, y1);
1458 PUSH_DATAf(push, z);
1459 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1460 PUSH_DATAf(push, 0.0f);
1461 PUSH_DATAf(push, tri_y);
1462 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1463 PUSH_DATA (push, 0);
1464 }
1465 if (info->dst.box.z + info->dst.box.depth - 1) {
1466 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1467 PUSH_DATA (push, 0);
1468 }
1469
1470 /* re-enable normally constant state */
1471
1472 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1473 PUSH_DATA (push, 1);
1474
1475 nv50_blitctx_post_blit(blit);
1476 }
1477
1478 static void
1479 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1480 {
1481 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1482 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1483 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1484 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1485 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1486 const int32_t dz = info->dst.box.z;
1487 const int32_t sz = info->src.box.z;
1488 uint32_t dstw, dsth;
1489 int32_t dstx, dsty;
1490 int64_t srcx, srcy;
1491 int64_t du_dx, dv_dy;
1492 int i;
1493 uint32_t mode;
1494 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1495 bool b;
1496
1497 mode = nv50_blit_get_filter(info) ?
1498 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1499 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1500 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1501 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1502
1503 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1504 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1505
1506 b = info->dst.format == info->src.format;
1507 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1508 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1509
1510 if (info->scissor_enable) {
1511 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1512 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1513 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1514 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1515 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1516 PUSH_DATA (push, 1); /* enable */
1517 }
1518
1519 if (nv50->cond_query && info->render_condition_enable) {
1520 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1521 PUSH_DATA (push, nv50->cond_condmode);
1522 }
1523
1524 if (mask != 0xffffffff) {
1525 BEGIN_NV04(push, NV50_2D(ROP), 1);
1526 PUSH_DATA (push, 0xca); /* DPSDxax */
1527 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1528 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1529 BEGIN_NV04(push, NV50_2D(PATTERN_BITMAP_COLOR(0)), 4);
1530 PUSH_DATA (push, 0x00000000);
1531 PUSH_DATA (push, mask);
1532 PUSH_DATA (push, 0xffffffff);
1533 PUSH_DATA (push, 0xffffffff);
1534 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1535 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1536 } else
1537 if (info->src.format != info->dst.format) {
1538 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1539 info->src.format == PIPE_FORMAT_R16_UNORM ||
1540 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1541 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1542 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1543 BEGIN_NV04(push, NV50_2D(BETA4), 2);
1544 PUSH_DATA (push, mask);
1545 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1546 }
1547 }
1548
1549 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1550 /* ms_x is always >= ms_y */
1551 du_dx <<= src->ms_x - dst->ms_x;
1552 dv_dy <<= src->ms_y - dst->ms_y;
1553 } else {
1554 du_dx >>= dst->ms_x - src->ms_x;
1555 dv_dy >>= dst->ms_y - src->ms_y;
1556 }
1557
1558 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1559 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1560
1561 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1562 /* center src coorinates for proper MS resolve filtering */
1563 srcx += (int64_t)1 << (src->ms_x + 31);
1564 srcy += (int64_t)1 << (src->ms_y + 31);
1565 }
1566
1567 dstx = info->dst.box.x << dst->ms_x;
1568 dsty = info->dst.box.y << dst->ms_y;
1569
1570 dstw = info->dst.box.width << dst->ms_x;
1571 dsth = info->dst.box.height << dst->ms_y;
1572
1573 if (dstx < 0) {
1574 dstw += dstx;
1575 srcx -= du_dx * dstx;
1576 dstx = 0;
1577 }
1578 if (dsty < 0) {
1579 dsth += dsty;
1580 srcy -= dv_dy * dsty;
1581 dsty = 0;
1582 }
1583
1584 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1585 PUSH_DATA (push, mode);
1586 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1587 PUSH_DATA (push, dstx);
1588 PUSH_DATA (push, dsty);
1589 PUSH_DATA (push, dstw);
1590 PUSH_DATA (push, dsth);
1591 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1592 PUSH_DATA (push, du_dx);
1593 PUSH_DATA (push, du_dx >> 32);
1594 PUSH_DATA (push, dv_dy);
1595 PUSH_DATA (push, dv_dy >> 32);
1596
1597 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1598 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1599 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1600 if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1601 return;
1602
1603 for (i = 0; i < info->dst.box.depth; ++i) {
1604 if (i > 0) {
1605 /* no scaling in z-direction possible for eng2d blits */
1606 if (dst->layout_3d) {
1607 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1608 PUSH_DATA (push, info->dst.box.z + i);
1609 } else {
1610 const unsigned z = info->dst.box.z + i;
1611 const uint64_t address = dst->base.address +
1612 dst->level[info->dst.level].offset +
1613 z * dst->layer_stride;
1614 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1615 PUSH_DATAh(push, address);
1616 PUSH_DATA (push, address);
1617 }
1618 if (src->layout_3d) {
1619 /* not possible because of depth tiling */
1620 assert(0);
1621 } else {
1622 const unsigned z = info->src.box.z + i;
1623 const uint64_t address = src->base.address +
1624 src->level[info->src.level].offset +
1625 z * src->layer_stride;
1626 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1627 PUSH_DATAh(push, address);
1628 PUSH_DATA (push, address);
1629 }
1630 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1631 PUSH_DATA (push, srcy >> 32);
1632 } else {
1633 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1634 PUSH_DATA (push, srcx);
1635 PUSH_DATA (push, srcx >> 32);
1636 PUSH_DATA (push, srcy);
1637 PUSH_DATA (push, srcy >> 32);
1638 }
1639 }
1640 nv50_bufctx_fence(nv50->bufctx, false);
1641
1642 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1643
1644 if (info->scissor_enable) {
1645 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1646 PUSH_DATA (push, 0);
1647 }
1648 if (mask != 0xffffffff) {
1649 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1650 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1651 }
1652 if (nv50->cond_query && info->render_condition_enable) {
1653 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1654 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1655 }
1656 }
1657
1658 static void
1659 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1660 {
1661 struct nv50_context *nv50 = nv50_context(pipe);
1662 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1663 bool eng3d = FALSE;
1664
1665 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1666 if (!(info->mask & PIPE_MASK_ZS))
1667 return;
1668 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1669 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1670 eng3d = true;
1671 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1672 eng3d = true;
1673 } else {
1674 if (!(info->mask & PIPE_MASK_RGBA))
1675 return;
1676 if (info->mask != PIPE_MASK_RGBA)
1677 eng3d = true;
1678 }
1679
1680 if (nv50_miptree(info->src.resource)->layout_3d) {
1681 eng3d = true;
1682 } else
1683 if (info->src.box.depth != info->dst.box.depth) {
1684 eng3d = true;
1685 debug_printf("blit: cannot filter array or cube textures in z direction");
1686 }
1687
1688 if (!eng3d && info->dst.format != info->src.format) {
1689 if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1690 !nv50_2d_src_format_faithful(info->src.format)) {
1691 eng3d = true;
1692 } else
1693 if (!nv50_2d_src_format_faithful(info->src.format)) {
1694 if (!util_format_is_luminance(info->src.format)) {
1695 if (util_format_is_intensity(info->src.format))
1696 eng3d = true;
1697 else
1698 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1699 eng3d = true;
1700 else
1701 eng3d = !nv50_2d_format_supported(info->src.format);
1702 }
1703 } else
1704 if (util_format_is_luminance_alpha(info->src.format))
1705 eng3d = true;
1706 }
1707
1708 if (info->src.resource->nr_samples == 8 &&
1709 info->dst.resource->nr_samples <= 1)
1710 eng3d = true;
1711
1712 if (info->num_window_rectangles > 0 || info->window_rectangle_include)
1713 eng3d = true;
1714
1715 /* FIXME: can't make this work with eng2d anymore */
1716 if ((info->src.resource->nr_samples | 1) !=
1717 (info->dst.resource->nr_samples | 1))
1718 eng3d = true;
1719
1720 /* FIXME: find correct src coordinate adjustments */
1721 if ((info->src.box.width != info->dst.box.width &&
1722 info->src.box.width != -info->dst.box.width) ||
1723 (info->src.box.height != info->dst.box.height &&
1724 info->src.box.height != -info->dst.box.height))
1725 eng3d = true;
1726
1727 if (nv50->screen->num_occlusion_queries_active) {
1728 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1729 PUSH_DATA (push, 0);
1730 }
1731
1732 if (!eng3d)
1733 nv50_blit_eng2d(nv50, info);
1734 else
1735 nv50_blit_3d(nv50, info);
1736
1737 if (nv50->screen->num_occlusion_queries_active) {
1738 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1739 PUSH_DATA (push, 1);
1740 }
1741 }
1742
1743 static void
1744 nv50_flush_resource(struct pipe_context *ctx,
1745 struct pipe_resource *resource)
1746 {
1747 }
1748
1749 bool
1750 nv50_blitter_create(struct nv50_screen *screen)
1751 {
1752 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1753 if (!screen->blitter) {
1754 NOUVEAU_ERR("failed to allocate blitter struct\n");
1755 return false;
1756 }
1757
1758 (void) mtx_init(&screen->blitter->mutex, mtx_plain);
1759
1760 nv50_blitter_make_vp(screen->blitter);
1761 nv50_blitter_make_sampler(screen->blitter);
1762
1763 return true;
1764 }
1765
1766 void
1767 nv50_blitter_destroy(struct nv50_screen *screen)
1768 {
1769 struct nv50_blitter *blitter = screen->blitter;
1770 unsigned i, m;
1771
1772 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1773 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1774 struct nv50_program *prog = blitter->fp[i][m];
1775 if (prog) {
1776 nv50_program_destroy(NULL, prog);
1777 FREE((void *)prog->pipe.tokens);
1778 FREE(prog);
1779 }
1780 }
1781 }
1782
1783 mtx_destroy(&blitter->mutex);
1784 FREE(blitter);
1785 }
1786
1787 bool
1788 nv50_blitctx_create(struct nv50_context *nv50)
1789 {
1790 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1791 if (!nv50->blit) {
1792 NOUVEAU_ERR("failed to allocate blit context\n");
1793 return false;
1794 }
1795
1796 nv50->blit->nv50 = nv50;
1797
1798 nv50->blit->rast.pipe.half_pixel_center = 1;
1799
1800 return true;
1801 }
1802
1803 void
1804 nv50_init_surface_functions(struct nv50_context *nv50)
1805 {
1806 struct pipe_context *pipe = &nv50->base.pipe;
1807
1808 pipe->resource_copy_region = nv50_resource_copy_region;
1809 pipe->blit = nv50_blit;
1810 pipe->flush_resource = nv50_flush_resource;
1811 pipe->clear_texture = nv50_clear_texture;
1812 pipe->clear_render_target = nv50_clear_render_target;
1813 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1814 pipe->clear_buffer = nv50_clear_buffer;
1815 }