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nv50: adjust blit_3d handling of ms output textures
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "tgsi/tgsi_ureg.h"
33
34 #include "os/os_thread.h"
35
36 #include "nv50/nv50_context.h"
37 #include "nv50/nv50_resource.h"
38
39 #include "nv50/nv50_defs.xml.h"
40 #include "nv50/nv50_texture.xml.h"
41
42 /* these are used in nv50_blit.h */
43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
44 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
45 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
47 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
48
49 #define NOUVEAU_DRIVER 0x50
50 #include "nv50/nv50_blit.h"
51
52 static INLINE uint8_t
53 nv50_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal)
54 {
55 uint8_t id = nv50_format_table[format].rt;
56
57 /* Hardware values for color formats range from 0xc0 to 0xff,
58 * but the 2D engine doesn't support all of them.
59 */
60 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
61 return id;
62 assert(dst_src_equal);
63
64 switch (util_format_get_blocksize(format)) {
65 case 1:
66 return NV50_SURFACE_FORMAT_R8_UNORM;
67 case 2:
68 return NV50_SURFACE_FORMAT_R16_UNORM;
69 case 4:
70 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
71 default:
72 return 0;
73 }
74 }
75
76 static int
77 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
78 struct nv50_miptree *mt, unsigned level, unsigned layer,
79 enum pipe_format pformat, boolean dst_src_pformat_equal)
80 {
81 struct nouveau_bo *bo = mt->base.bo;
82 uint32_t width, height, depth;
83 uint32_t format;
84 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
85 uint32_t offset = mt->level[level].offset;
86
87 format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
88 if (!format) {
89 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
90 util_format_name(pformat));
91 return 1;
92 }
93
94 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
95 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
96 depth = u_minify(mt->base.base.depth0, level);
97
98 offset = mt->level[level].offset;
99 if (!mt->layout_3d) {
100 offset += mt->layer_stride * layer;
101 depth = 1;
102 layer = 0;
103 } else
104 if (!dst) {
105 offset += nv50_mt_zslice_offset(mt, level, layer);
106 layer = 0;
107 }
108
109 if (!nouveau_bo_memtype(bo)) {
110 BEGIN_NV04(push, SUBC_2D(mthd), 2);
111 PUSH_DATA (push, format);
112 PUSH_DATA (push, 1);
113 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
114 PUSH_DATA (push, mt->level[level].pitch);
115 PUSH_DATA (push, width);
116 PUSH_DATA (push, height);
117 PUSH_DATAh(push, bo->offset + offset);
118 PUSH_DATA (push, bo->offset + offset);
119 } else {
120 BEGIN_NV04(push, SUBC_2D(mthd), 5);
121 PUSH_DATA (push, format);
122 PUSH_DATA (push, 0);
123 PUSH_DATA (push, mt->level[level].tile_mode);
124 PUSH_DATA (push, depth);
125 PUSH_DATA (push, layer);
126 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
127 PUSH_DATA (push, width);
128 PUSH_DATA (push, height);
129 PUSH_DATAh(push, bo->offset + offset);
130 PUSH_DATA (push, bo->offset + offset);
131 }
132
133 #if 0
134 if (dst) {
135 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
136 PUSH_DATA (push, 0);
137 PUSH_DATA (push, 0);
138 PUSH_DATA (push, width);
139 PUSH_DATA (push, height);
140 }
141 #endif
142 return 0;
143 }
144
145 static int
146 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
147 struct nv50_miptree *dst, unsigned dst_level,
148 unsigned dx, unsigned dy, unsigned dz,
149 struct nv50_miptree *src, unsigned src_level,
150 unsigned sx, unsigned sy, unsigned sz,
151 unsigned w, unsigned h)
152 {
153 const enum pipe_format dfmt = dst->base.base.format;
154 const enum pipe_format sfmt = src->base.base.format;
155 int ret;
156 boolean eqfmt = dfmt == sfmt;
157
158 if (!PUSH_SPACE(push, 2 * 16 + 32))
159 return PIPE_ERROR;
160
161 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
162 if (ret)
163 return ret;
164
165 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
166 if (ret)
167 return ret;
168
169 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
170 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
171 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
172 PUSH_DATA (push, dx << dst->ms_x);
173 PUSH_DATA (push, dy << dst->ms_y);
174 PUSH_DATA (push, w << dst->ms_x);
175 PUSH_DATA (push, h << dst->ms_y);
176 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
177 PUSH_DATA (push, 0);
178 PUSH_DATA (push, 1);
179 PUSH_DATA (push, 0);
180 PUSH_DATA (push, 1);
181 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
182 PUSH_DATA (push, 0);
183 PUSH_DATA (push, sx << src->ms_x);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, sy << src->ms_y);
186
187 return 0;
188 }
189
190 static void
191 nv50_resource_copy_region(struct pipe_context *pipe,
192 struct pipe_resource *dst, unsigned dst_level,
193 unsigned dstx, unsigned dsty, unsigned dstz,
194 struct pipe_resource *src, unsigned src_level,
195 const struct pipe_box *src_box)
196 {
197 struct nv50_context *nv50 = nv50_context(pipe);
198 int ret;
199 boolean m2mf;
200 unsigned dst_layer = dstz, src_layer = src_box->z;
201
202 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
203 nouveau_copy_buffer(&nv50->base,
204 nv04_resource(dst), dstx,
205 nv04_resource(src), src_box->x, src_box->width);
206 return;
207 }
208
209 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
210 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
211
212 m2mf = (src->format == dst->format) ||
213 (util_format_get_blocksizebits(src->format) ==
214 util_format_get_blocksizebits(dst->format));
215
216 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
217
218 if (m2mf) {
219 struct nv50_m2mf_rect drect, srect;
220 unsigned i;
221 unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
222 unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
223
224 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
225 nv50_m2mf_rect_setup(&srect, src, src_level,
226 src_box->x, src_box->y, src_box->z);
227
228 for (i = 0; i < src_box->depth; ++i) {
229 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
230
231 if (nv50_miptree(dst)->layout_3d)
232 drect.z++;
233 else
234 drect.base += nv50_miptree(dst)->layer_stride;
235
236 if (nv50_miptree(src)->layout_3d)
237 srect.z++;
238 else
239 srect.base += nv50_miptree(src)->layer_stride;
240 }
241 return;
242 }
243
244 assert((src->format == dst->format) ||
245 (nv50_2d_src_format_faithful(src->format) &&
246 nv50_2d_dst_format_faithful(dst->format)));
247
248 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
249 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
250 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
251 nouveau_pushbuf_validate(nv50->base.pushbuf);
252
253 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
254 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
255 nv50_miptree(dst), dst_level,
256 dstx, dsty, dst_layer,
257 nv50_miptree(src), src_level,
258 src_box->x, src_box->y, src_layer,
259 src_box->width, src_box->height);
260 if (ret)
261 break;
262 }
263 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
264 }
265
266 static void
267 nv50_clear_render_target(struct pipe_context *pipe,
268 struct pipe_surface *dst,
269 const union pipe_color_union *color,
270 unsigned dstx, unsigned dsty,
271 unsigned width, unsigned height)
272 {
273 struct nv50_context *nv50 = nv50_context(pipe);
274 struct nouveau_pushbuf *push = nv50->base.pushbuf;
275 struct nv50_miptree *mt = nv50_miptree(dst->texture);
276 struct nv50_surface *sf = nv50_surface(dst);
277 struct nouveau_bo *bo = mt->base.bo;
278 unsigned z;
279
280 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
281 PUSH_DATAf(push, color->f[0]);
282 PUSH_DATAf(push, color->f[1]);
283 PUSH_DATAf(push, color->f[2]);
284 PUSH_DATAf(push, color->f[3]);
285
286 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
287 return;
288
289 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
290
291 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
292 PUSH_DATA (push, 1);
293 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
294 PUSH_DATAh(push, bo->offset + sf->offset);
295 PUSH_DATA (push, bo->offset + sf->offset);
296 PUSH_DATA (push, nv50_format_table[dst->format].rt);
297 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
298 PUSH_DATA (push, mt->layer_stride >> 2);
299 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
300 if (nouveau_bo_memtype(bo))
301 PUSH_DATA(push, sf->width);
302 else
303 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
304 PUSH_DATA (push, sf->height);
305 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
306 if (mt->layout_3d)
307 PUSH_DATA(push, NV50_3D_RT_ARRAY_MODE_MODE_3D | 512);
308 else
309 PUSH_DATA(push, 512);
310
311 if (!nouveau_bo_memtype(bo)) {
312 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
313 PUSH_DATA (push, 0);
314 }
315
316 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
317
318 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
319 PUSH_DATA (push, (width << 16) | dstx);
320 PUSH_DATA (push, (height << 16) | dsty);
321
322 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
323 for (z = 0; z < sf->depth; ++z) {
324 PUSH_DATA (push, 0x3c |
325 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
326 }
327
328 nv50->dirty |= NV50_NEW_FRAMEBUFFER;
329 }
330
331 static void
332 nv50_clear_depth_stencil(struct pipe_context *pipe,
333 struct pipe_surface *dst,
334 unsigned clear_flags,
335 double depth,
336 unsigned stencil,
337 unsigned dstx, unsigned dsty,
338 unsigned width, unsigned height)
339 {
340 struct nv50_context *nv50 = nv50_context(pipe);
341 struct nouveau_pushbuf *push = nv50->base.pushbuf;
342 struct nv50_miptree *mt = nv50_miptree(dst->texture);
343 struct nv50_surface *sf = nv50_surface(dst);
344 struct nouveau_bo *bo = mt->base.bo;
345 uint32_t mode = 0;
346 unsigned z;
347
348 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
349
350 if (clear_flags & PIPE_CLEAR_DEPTH) {
351 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
352 PUSH_DATAf(push, depth);
353 mode |= NV50_3D_CLEAR_BUFFERS_Z;
354 }
355
356 if (clear_flags & PIPE_CLEAR_STENCIL) {
357 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
358 PUSH_DATA (push, stencil & 0xff);
359 mode |= NV50_3D_CLEAR_BUFFERS_S;
360 }
361
362 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
363 return;
364
365 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
366
367 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
368 PUSH_DATAh(push, bo->offset + sf->offset);
369 PUSH_DATA (push, bo->offset + sf->offset);
370 PUSH_DATA (push, nv50_format_table[dst->format].rt);
371 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
372 PUSH_DATA (push, mt->layer_stride >> 2);
373 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
374 PUSH_DATA (push, 1);
375 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
376 PUSH_DATA (push, sf->width);
377 PUSH_DATA (push, sf->height);
378 PUSH_DATA (push, (1 << 16) | 1);
379
380 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
381 PUSH_DATA (push, 512);
382
383 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
384 PUSH_DATA (push, (width << 16) | dstx);
385 PUSH_DATA (push, (height << 16) | dsty);
386
387 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
388 for (z = 0; z < sf->depth; ++z) {
389 PUSH_DATA (push, mode |
390 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
391 }
392
393 nv50->dirty |= NV50_NEW_FRAMEBUFFER;
394 }
395
396 void
397 nv50_clear(struct pipe_context *pipe, unsigned buffers,
398 const union pipe_color_union *color,
399 double depth, unsigned stencil)
400 {
401 struct nv50_context *nv50 = nv50_context(pipe);
402 struct nouveau_pushbuf *push = nv50->base.pushbuf;
403 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
404 unsigned i, j, k;
405 uint32_t mode = 0;
406
407 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
408 if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
409 return;
410
411 /* We have to clear ALL of the layers, not up to the min number of layers
412 * of any attachment. */
413 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
414 PUSH_DATA (push, (nv50->rt_array_mode & NV50_3D_RT_ARRAY_MODE_MODE_3D) | 512);
415
416 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
417 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
418 PUSH_DATAf(push, color->f[0]);
419 PUSH_DATAf(push, color->f[1]);
420 PUSH_DATAf(push, color->f[2]);
421 PUSH_DATAf(push, color->f[3]);
422 if (buffers & PIPE_CLEAR_COLOR0)
423 mode =
424 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
425 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
426 }
427
428 if (buffers & PIPE_CLEAR_DEPTH) {
429 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
430 PUSH_DATA (push, fui(depth));
431 mode |= NV50_3D_CLEAR_BUFFERS_Z;
432 }
433
434 if (buffers & PIPE_CLEAR_STENCIL) {
435 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
436 PUSH_DATA (push, stencil & 0xff);
437 mode |= NV50_3D_CLEAR_BUFFERS_S;
438 }
439
440 if (mode) {
441 int zs_layers = 0, color0_layers = 0;
442 if (fb->cbufs[0] && (mode & 0x3c))
443 color0_layers = fb->cbufs[0]->u.tex.last_layer -
444 fb->cbufs[0]->u.tex.first_layer + 1;
445 if (fb->zsbuf && (mode & ~0x3c))
446 zs_layers = fb->zsbuf->u.tex.last_layer -
447 fb->zsbuf->u.tex.first_layer + 1;
448
449 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
450 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
451 PUSH_DATA(push, mode | (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
452 }
453 for (k = j; k < zs_layers; k++) {
454 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
455 PUSH_DATA(push, (mode & ~0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
456 }
457 for (k = j; k < color0_layers; k++) {
458 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
459 PUSH_DATA(push, (mode & 0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
460 }
461 }
462
463 for (i = 1; i < fb->nr_cbufs; i++) {
464 struct pipe_surface *sf = fb->cbufs[i];
465 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
466 continue;
467 for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
468 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
469 PUSH_DATA (push, (i << 6) | 0x3c |
470 (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
471 }
472 }
473
474 /* restore the array mode */
475 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
476 PUSH_DATA (push, nv50->rt_array_mode);
477 }
478
479
480 /* =============================== BLIT CODE ===================================
481 */
482
483 struct nv50_blitter
484 {
485 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
486 struct nv50_program vp;
487
488 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
489
490 pipe_mutex mutex;
491 };
492
493 struct nv50_blitctx
494 {
495 struct nv50_context *nv50;
496 struct nv50_program *fp;
497 uint8_t mode;
498 uint16_t color_mask;
499 uint8_t filter;
500 enum pipe_texture_target target;
501 struct {
502 struct pipe_framebuffer_state fb;
503 struct nv50_rasterizer_stateobj *rast;
504 struct nv50_program *vp;
505 struct nv50_program *gp;
506 struct nv50_program *fp;
507 unsigned num_textures[3];
508 unsigned num_samplers[3];
509 struct pipe_sampler_view *texture[2];
510 struct nv50_tsc_entry *sampler[2];
511 uint32_t dirty;
512 } saved;
513 struct nv50_rasterizer_stateobj rast;
514 };
515
516 static void
517 nv50_blitter_make_vp(struct nv50_blitter *blit)
518 {
519 static const uint32_t code[] =
520 {
521 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
522 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
523 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
524 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
525 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
526 };
527
528 blit->vp.type = PIPE_SHADER_VERTEX;
529 blit->vp.translated = TRUE;
530 blit->vp.code = (uint32_t *)code; /* const_cast */
531 blit->vp.code_size = sizeof(code);
532 blit->vp.max_gpr = 4;
533 blit->vp.max_out = 5;
534 blit->vp.out_nr = 2;
535 blit->vp.out[0].mask = 0x3;
536 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
537 blit->vp.out[1].hw = 2;
538 blit->vp.out[1].mask = 0x7;
539 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
540 blit->vp.out[1].si = 0;
541 blit->vp.vp.attrs[0] = 0x73;
542 blit->vp.vp.psiz = 0x40;
543 blit->vp.vp.edgeflag = 0x40;
544 }
545
546 void *
547 nv50_blitter_make_fp(struct pipe_context *pipe,
548 unsigned mode,
549 enum pipe_texture_target ptarg)
550 {
551 struct ureg_program *ureg;
552 struct ureg_src tc;
553 struct ureg_dst out;
554 struct ureg_dst data;
555
556 const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
557
558 boolean tex_rgbaz = FALSE;
559 boolean tex_s = FALSE;
560 boolean cvt_un8 = FALSE;
561
562 if (mode != NV50_BLIT_MODE_PASS &&
563 mode != NV50_BLIT_MODE_Z24X8 &&
564 mode != NV50_BLIT_MODE_X8Z24)
565 tex_s = TRUE;
566
567 if (mode != NV50_BLIT_MODE_X24S8 &&
568 mode != NV50_BLIT_MODE_S8X24 &&
569 mode != NV50_BLIT_MODE_XS)
570 tex_rgbaz = TRUE;
571
572 if (mode != NV50_BLIT_MODE_PASS &&
573 mode != NV50_BLIT_MODE_ZS &&
574 mode != NV50_BLIT_MODE_XS)
575 cvt_un8 = TRUE;
576
577 ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
578 if (!ureg)
579 return NULL;
580
581 out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
582 tc = ureg_DECL_fs_input(
583 ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
584
585 data = ureg_DECL_temporary(ureg);
586
587 if (tex_s) {
588 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
589 target, tc, ureg_DECL_sampler(ureg, 1));
590 ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
591 ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
592 }
593 if (tex_rgbaz) {
594 const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
595 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
596 ureg_TEX(ureg, ureg_writemask(data, mask),
597 target, tc, ureg_DECL_sampler(ureg, 0));
598 }
599
600 if (cvt_un8) {
601 struct ureg_src mask;
602 struct ureg_src scale;
603 struct ureg_dst outz;
604 struct ureg_dst outs;
605 struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
606 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
607 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
608 struct ureg_src zsrc3 = ureg_src(data);
609 struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
610 struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
611 struct ureg_src zshuf;
612
613 mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
614 scale = ureg_imm4f(ureg,
615 1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
616 (1 << 24) - 1);
617
618 if (mode == NV50_BLIT_MODE_Z24S8 ||
619 mode == NV50_BLIT_MODE_X24S8 ||
620 mode == NV50_BLIT_MODE_Z24X8) {
621 outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
622 outs = ureg_writemask(out, TGSI_WRITEMASK_W);
623 zshuf = ureg_src(data);
624 } else {
625 outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
626 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
627 zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
628 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
629 }
630
631 if (tex_s) {
632 ureg_I2F(ureg, sdst, ssrc);
633 ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
634 }
635
636 if (tex_rgbaz) {
637 ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
638 ureg_F2I(ureg, zdst, zsrc);
639 ureg_AND(ureg, zdst3, zsrc, mask);
640 ureg_I2F(ureg, zdst3, zsrc3);
641 ureg_MUL(ureg, zdst3, zsrc3, scale);
642 ureg_MOV(ureg, outz, zshuf);
643 }
644 } else {
645 unsigned mask = TGSI_WRITEMASK_XYZW;
646
647 if (mode != NV50_BLIT_MODE_PASS) {
648 mask &= ~TGSI_WRITEMASK_ZW;
649 if (!tex_s)
650 mask = TGSI_WRITEMASK_X;
651 if (!tex_rgbaz)
652 mask = TGSI_WRITEMASK_Y;
653 }
654 ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
655 }
656 ureg_END(ureg);
657
658 return ureg_create_shader_and_destroy(ureg, pipe);
659 }
660
661 static void
662 nv50_blitter_make_sampler(struct nv50_blitter *blit)
663 {
664 /* clamp to edge, min/max lod = 0, nearest filtering */
665
666 blit->sampler[0].id = -1;
667
668 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
669 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
670 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
671 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
672 blit->sampler[0].tsc[1] =
673 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
674
675 /* clamp to edge, min/max lod = 0, bilinear filtering */
676
677 blit->sampler[1].id = -1;
678
679 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
680 blit->sampler[1].tsc[1] =
681 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
682 }
683
684 unsigned
685 nv50_blit_select_mode(const struct pipe_blit_info *info)
686 {
687 const unsigned mask = info->mask;
688
689 switch (info->dst.resource->format) {
690 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
691 case PIPE_FORMAT_Z24X8_UNORM:
692 switch (mask & PIPE_MASK_ZS) {
693 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
694 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
695 default:
696 return NV50_BLIT_MODE_X24S8;
697 }
698 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
699 switch (mask & PIPE_MASK_ZS) {
700 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
701 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
702 default:
703 return NV50_BLIT_MODE_S8X24;
704 }
705 case PIPE_FORMAT_Z32_FLOAT:
706 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
707 switch (mask & PIPE_MASK_ZS) {
708 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
709 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
710 default:
711 return NV50_BLIT_MODE_XS;
712 }
713 default:
714 return NV50_BLIT_MODE_PASS;
715 }
716 }
717
718 static void
719 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
720 {
721 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
722
723 const enum pipe_texture_target ptarg =
724 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
725
726 const unsigned targ = nv50_blit_texture_type(ptarg);
727 const unsigned mode = ctx->mode;
728
729 if (!blitter->fp[targ][mode]) {
730 pipe_mutex_lock(blitter->mutex);
731 if (!blitter->fp[targ][mode])
732 blitter->fp[targ][mode] =
733 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
734 pipe_mutex_unlock(blitter->mutex);
735 }
736 ctx->fp = blitter->fp[targ][mode];
737 }
738
739 static void
740 nv50_blit_set_dst(struct nv50_blitctx *ctx,
741 struct pipe_resource *res, unsigned level, unsigned layer,
742 enum pipe_format format)
743 {
744 struct nv50_context *nv50 = ctx->nv50;
745 struct pipe_context *pipe = &nv50->base.pipe;
746 struct pipe_surface templ;
747
748 if (util_format_is_depth_or_stencil(format))
749 templ.format = nv50_blit_zeta_to_colour_format(format);
750 else
751 templ.format = format;
752
753 templ.u.tex.level = level;
754 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
755
756 if (layer == -1) {
757 templ.u.tex.first_layer = 0;
758 templ.u.tex.last_layer =
759 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
760 }
761
762 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
763 nv50->framebuffer.nr_cbufs = 1;
764 nv50->framebuffer.zsbuf = NULL;
765 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
766 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
767 }
768
769 static void
770 nv50_blit_set_src(struct nv50_blitctx *blit,
771 struct pipe_resource *res, unsigned level, unsigned layer,
772 enum pipe_format format, const uint8_t filter)
773 {
774 struct nv50_context *nv50 = blit->nv50;
775 struct pipe_context *pipe = &nv50->base.pipe;
776 struct pipe_sampler_view templ;
777 uint32_t flags;
778 enum pipe_texture_target target;
779
780 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
781
782 templ.format = format;
783 templ.u.tex.first_level = templ.u.tex.last_level = level;
784 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
785 templ.swizzle_r = PIPE_SWIZZLE_RED;
786 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
787 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
788 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
789
790 if (layer == -1) {
791 templ.u.tex.first_layer = 0;
792 templ.u.tex.last_layer =
793 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
794 }
795
796 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
797 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
798 if (filter && res->nr_samples == 8)
799 flags |= NV50_TEXVIEW_FILTER_MSAA8;
800
801 nv50->textures[2][0] = nv50_create_texture_view(
802 pipe, res, &templ, flags, target);
803 nv50->textures[2][1] = NULL;
804
805 nv50->num_textures[0] = nv50->num_textures[1] = 0;
806 nv50->num_textures[2] = 1;
807
808 templ.format = nv50_zs_to_s_format(format);
809 if (templ.format != res->format) {
810 nv50->textures[2][1] = nv50_create_texture_view(
811 pipe, res, &templ, flags, target);
812 nv50->num_textures[2] = 2;
813 }
814 }
815
816 static void
817 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
818 {
819 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
820
821 if (blit->nv50->cond_query) {
822 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
823 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
824 }
825
826 /* blend state */
827 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
828 PUSH_DATA (push, blit->color_mask);
829 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
830 PUSH_DATA (push, 0);
831 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
832 PUSH_DATA (push, 0);
833
834 /* rasterizer state */
835 #ifndef NV50_SCISSORS_CLIPPING
836 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
837 PUSH_DATA (push, 1);
838 #endif
839 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
840 PUSH_DATA (push, 0);
841 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
842 PUSH_DATA (push, 0);
843 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
844 PUSH_DATA (push, 0);
845 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
846 PUSH_DATA (push, 0xffff);
847 PUSH_DATA (push, 0xffff);
848 PUSH_DATA (push, 0xffff);
849 PUSH_DATA (push, 0xffff);
850 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
851 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
852 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
853 PUSH_DATA (push, 0);
854 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
855 PUSH_DATA (push, 0);
856 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
857 PUSH_DATA (push, 0);
858 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
859 PUSH_DATA (push, 0);
860
861 /* zsa state */
862 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
863 PUSH_DATA (push, 0);
864 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
865 PUSH_DATA (push, 0);
866 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
867 PUSH_DATA (push, 0);
868 }
869
870 static void
871 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
872 {
873 struct nv50_context *nv50 = ctx->nv50;
874 struct nv50_blitter *blitter = nv50->screen->blitter;
875 int s;
876
877 ctx->saved.fb.width = nv50->framebuffer.width;
878 ctx->saved.fb.height = nv50->framebuffer.height;
879 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
880 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
881 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
882
883 ctx->saved.rast = nv50->rast;
884
885 ctx->saved.vp = nv50->vertprog;
886 ctx->saved.gp = nv50->gmtyprog;
887 ctx->saved.fp = nv50->fragprog;
888
889 nv50->rast = &ctx->rast;
890
891 nv50->vertprog = &blitter->vp;
892 nv50->gmtyprog = NULL;
893 nv50->fragprog = ctx->fp;
894
895 for (s = 0; s < 3; ++s) {
896 ctx->saved.num_textures[s] = nv50->num_textures[s];
897 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
898 }
899 ctx->saved.texture[0] = nv50->textures[2][0];
900 ctx->saved.texture[1] = nv50->textures[2][1];
901 ctx->saved.sampler[0] = nv50->samplers[2][0];
902 ctx->saved.sampler[1] = nv50->samplers[2][1];
903
904 nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
905 nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
906
907 nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
908 nv50->num_samplers[2] = 2;
909
910 ctx->saved.dirty = nv50->dirty;
911
912 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
913 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
914
915 nv50->dirty =
916 NV50_NEW_FRAMEBUFFER |
917 NV50_NEW_VERTPROG | NV50_NEW_FRAGPROG | NV50_NEW_GMTYPROG |
918 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS;
919 }
920
921 static void
922 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
923 {
924 struct nv50_context *nv50 = blit->nv50;
925 int s;
926
927 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
928
929 nv50->framebuffer.width = blit->saved.fb.width;
930 nv50->framebuffer.height = blit->saved.fb.height;
931 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
932 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
933 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
934
935 nv50->rast = blit->saved.rast;
936
937 nv50->vertprog = blit->saved.vp;
938 nv50->gmtyprog = blit->saved.gp;
939 nv50->fragprog = blit->saved.fp;
940
941 pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
942 pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
943
944 for (s = 0; s < 3; ++s) {
945 nv50->num_textures[s] = blit->saved.num_textures[s];
946 nv50->num_samplers[s] = blit->saved.num_samplers[s];
947 }
948 nv50->textures[2][0] = blit->saved.texture[0];
949 nv50->textures[2][1] = blit->saved.texture[1];
950 nv50->samplers[2][0] = blit->saved.sampler[0];
951 nv50->samplers[2][1] = blit->saved.sampler[1];
952
953 if (nv50->cond_query)
954 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
955 nv50->cond_cond, nv50->cond_mode);
956
957 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
958 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
959
960 nv50->dirty = blit->saved.dirty |
961 (NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR | NV50_NEW_SAMPLE_MASK |
962 NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
963 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
964 NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
965 }
966
967
968 static void
969 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
970 {
971 struct nv50_blitctx *blit = nv50->blit;
972 struct nouveau_pushbuf *push = nv50->base.pushbuf;
973 struct pipe_resource *src = info->src.resource;
974 struct pipe_resource *dst = info->dst.resource;
975 int32_t minx, maxx, miny, maxy;
976 int32_t i;
977 float x0, x1, y0, y1, z;
978 float dz;
979 float x_range, y_range;
980 float tri_x, tri_y;
981
982 blit->mode = nv50_blit_select_mode(info);
983 blit->color_mask = nv50_blit_derive_color_mask(info);
984 blit->filter = nv50_blit_get_filter(info);
985
986 nv50_blit_select_fp(blit, info);
987 nv50_blitctx_pre_blit(blit);
988
989 nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
990 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
991 blit->filter);
992
993 nv50_blitctx_prepare_state(blit);
994
995 nv50_state_validate(nv50, ~0, 36);
996
997 x_range = (float)info->src.box.width / (float)info->dst.box.width;
998 y_range = (float)info->src.box.height / (float)info->dst.box.height;
999
1000 tri_x = 16384 << nv50_miptree(dst)->ms_x;
1001 tri_y = 16384 << nv50_miptree(dst)->ms_y;
1002
1003 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1004 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1005
1006 x1 = x0 + tri_x * x_range;
1007 y1 = y0 + tri_y * y_range;
1008
1009 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1010 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1011 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1012 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1013
1014 if (src->last_level > 0) {
1015 /* If there are mip maps, GPU always assumes normalized coordinates. */
1016 const unsigned l = info->src.level;
1017 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1018 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1019 x0 /= fh;
1020 x1 /= fh;
1021 y0 /= fv;
1022 y1 /= fv;
1023 }
1024
1025 /* XXX: multiply by 6 for cube arrays ? */
1026 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1027 z = (float)info->src.box.z;
1028 if (nv50_miptree(src)->layout_3d)
1029 z += 0.5f * dz;
1030
1031 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1032 PUSH_DATA (push, 0);
1033 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1034 PUSH_DATA (push, 0x1);
1035
1036 /* Draw a large triangle in screen coordinates covering the whole
1037 * render target, with scissors defining the destination region.
1038 * The vertex is supplied with non-normalized texture coordinates
1039 * arranged in a way to yield the desired offset and scale.
1040 */
1041
1042 minx = info->dst.box.x;
1043 maxx = info->dst.box.x + info->dst.box.width;
1044 miny = info->dst.box.y;
1045 maxy = info->dst.box.y + info->dst.box.height;
1046 if (info->scissor_enable) {
1047 minx = MAX2(minx, info->scissor.minx);
1048 maxx = MIN2(maxx, info->scissor.maxx);
1049 miny = MAX2(miny, info->scissor.miny);
1050 maxy = MIN2(maxy, info->scissor.maxy);
1051 }
1052 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
1053 PUSH_DATA (push, (maxx << 16) | minx);
1054 PUSH_DATA (push, (maxy << 16) | miny);
1055
1056 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1057 if (info->dst.box.z + i) {
1058 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1059 PUSH_DATA (push, info->dst.box.z + i);
1060 }
1061 PUSH_SPACE(push, 32);
1062 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1063 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1064 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1065 PUSH_DATAf(push, x0);
1066 PUSH_DATAf(push, y0);
1067 PUSH_DATAf(push, z);
1068 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1069 PUSH_DATAf(push, 0.0f);
1070 PUSH_DATAf(push, 0.0f);
1071 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1072 PUSH_DATAf(push, x1);
1073 PUSH_DATAf(push, y0);
1074 PUSH_DATAf(push, z);
1075 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1076 PUSH_DATAf(push, tri_x);
1077 PUSH_DATAf(push, 0.0f);
1078 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1079 PUSH_DATAf(push, x0);
1080 PUSH_DATAf(push, y1);
1081 PUSH_DATAf(push, z);
1082 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1083 PUSH_DATAf(push, 0.0f);
1084 PUSH_DATAf(push, tri_y);
1085 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1086 PUSH_DATA (push, 0);
1087 }
1088 if (info->dst.box.z + info->dst.box.depth - 1) {
1089 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1090 PUSH_DATA (push, 0);
1091 }
1092
1093 /* re-enable normally constant state */
1094
1095 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1096 PUSH_DATA (push, 1);
1097
1098 nv50_blitctx_post_blit(blit);
1099 }
1100
1101 static void
1102 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1103 {
1104 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1105 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1106 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1107 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1108 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1109 const int32_t dz = info->dst.box.z;
1110 const int32_t sz = info->src.box.z;
1111 uint32_t dstw, dsth;
1112 int32_t dstx, dsty;
1113 int64_t srcx, srcy;
1114 int64_t du_dx, dv_dy;
1115 int i;
1116 uint32_t mode;
1117 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1118 boolean b;
1119
1120 mode = nv50_blit_get_filter(info) ?
1121 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1122 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1123 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1124 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1125
1126 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1127 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1128
1129 b = info->dst.format == info->src.format;
1130 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1131 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1132
1133 if (info->scissor_enable) {
1134 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1135 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1136 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1137 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1138 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1139 PUSH_DATA (push, 1); /* enable */
1140 }
1141
1142 if (mask != 0xffffffff) {
1143 BEGIN_NV04(push, NV50_2D(ROP), 1);
1144 PUSH_DATA (push, 0xca); /* DPSDxax */
1145 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1146 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_32BPP);
1147 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR(0)), 4);
1148 PUSH_DATA (push, 0x00000000);
1149 PUSH_DATA (push, mask);
1150 PUSH_DATA (push, 0xffffffff);
1151 PUSH_DATA (push, 0xffffffff);
1152 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1153 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1154 } else
1155 if (info->src.format != info->dst.format) {
1156 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1157 info->src.format == PIPE_FORMAT_R16_UNORM ||
1158 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1159 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1160 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1161 BEGIN_NV04(push, NV50_2D(BETA4), 2);
1162 PUSH_DATA (push, mask);
1163 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1164 }
1165 }
1166
1167 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1168 /* ms_x is always >= ms_y */
1169 du_dx <<= src->ms_x - dst->ms_x;
1170 dv_dy <<= src->ms_y - dst->ms_y;
1171 } else {
1172 du_dx >>= dst->ms_x - src->ms_x;
1173 dv_dy >>= dst->ms_y - src->ms_y;
1174 }
1175
1176 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1177 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1178
1179 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1180 /* center src coorinates for proper MS resolve filtering */
1181 srcx += (int64_t)src->ms_x << 32;
1182 srcy += (int64_t)src->ms_y << 32;
1183 }
1184
1185 dstx = info->dst.box.x << dst->ms_x;
1186 dsty = info->dst.box.y << dst->ms_y;
1187
1188 dstw = info->dst.box.width << dst->ms_x;
1189 dsth = info->dst.box.height << dst->ms_y;
1190
1191 if (dstx < 0) {
1192 dstw += dstx;
1193 srcx -= du_dx * dstx;
1194 dstx = 0;
1195 }
1196 if (dsty < 0) {
1197 dsth += dsty;
1198 srcy -= dv_dy * dsty;
1199 dsty = 0;
1200 }
1201
1202 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1203 PUSH_DATA (push, mode);
1204 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1205 PUSH_DATA (push, dstx);
1206 PUSH_DATA (push, dsty);
1207 PUSH_DATA (push, dstw);
1208 PUSH_DATA (push, dsth);
1209 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1210 PUSH_DATA (push, du_dx);
1211 PUSH_DATA (push, du_dx >> 32);
1212 PUSH_DATA (push, dv_dy);
1213 PUSH_DATA (push, dv_dy >> 32);
1214
1215 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1216 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1217 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1218 if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1219 return;
1220
1221 for (i = 0; i < info->dst.box.depth; ++i) {
1222 if (i > 0) {
1223 /* no scaling in z-direction possible for eng2d blits */
1224 if (dst->layout_3d) {
1225 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1226 PUSH_DATA (push, info->dst.box.z + i);
1227 } else {
1228 const unsigned z = info->dst.box.z + i;
1229 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1230 PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
1231 PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
1232 }
1233 if (src->layout_3d) {
1234 /* not possible because of depth tiling */
1235 assert(0);
1236 } else {
1237 const unsigned z = info->src.box.z + i;
1238 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1239 PUSH_DATAh(push, src->base.address + z * src->layer_stride);
1240 PUSH_DATA (push, src->base.address + z * src->layer_stride);
1241 }
1242 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1243 PUSH_DATA (push, srcy >> 32);
1244 } else {
1245 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1246 PUSH_DATA (push, srcx);
1247 PUSH_DATA (push, srcx >> 32);
1248 PUSH_DATA (push, srcy);
1249 PUSH_DATA (push, srcy >> 32);
1250 }
1251 }
1252 nv50_bufctx_fence(nv50->bufctx, FALSE);
1253
1254 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1255
1256 if (info->scissor_enable) {
1257 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1258 PUSH_DATA (push, 0);
1259 }
1260 if (mask != 0xffffffff) {
1261 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1262 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1263 }
1264 }
1265
1266 static void
1267 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1268 {
1269 struct nv50_context *nv50 = nv50_context(pipe);
1270 boolean eng3d = FALSE;
1271
1272 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1273 if (!(info->mask & PIPE_MASK_ZS))
1274 return;
1275 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1276 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1277 eng3d = TRUE;
1278 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1279 eng3d = TRUE;
1280 } else {
1281 if (!(info->mask & PIPE_MASK_RGBA))
1282 return;
1283 if (info->mask != PIPE_MASK_RGBA)
1284 eng3d = TRUE;
1285 }
1286
1287 if (nv50_miptree(info->src.resource)->layout_3d) {
1288 eng3d = TRUE;
1289 } else
1290 if (info->src.box.depth != info->dst.box.depth) {
1291 eng3d = TRUE;
1292 debug_printf("blit: cannot filter array or cube textures in z direction");
1293 }
1294
1295 if (!eng3d && info->dst.format != info->src.format) {
1296 if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1297 !nv50_2d_src_format_faithful(info->src.format)) {
1298 eng3d = TRUE;
1299 } else
1300 if (!nv50_2d_src_format_faithful(info->src.format)) {
1301 if (!util_format_is_luminance(info->src.format)) {
1302 if (util_format_is_intensity(info->src.format))
1303 eng3d = TRUE;
1304 else
1305 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1306 eng3d = TRUE;
1307 else
1308 eng3d = !nv50_2d_format_supported(info->src.format);
1309 }
1310 } else
1311 if (util_format_is_luminance_alpha(info->src.format))
1312 eng3d = TRUE;
1313 }
1314
1315 if (info->src.resource->nr_samples == 8 &&
1316 info->dst.resource->nr_samples <= 1)
1317 eng3d = TRUE;
1318
1319 /* FIXME: can't make this work with eng2d anymore */
1320 if (info->src.resource->nr_samples > 1 ||
1321 info->dst.resource->nr_samples > 1)
1322 eng3d = TRUE;
1323
1324 /* FIXME: find correct src coordinate adjustments */
1325 if ((info->src.box.width != info->dst.box.width &&
1326 info->src.box.width != -info->dst.box.width) ||
1327 (info->src.box.height != info->dst.box.height &&
1328 info->src.box.height != -info->dst.box.height))
1329 eng3d = TRUE;
1330
1331 if (!eng3d)
1332 nv50_blit_eng2d(nv50, info);
1333 else
1334 nv50_blit_3d(nv50, info);
1335 }
1336
1337 static void
1338 nv50_flush_resource(struct pipe_context *ctx,
1339 struct pipe_resource *resource)
1340 {
1341 }
1342
1343 boolean
1344 nv50_blitter_create(struct nv50_screen *screen)
1345 {
1346 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1347 if (!screen->blitter) {
1348 NOUVEAU_ERR("failed to allocate blitter struct\n");
1349 return FALSE;
1350 }
1351
1352 pipe_mutex_init(screen->blitter->mutex);
1353
1354 nv50_blitter_make_vp(screen->blitter);
1355 nv50_blitter_make_sampler(screen->blitter);
1356
1357 return TRUE;
1358 }
1359
1360 void
1361 nv50_blitter_destroy(struct nv50_screen *screen)
1362 {
1363 struct nv50_blitter *blitter = screen->blitter;
1364 unsigned i, m;
1365
1366 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1367 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1368 struct nv50_program *prog = blitter->fp[i][m];
1369 if (prog) {
1370 nv50_program_destroy(NULL, prog);
1371 FREE((void *)prog->pipe.tokens);
1372 FREE(prog);
1373 }
1374 }
1375 }
1376
1377 FREE(blitter);
1378 }
1379
1380 boolean
1381 nv50_blitctx_create(struct nv50_context *nv50)
1382 {
1383 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1384 if (!nv50->blit) {
1385 NOUVEAU_ERR("failed to allocate blit context\n");
1386 return FALSE;
1387 }
1388
1389 nv50->blit->nv50 = nv50;
1390
1391 nv50->blit->rast.pipe.half_pixel_center = 1;
1392
1393 return TRUE;
1394 }
1395
1396 void
1397 nv50_init_surface_functions(struct nv50_context *nv50)
1398 {
1399 struct pipe_context *pipe = &nv50->base.pipe;
1400
1401 pipe->resource_copy_region = nv50_resource_copy_region;
1402 pipe->blit = nv50_blit;
1403 pipe->flush_resource = nv50_flush_resource;
1404 pipe->clear_render_target = nv50_clear_render_target;
1405 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1406 }