src/gallium/drivers/nouveau/nv50/nv50_surface.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <stdint.h>
  24
  25 #include "pipe/p_defines.h"
  26
  27 #include "util/u_inlines.h"
  28 #include "util/u_pack_color.h"
  29 #include "util/u_format.h"
  30 #include "util/u_surface.h"
  31
  32 #include "tgsi/tgsi_ureg.h"
  33
  34 #include "os/os_thread.h"
  35
  36 #include "nv50/nv50_context.h"
  37 #include "nv50/nv50_resource.h"
  38
  39 #include "nv50/nv50_defs.xml.h"
  40 #include "nv50/nv50_texture.xml.h"
  41
  42 /* these are used in nv50_blit.h */
  43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
  44 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
  45 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
  46 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
  47 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
  48
  49 #define NOUVEAU_DRIVER 0x50
  50 #include "nv50/nv50_blit.h"
  51
  52 static INLINE uint8_t
  53 nv50_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal)
  54 {
  55    uint8_t id = nv50_format_table[format].rt;
  56
  57    /* Hardware values for color formats range from 0xc0 to 0xff,
  58     * but the 2D engine doesn't support all of them.
  59     */
  60    if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
  61       return id;
  62    assert(dst_src_equal);
  63
  64    switch (util_format_get_blocksize(format)) {
  65    case 1:
  66       return NV50_SURFACE_FORMAT_R8_UNORM;
  67    case 2:
  68       return NV50_SURFACE_FORMAT_R16_UNORM;
  69    case 4:
  70       return NV50_SURFACE_FORMAT_BGRA8_UNORM;
  71    default:
  72       return 0;
  73    }
  74 }
  75
  76 static int
  77 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
  78                     struct nv50_miptree *mt, unsigned level, unsigned layer,
  79                     enum pipe_format pformat, boolean dst_src_pformat_equal)
  80 {
  81    struct nouveau_bo *bo = mt->base.bo;
  82    uint32_t width, height, depth;
  83    uint32_t format;
  84    uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
  85    uint32_t offset = mt->level[level].offset;
  86
  87    format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
  88    if (!format) {
  89       NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
  90                   util_format_name(pformat));
  91       return 1;
  92    }
  93
  94    width = u_minify(mt->base.base.width0, level) << mt->ms_x;
  95    height = u_minify(mt->base.base.height0, level) << mt->ms_y;
  96    depth = u_minify(mt->base.base.depth0, level);
  97
  98    offset = mt->level[level].offset;
  99    if (!mt->layout_3d) {
 100       offset += mt->layer_stride * layer;
 101       depth = 1;
 102       layer = 0;
 103    } else
 104    if (!dst) {
 105       offset += nv50_mt_zslice_offset(mt, level, layer);
 106       layer = 0;
 107    }
 108
 109    if (!nouveau_bo_memtype(bo)) {
 110       BEGIN_NV04(push, SUBC_2D(mthd), 2);
 111       PUSH_DATA (push, format);
 112       PUSH_DATA (push, 1);
 113       BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
 114       PUSH_DATA (push, mt->level[level].pitch);
 115       PUSH_DATA (push, width);
 116       PUSH_DATA (push, height);
 117       PUSH_DATAh(push, bo->offset + offset);
 118       PUSH_DATA (push, bo->offset + offset);
 119    } else {
 120       BEGIN_NV04(push, SUBC_2D(mthd), 5);
 121       PUSH_DATA (push, format);
 122       PUSH_DATA (push, 0);
 123       PUSH_DATA (push, mt->level[level].tile_mode);
 124       PUSH_DATA (push, depth);
 125       PUSH_DATA (push, layer);
 126       BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
 127       PUSH_DATA (push, width);
 128       PUSH_DATA (push, height);
 129       PUSH_DATAh(push, bo->offset + offset);
 130       PUSH_DATA (push, bo->offset + offset);
 131    }
 132
 133 #if 0
 134    if (dst) {
 135       BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
 136       PUSH_DATA (push, 0);
 137       PUSH_DATA (push, 0);
 138       PUSH_DATA (push, width);
 139       PUSH_DATA (push, height);
 140    }
 141 #endif
 142    return 0;
 143 }
 144
 145 static int
 146 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
 147                         struct nv50_miptree *dst, unsigned dst_level,
 148                         unsigned dx, unsigned dy, unsigned dz,
 149                         struct nv50_miptree *src, unsigned src_level,
 150                         unsigned sx, unsigned sy, unsigned sz,
 151                         unsigned w, unsigned h)
 152 {
 153    const enum pipe_format dfmt = dst->base.base.format;
 154    const enum pipe_format sfmt = src->base.base.format;
 155    int ret;
 156    boolean eqfmt = dfmt == sfmt;
 157
 158    if (!PUSH_SPACE(push, 2 * 16 + 32))
 159       return PIPE_ERROR;
 160
 161    ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
 162    if (ret)
 163       return ret;
 164
 165    ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
 166    if (ret)
 167       return ret;
 168
 169    BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
 170    PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
 171    BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
 172    PUSH_DATA (push, dx << dst->ms_x);
 173    PUSH_DATA (push, dy << dst->ms_y);
 174    PUSH_DATA (push, w << dst->ms_x);
 175    PUSH_DATA (push, h << dst->ms_y);
 176    BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
 177    PUSH_DATA (push, 0);
 178    PUSH_DATA (push, 1);
 179    PUSH_DATA (push, 0);
 180    PUSH_DATA (push, 1);
 181    BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
 182    PUSH_DATA (push, 0);
 183    PUSH_DATA (push, sx << src->ms_x);
 184    PUSH_DATA (push, 0);
 185    PUSH_DATA (push, sy << src->ms_y);
 186
 187    return 0;
 188 }
 189
 190 static void
 191 nv50_resource_copy_region(struct pipe_context *pipe,
 192                           struct pipe_resource *dst, unsigned dst_level,
 193                           unsigned dstx, unsigned dsty, unsigned dstz,
 194                           struct pipe_resource *src, unsigned src_level,
 195                           const struct pipe_box *src_box)
 196 {
 197    struct nv50_context *nv50 = nv50_context(pipe);
 198    int ret;
 199    boolean m2mf;
 200    unsigned dst_layer = dstz, src_layer = src_box->z;
 201
 202    if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 203       nouveau_copy_buffer(&nv50->base,
 204                           nv04_resource(dst), dstx,
 205                           nv04_resource(src), src_box->x, src_box->width);
 206       return;
 207    }
 208
 209    /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
 210    assert((src->nr_samples | 1) == (dst->nr_samples | 1));
 211
 212    m2mf = (src->format == dst->format) ||
 213       (util_format_get_blocksizebits(src->format) ==
 214        util_format_get_blocksizebits(dst->format));
 215
 216    nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 217
 218    if (m2mf) {
 219       struct nv50_m2mf_rect drect, srect;
 220       unsigned i;
 221       unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
 222       unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
 223
 224       nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
 225       nv50_m2mf_rect_setup(&srect, src, src_level,
 226                            src_box->x, src_box->y, src_box->z);
 227
 228       for (i = 0; i < src_box->depth; ++i) {
 229          nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
 230
 231          if (nv50_miptree(dst)->layout_3d)
 232             drect.z++;
 233          else
 234             drect.base += nv50_miptree(dst)->layer_stride;
 235
 236          if (nv50_miptree(src)->layout_3d)
 237             srect.z++;
 238          else
 239             srect.base += nv50_miptree(src)->layer_stride;
 240       }
 241       return;
 242    }
 243
 244    assert((src->format == dst->format) ||
 245           (nv50_2d_src_format_faithful(src->format) &&
 246            nv50_2d_dst_format_faithful(dst->format)));
 247
 248    BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
 249    BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
 250    nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
 251    nouveau_pushbuf_validate(nv50->base.pushbuf);
 252
 253    for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
 254       ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
 255                                     nv50_miptree(dst), dst_level,
 256                                     dstx, dsty, dst_layer,
 257                                     nv50_miptree(src), src_level,
 258                                     src_box->x, src_box->y, src_layer,
 259                                     src_box->width, src_box->height);
 260       if (ret)
 261          break;
 262    }
 263    nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
 264 }
 265
 266 static void
 267 nv50_clear_render_target(struct pipe_context *pipe,
 268                          struct pipe_surface *dst,
 269                          const union pipe_color_union *color,
 270                          unsigned dstx, unsigned dsty,
 271                          unsigned width, unsigned height)
 272 {
 273    struct nv50_context *nv50 = nv50_context(pipe);
 274    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 275    struct nv50_miptree *mt = nv50_miptree(dst->texture);
 276    struct nv50_surface *sf = nv50_surface(dst);
 277    struct nouveau_bo *bo = mt->base.bo;
 278    unsigned z;
 279
 280    BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
 281    PUSH_DATAf(push, color->f[0]);
 282    PUSH_DATAf(push, color->f[1]);
 283    PUSH_DATAf(push, color->f[2]);
 284    PUSH_DATAf(push, color->f[3]);
 285
 286    if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
 287       return;
 288
 289    PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
 290
 291    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 292    PUSH_DATA (push, 1);
 293    BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
 294    PUSH_DATAh(push, bo->offset + sf->offset);
 295    PUSH_DATA (push, bo->offset + sf->offset);
 296    PUSH_DATA (push, nv50_format_table[dst->format].rt);
 297    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
 298    PUSH_DATA (push, mt->layer_stride >> 2);
 299    BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
 300    if (nouveau_bo_memtype(bo))
 301       PUSH_DATA(push, sf->width);
 302    else
 303       PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
 304    PUSH_DATA (push, sf->height);
 305    BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
 306    if (mt->layout_3d)
 307       PUSH_DATA(push, NV50_3D_RT_ARRAY_MODE_MODE_3D | 512);
 308    else
 309       PUSH_DATA(push, 512);
 310
 311    if (!nouveau_bo_memtype(bo)) {
 312       BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
 313       PUSH_DATA (push, 0);
 314    }
 315
 316    /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
 317
 318    BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
 319    PUSH_DATA (push, (width << 16) | dstx);
 320    PUSH_DATA (push, (height << 16) | dsty);
 321
 322    BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
 323    for (z = 0; z < sf->depth; ++z) {
 324       PUSH_DATA (push, 0x3c |
 325                  (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
 326    }
 327
 328    nv50->dirty |= NV50_NEW_FRAMEBUFFER;
 329 }
 330
 331 static void
 332 nv50_clear_depth_stencil(struct pipe_context *pipe,
 333                          struct pipe_surface *dst,
 334                          unsigned clear_flags,
 335                          double depth,
 336                          unsigned stencil,
 337                          unsigned dstx, unsigned dsty,
 338                          unsigned width, unsigned height)
 339 {
 340    struct nv50_context *nv50 = nv50_context(pipe);
 341    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 342    struct nv50_miptree *mt = nv50_miptree(dst->texture);
 343    struct nv50_surface *sf = nv50_surface(dst);
 344    struct nouveau_bo *bo = mt->base.bo;
 345    uint32_t mode = 0;
 346    unsigned z;
 347
 348    assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
 349
 350    if (clear_flags & PIPE_CLEAR_DEPTH) {
 351       BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
 352       PUSH_DATAf(push, depth);
 353       mode |= NV50_3D_CLEAR_BUFFERS_Z;
 354    }
 355
 356    if (clear_flags & PIPE_CLEAR_STENCIL) {
 357       BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
 358       PUSH_DATA (push, stencil & 0xff);
 359       mode |= NV50_3D_CLEAR_BUFFERS_S;
 360    }
 361
 362    if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
 363       return;
 364
 365    PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
 366
 367    BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
 368    PUSH_DATAh(push, bo->offset + sf->offset);
 369    PUSH_DATA (push, bo->offset + sf->offset);
 370    PUSH_DATA (push, nv50_format_table[dst->format].rt);
 371    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
 372    PUSH_DATA (push, mt->layer_stride >> 2);
 373    BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
 374    PUSH_DATA (push, 1);
 375    BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
 376    PUSH_DATA (push, sf->width);
 377    PUSH_DATA (push, sf->height);
 378    PUSH_DATA (push, (1 << 16) | 1);
 379
 380    BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
 381    PUSH_DATA (push, 512);
 382
 383    BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
 384    PUSH_DATA (push, (width << 16) | dstx);
 385    PUSH_DATA (push, (height << 16) | dsty);
 386
 387    BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
 388    for (z = 0; z < sf->depth; ++z) {
 389       PUSH_DATA (push, mode |
 390                  (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
 391    }
 392
 393    nv50->dirty |= NV50_NEW_FRAMEBUFFER;
 394 }
 395
 396 void
 397 nv50_clear(struct pipe_context *pipe, unsigned buffers,
 398            const union pipe_color_union *color,
 399            double depth, unsigned stencil)
 400 {
 401    struct nv50_context *nv50 = nv50_context(pipe);
 402    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 403    struct pipe_framebuffer_state *fb = &nv50->framebuffer;
 404    unsigned i, j, k;
 405    uint32_t mode = 0;
 406
 407    /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
 408    if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
 409       return;
 410
 411    /* We have to clear ALL of the layers, not up to the min number of layers
 412     * of any attachment. */
 413    BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
 414    PUSH_DATA (push, (nv50->rt_array_mode & NV50_3D_RT_ARRAY_MODE_MODE_3D) | 512);
 415
 416    if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
 417       BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
 418       PUSH_DATAf(push, color->f[0]);
 419       PUSH_DATAf(push, color->f[1]);
 420       PUSH_DATAf(push, color->f[2]);
 421       PUSH_DATAf(push, color->f[3]);
 422       if (buffers & PIPE_CLEAR_COLOR0)
 423          mode =
 424             NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
 425             NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
 426    }
 427
 428    if (buffers & PIPE_CLEAR_DEPTH) {
 429       BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
 430       PUSH_DATA (push, fui(depth));
 431       mode |= NV50_3D_CLEAR_BUFFERS_Z;
 432    }
 433
 434    if (buffers & PIPE_CLEAR_STENCIL) {
 435       BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
 436       PUSH_DATA (push, stencil & 0xff);
 437       mode |= NV50_3D_CLEAR_BUFFERS_S;
 438    }
 439
 440    if (mode) {
 441       int zs_layers = 0, color0_layers = 0;
 442       if (fb->cbufs[0] && (mode & 0x3c))
 443          color0_layers = fb->cbufs[0]->u.tex.last_layer -
 444             fb->cbufs[0]->u.tex.first_layer + 1;
 445       if (fb->zsbuf && (mode & ~0x3c))
 446          zs_layers = fb->zsbuf->u.tex.last_layer -
 447             fb->zsbuf->u.tex.first_layer + 1;
 448
 449       for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
 450          BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
 451          PUSH_DATA(push, mode | (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
 452       }
 453       for (k = j; k < zs_layers; k++) {
 454          BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
 455          PUSH_DATA(push, (mode & ~0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
 456       }
 457       for (k = j; k < color0_layers; k++) {
 458          BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
 459          PUSH_DATA(push, (mode & 0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
 460       }
 461    }
 462
 463    for (i = 1; i < fb->nr_cbufs; i++) {
 464       struct pipe_surface *sf = fb->cbufs[i];
 465       if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
 466          continue;
 467       for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
 468          BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
 469          PUSH_DATA (push, (i << 6) | 0x3c |
 470                     (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
 471       }
 472    }
 473
 474    /* restore the array mode */
 475    BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
 476    PUSH_DATA (push, nv50->rt_array_mode);
 477 }
 478
 479 static void
 480 nv50_clear_buffer(struct pipe_context *pipe,
 481                   struct pipe_resource *res,
 482                   unsigned offset, unsigned size,
 483                   const void *data, int data_size)
 484 {
 485    struct nv50_context *nv50 = nv50_context(pipe);
 486    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 487    struct nv04_resource *buf = (struct nv04_resource *)res;
 488    union pipe_color_union color;
 489    enum pipe_format dst_fmt;
 490    unsigned width, height, elements;
 491
 492    assert(res->target == PIPE_BUFFER);
 493    assert(nouveau_bo_memtype(buf->bo) == 0);
 494
 495    switch (data_size) {
 496    case 16:
 497       dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
 498       memcpy(&color.ui, data, 16);
 499       break;
 500    case 8:
 501       dst_fmt = PIPE_FORMAT_R32G32_UINT;
 502       memcpy(&color.ui, data, 8);
 503       memset(&color.ui[2], 0, 8);
 504       break;
 505    case 4:
 506       dst_fmt = PIPE_FORMAT_R32_UINT;
 507       memcpy(&color.ui, data, 4);
 508       memset(&color.ui[1], 0, 12);
 509       break;
 510    case 2:
 511       dst_fmt = PIPE_FORMAT_R16_UINT;
 512       color.ui[0] = util_cpu_to_le32(
 513             util_le16_to_cpu(*(unsigned short *)data));
 514       memset(&color.ui[1], 0, 12);
 515       break;
 516    case 1:
 517       dst_fmt = PIPE_FORMAT_R8_UINT;
 518       color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
 519       memset(&color.ui[1], 0, 12);
 520       break;
 521    default:
 522       assert(!"Unsupported element size");
 523       return;
 524    }
 525
 526    assert(size % data_size == 0);
 527
 528    elements = size / data_size;
 529    height = (elements + 8191) / 8192;
 530    width = elements / height;
 531
 532    BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
 533    PUSH_DATAf(push, color.f[0]);
 534    PUSH_DATAf(push, color.f[1]);
 535    PUSH_DATAf(push, color.f[2]);
 536    PUSH_DATAf(push, color.f[3]);
 537
 538    if (nouveau_pushbuf_space(push, 32, 1, 0))
 539       return;
 540
 541    PUSH_REFN(push, buf->bo, buf->domain | NOUVEAU_BO_WR);
 542
 543    BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
 544    PUSH_DATA (push, width << 16);
 545    PUSH_DATA (push, height << 16);
 546    BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
 547    PUSH_DATA (push, 8192 << 16);
 548    PUSH_DATA (push, 8192 << 16);
 549    nv50->scissors_dirty |= 1;
 550
 551    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 552    PUSH_DATA (push, 1);
 553    BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
 554    PUSH_DATAh(push, buf->bo->offset + buf->offset + offset);
 555    PUSH_DATA (push, buf->bo->offset + buf->offset + offset);
 556    PUSH_DATA (push, nv50_format_table[dst_fmt].rt);
 557    PUSH_DATA (push, 0);
 558    PUSH_DATA (push, 0);
 559    BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
 560    PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | (width * data_size));
 561    PUSH_DATA (push, height);
 562    BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
 563    PUSH_DATA (push, 0);
 564
 565    /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
 566
 567    BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
 568    PUSH_DATA (push, (width << 16));
 569    PUSH_DATA (push, (height << 16));
 570
 571    BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
 572    PUSH_DATA (push, 0x3c);
 573
 574    if (width * height != elements) {
 575       offset += width * height * data_size;
 576       width = elements - width * height;
 577       height = 1;
 578       BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 2);
 579       PUSH_DATAh(push, buf->bo->offset + buf->offset + offset);
 580       PUSH_DATA (push, buf->bo->offset + buf->offset + offset);
 581       BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
 582       PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | (width * data_size));
 583       PUSH_DATA (push, height);
 584       BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
 585       PUSH_DATA (push, 0x3c);
 586    }
 587
 588    nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
 589    nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
 590
 591    nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
 592 }
 593
 594 /* =============================== BLIT CODE ===================================
 595  */
 596
 597 struct nv50_blitter
 598 {
 599    struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
 600    struct nv50_program vp;
 601
 602    struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
 603
 604    pipe_mutex mutex;
 605 };
 606
 607 struct nv50_blitctx
 608 {
 609    struct nv50_context *nv50;
 610    struct nv50_program *fp;
 611    uint8_t mode;
 612    uint16_t color_mask;
 613    uint8_t filter;
 614    uint8_t render_condition_enable;
 615    enum pipe_texture_target target;
 616    struct {
 617       struct pipe_framebuffer_state fb;
 618       struct nv50_rasterizer_stateobj *rast;
 619       struct nv50_program *vp;
 620       struct nv50_program *gp;
 621       struct nv50_program *fp;
 622       unsigned num_textures[3];
 623       unsigned num_samplers[3];
 624       struct pipe_sampler_view *texture[2];
 625       struct nv50_tsc_entry *sampler[2];
 626       unsigned min_samples;
 627       uint32_t dirty;
 628    } saved;
 629    struct nv50_rasterizer_stateobj rast;
 630 };
 631
 632 static void
 633 nv50_blitter_make_vp(struct nv50_blitter *blit)
 634 {
 635    static const uint32_t code[] =
 636    {
 637       0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
 638       0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
 639       0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
 640       0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
 641       0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
 642    };
 643
 644    blit->vp.type = PIPE_SHADER_VERTEX;
 645    blit->vp.translated = TRUE;
 646    blit->vp.code = (uint32_t *)code; /* const_cast */
 647    blit->vp.code_size = sizeof(code);
 648    blit->vp.max_gpr = 4;
 649    blit->vp.max_out = 5;
 650    blit->vp.out_nr = 2;
 651    blit->vp.out[0].mask = 0x3;
 652    blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
 653    blit->vp.out[1].hw = 2;
 654    blit->vp.out[1].mask = 0x7;
 655    blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
 656    blit->vp.out[1].si = 0;
 657    blit->vp.vp.attrs[0] = 0x73;
 658    blit->vp.vp.psiz = 0x40;
 659    blit->vp.vp.edgeflag = 0x40;
 660 }
 661
 662 void *
 663 nv50_blitter_make_fp(struct pipe_context *pipe,
 664                      unsigned mode,
 665                      enum pipe_texture_target ptarg)
 666 {
 667    struct ureg_program *ureg;
 668    struct ureg_src tc;
 669    struct ureg_dst out;
 670    struct ureg_dst data;
 671
 672    const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
 673
 674    boolean tex_rgbaz = FALSE;
 675    boolean tex_s = FALSE;
 676    boolean cvt_un8 = FALSE;
 677
 678    if (mode != NV50_BLIT_MODE_PASS &&
 679        mode != NV50_BLIT_MODE_Z24X8 &&
 680        mode != NV50_BLIT_MODE_X8Z24)
 681       tex_s = TRUE;
 682
 683    if (mode != NV50_BLIT_MODE_X24S8 &&
 684        mode != NV50_BLIT_MODE_S8X24 &&
 685        mode != NV50_BLIT_MODE_XS)
 686       tex_rgbaz = TRUE;
 687
 688    if (mode != NV50_BLIT_MODE_PASS &&
 689        mode != NV50_BLIT_MODE_ZS &&
 690        mode != NV50_BLIT_MODE_XS)
 691       cvt_un8 = TRUE;
 692
 693    ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
 694    if (!ureg)
 695       return NULL;
 696
 697    out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
 698    tc = ureg_DECL_fs_input(
 699       ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
 700
 701    data = ureg_DECL_temporary(ureg);
 702
 703    if (tex_s) {
 704       ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
 705                target, tc, ureg_DECL_sampler(ureg, 1));
 706       ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
 707                ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
 708    }
 709    if (tex_rgbaz) {
 710       const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
 711          TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
 712       ureg_TEX(ureg, ureg_writemask(data, mask),
 713                target, tc, ureg_DECL_sampler(ureg, 0));
 714    }
 715
 716    if (cvt_un8) {
 717       struct ureg_src mask;
 718       struct ureg_src scale;
 719       struct ureg_dst outz;
 720       struct ureg_dst outs;
 721       struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
 722       struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
 723       struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
 724       struct ureg_src zsrc3 = ureg_src(data);
 725       struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
 726       struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
 727       struct ureg_src zshuf;
 728
 729       mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
 730       scale = ureg_imm4f(ureg,
 731                          1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
 732                          (1 << 24) - 1);
 733
 734       if (mode == NV50_BLIT_MODE_Z24S8 ||
 735           mode == NV50_BLIT_MODE_X24S8 ||
 736           mode == NV50_BLIT_MODE_Z24X8) {
 737          outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
 738          outs = ureg_writemask(out, TGSI_WRITEMASK_W);
 739          zshuf = ureg_src(data);
 740       } else {
 741          outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
 742          outs = ureg_writemask(out, TGSI_WRITEMASK_X);
 743          zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
 744                               TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
 745       }
 746
 747       if (tex_s) {
 748          ureg_I2F(ureg, sdst, ssrc);
 749          ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
 750       }
 751
 752       if (tex_rgbaz) {
 753          ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
 754          ureg_F2I(ureg, zdst, zsrc);
 755          ureg_AND(ureg, zdst3, zsrc, mask);
 756          ureg_I2F(ureg, zdst3, zsrc3);
 757          ureg_MUL(ureg, zdst3, zsrc3, scale);
 758          ureg_MOV(ureg, outz, zshuf);
 759       }
 760    } else {
 761       unsigned mask = TGSI_WRITEMASK_XYZW;
 762
 763       if (mode != NV50_BLIT_MODE_PASS) {
 764          mask &= ~TGSI_WRITEMASK_ZW;
 765          if (!tex_s)
 766             mask = TGSI_WRITEMASK_X;
 767          if (!tex_rgbaz)
 768             mask = TGSI_WRITEMASK_Y;
 769       }
 770       ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
 771    }
 772    ureg_END(ureg);
 773
 774    return ureg_create_shader_and_destroy(ureg, pipe);
 775 }
 776
 777 static void
 778 nv50_blitter_make_sampler(struct nv50_blitter *blit)
 779 {
 780    /* clamp to edge, min/max lod = 0, nearest filtering */
 781
 782    blit->sampler[0].id = -1;
 783
 784    blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
 785       (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
 786       (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
 787       (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
 788    blit->sampler[0].tsc[1] =
 789       NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
 790
 791    /* clamp to edge, min/max lod = 0, bilinear filtering */
 792
 793    blit->sampler[1].id = -1;
 794
 795    blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
 796    blit->sampler[1].tsc[1] =
 797       NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
 798 }
 799
 800 unsigned
 801 nv50_blit_select_mode(const struct pipe_blit_info *info)
 802 {
 803    const unsigned mask = info->mask;
 804
 805    switch (info->dst.resource->format) {
 806    case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 807    case PIPE_FORMAT_Z24X8_UNORM:
 808       switch (mask & PIPE_MASK_ZS) {
 809       case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
 810       case PIPE_MASK_Z:  return NV50_BLIT_MODE_Z24X8;
 811       default:
 812          return NV50_BLIT_MODE_X24S8;
 813       }
 814    case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 815       switch (mask & PIPE_MASK_ZS) {
 816       case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
 817       case PIPE_MASK_Z:  return NV50_BLIT_MODE_X8Z24;
 818       default:
 819          return NV50_BLIT_MODE_S8X24;
 820       }
 821    case PIPE_FORMAT_Z32_FLOAT:
 822    case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 823       switch (mask & PIPE_MASK_ZS) {
 824       case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
 825       case PIPE_MASK_Z:  return NV50_BLIT_MODE_PASS;
 826       default:
 827          return NV50_BLIT_MODE_XS;
 828       }
 829    default:
 830       return NV50_BLIT_MODE_PASS;
 831    }
 832 }
 833
 834 static void
 835 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
 836 {
 837    struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
 838
 839    const enum pipe_texture_target ptarg =
 840       nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
 841
 842    const unsigned targ = nv50_blit_texture_type(ptarg);
 843    const unsigned mode = ctx->mode;
 844
 845    if (!blitter->fp[targ][mode]) {
 846       pipe_mutex_lock(blitter->mutex);
 847       if (!blitter->fp[targ][mode])
 848          blitter->fp[targ][mode] =
 849             nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
 850       pipe_mutex_unlock(blitter->mutex);
 851    }
 852    ctx->fp = blitter->fp[targ][mode];
 853 }
 854
 855 static void
 856 nv50_blit_set_dst(struct nv50_blitctx *ctx,
 857                   struct pipe_resource *res, unsigned level, unsigned layer,
 858                   enum pipe_format format)
 859 {
 860    struct nv50_context *nv50 = ctx->nv50;
 861    struct pipe_context *pipe = &nv50->base.pipe;
 862    struct pipe_surface templ;
 863
 864    if (util_format_is_depth_or_stencil(format))
 865       templ.format = nv50_blit_zeta_to_colour_format(format);
 866    else
 867       templ.format = format;
 868
 869    templ.u.tex.level = level;
 870    templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
 871
 872    if (layer == -1) {
 873       templ.u.tex.first_layer = 0;
 874       templ.u.tex.last_layer =
 875          (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
 876    }
 877
 878    nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
 879    nv50->framebuffer.nr_cbufs = 1;
 880    nv50->framebuffer.zsbuf = NULL;
 881    nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
 882    nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
 883 }
 884
 885 static void
 886 nv50_blit_set_src(struct nv50_blitctx *blit,
 887                   struct pipe_resource *res, unsigned level, unsigned layer,
 888                   enum pipe_format format, const uint8_t filter)
 889 {
 890    struct nv50_context *nv50 = blit->nv50;
 891    struct pipe_context *pipe = &nv50->base.pipe;
 892    struct pipe_sampler_view templ;
 893    uint32_t flags;
 894    enum pipe_texture_target target;
 895
 896    target = nv50_blit_reinterpret_pipe_texture_target(res->target);
 897
 898    templ.format = format;
 899    templ.u.tex.first_level = templ.u.tex.last_level = level;
 900    templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
 901    templ.swizzle_r = PIPE_SWIZZLE_RED;
 902    templ.swizzle_g = PIPE_SWIZZLE_GREEN;
 903    templ.swizzle_b = PIPE_SWIZZLE_BLUE;
 904    templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
 905
 906    if (layer == -1) {
 907       templ.u.tex.first_layer = 0;
 908       templ.u.tex.last_layer =
 909          (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
 910    }
 911
 912    flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
 913    flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
 914    if (filter && res->nr_samples == 8)
 915       flags |= NV50_TEXVIEW_FILTER_MSAA8;
 916
 917    nv50->textures[2][0] = nv50_create_texture_view(
 918       pipe, res, &templ, flags, target);
 919    nv50->textures[2][1] = NULL;
 920
 921    nv50->num_textures[0] = nv50->num_textures[1] = 0;
 922    nv50->num_textures[2] = 1;
 923
 924    templ.format = nv50_zs_to_s_format(format);
 925    if (templ.format != res->format) {
 926       nv50->textures[2][1] = nv50_create_texture_view(
 927          pipe, res, &templ, flags, target);
 928       nv50->num_textures[2] = 2;
 929    }
 930 }
 931
 932 static void
 933 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
 934 {
 935    struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
 936
 937    if (blit->nv50->cond_query && !blit->render_condition_enable) {
 938       BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 939       PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 940    }
 941
 942    /* blend state */
 943    BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
 944    PUSH_DATA (push, blit->color_mask);
 945    BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
 946    PUSH_DATA (push, 0);
 947    BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
 948    PUSH_DATA (push, 0);
 949
 950    /* rasterizer state */
 951 #ifndef NV50_SCISSORS_CLIPPING
 952    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
 953    PUSH_DATA (push, 1);
 954 #endif
 955    BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
 956    PUSH_DATA (push, 0);
 957    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 958    PUSH_DATA (push, 0);
 959    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 960    PUSH_DATA (push, 0);
 961    BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
 962    PUSH_DATA (push, 0xffff);
 963    PUSH_DATA (push, 0xffff);
 964    PUSH_DATA (push, 0xffff);
 965    PUSH_DATA (push, 0xffff);
 966    BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
 967    PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
 968    PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
 969    PUSH_DATA (push, 0);
 970    BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
 971    PUSH_DATA (push, 0);
 972    BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
 973    PUSH_DATA (push, 0);
 974    BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
 975    PUSH_DATA (push, 0);
 976
 977    /* zsa state */
 978    BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
 979    PUSH_DATA (push, 0);
 980    BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
 981    PUSH_DATA (push, 0);
 982    BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
 983    PUSH_DATA (push, 0);
 984 }
 985
 986 static void
 987 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
 988 {
 989    struct nv50_context *nv50 = ctx->nv50;
 990    struct nv50_blitter *blitter = nv50->screen->blitter;
 991    int s;
 992
 993    ctx->saved.fb.width = nv50->framebuffer.width;
 994    ctx->saved.fb.height = nv50->framebuffer.height;
 995    ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
 996    ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
 997    ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
 998
 999    ctx->saved.rast = nv50->rast;
1000
1001    ctx->saved.vp = nv50->vertprog;
1002    ctx->saved.gp = nv50->gmtyprog;
1003    ctx->saved.fp = nv50->fragprog;
1004
1005    ctx->saved.min_samples = nv50->min_samples;
1006
1007    nv50->rast = &ctx->rast;
1008
1009    nv50->vertprog = &blitter->vp;
1010    nv50->gmtyprog = NULL;
1011    nv50->fragprog = ctx->fp;
1012
1013    for (s = 0; s < 3; ++s) {
1014       ctx->saved.num_textures[s] = nv50->num_textures[s];
1015       ctx->saved.num_samplers[s] = nv50->num_samplers[s];
1016    }
1017    ctx->saved.texture[0] = nv50->textures[2][0];
1018    ctx->saved.texture[1] = nv50->textures[2][1];
1019    ctx->saved.sampler[0] = nv50->samplers[2][0];
1020    ctx->saved.sampler[1] = nv50->samplers[2][1];
1021
1022    nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
1023    nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
1024
1025    nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
1026    nv50->num_samplers[2] = 2;
1027
1028    nv50->min_samples = 1;
1029
1030    ctx->saved.dirty = nv50->dirty;
1031
1032    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
1033    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
1034
1035    nv50->dirty =
1036       NV50_NEW_FRAMEBUFFER | NV50_NEW_MIN_SAMPLES |
1037       NV50_NEW_VERTPROG | NV50_NEW_FRAGPROG | NV50_NEW_GMTYPROG |
1038       NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS;
1039 }
1040
1041 static void
1042 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
1043 {
1044    struct nv50_context *nv50 = blit->nv50;
1045    int s;
1046
1047    pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
1048
1049    nv50->framebuffer.width = blit->saved.fb.width;
1050    nv50->framebuffer.height = blit->saved.fb.height;
1051    nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1052    nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1053    nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1054
1055    nv50->rast = blit->saved.rast;
1056
1057    nv50->vertprog = blit->saved.vp;
1058    nv50->gmtyprog = blit->saved.gp;
1059    nv50->fragprog = blit->saved.fp;
1060
1061    nv50->min_samples = blit->saved.min_samples;
1062
1063    pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
1064    pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
1065
1066    for (s = 0; s < 3; ++s) {
1067       nv50->num_textures[s] = blit->saved.num_textures[s];
1068       nv50->num_samplers[s] = blit->saved.num_samplers[s];
1069    }
1070    nv50->textures[2][0] = blit->saved.texture[0];
1071    nv50->textures[2][1] = blit->saved.texture[1];
1072    nv50->samplers[2][0] = blit->saved.sampler[0];
1073    nv50->samplers[2][1] = blit->saved.sampler[1];
1074
1075    if (nv50->cond_query && !blit->render_condition_enable)
1076       nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
1077                                        nv50->cond_cond, nv50->cond_mode);
1078
1079    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
1080    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
1081
1082    nv50->dirty = blit->saved.dirty |
1083       (NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR | NV50_NEW_SAMPLE_MASK |
1084        NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
1085        NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
1086        NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
1087
1088    nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
1089 }
1090
1091
1092 static void
1093 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1094 {
1095    struct nv50_blitctx *blit = nv50->blit;
1096    struct nouveau_pushbuf *push = nv50->base.pushbuf;
1097    struct pipe_resource *src = info->src.resource;
1098    struct pipe_resource *dst = info->dst.resource;
1099    int32_t minx, maxx, miny, maxy;
1100    int32_t i;
1101    float x0, x1, y0, y1, z;
1102    float dz;
1103    float x_range, y_range;
1104    float tri_x, tri_y;
1105
1106    blit->mode = nv50_blit_select_mode(info);
1107    blit->color_mask = nv50_blit_derive_color_mask(info);
1108    blit->filter = nv50_blit_get_filter(info);
1109    blit->render_condition_enable = info->render_condition_enable;
1110
1111    nv50_blit_select_fp(blit, info);
1112    nv50_blitctx_pre_blit(blit);
1113
1114    nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1115    nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1116                      blit->filter);
1117
1118    nv50_blitctx_prepare_state(blit);
1119
1120    nv50_state_validate(nv50, ~0, 36);
1121
1122    x_range = (float)info->src.box.width / (float)info->dst.box.width;
1123    y_range = (float)info->src.box.height / (float)info->dst.box.height;
1124
1125    tri_x = 16384 << nv50_miptree(dst)->ms_x;
1126    tri_y = 16384 << nv50_miptree(dst)->ms_y;
1127
1128    x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1129    y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1130
1131    x1 = x0 + tri_x * x_range;
1132    y1 = y0 + tri_y * y_range;
1133
1134    x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1135    x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1136    y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1137    y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1138
1139    if (src->last_level > 0) {
1140       /* If there are mip maps, GPU always assumes normalized coordinates. */
1141       const unsigned l = info->src.level;
1142       const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1143       const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1144       x0 /= fh;
1145       x1 /= fh;
1146       y0 /= fv;
1147       y1 /= fv;
1148    }
1149
1150    /* XXX: multiply by 6 for cube arrays ? */
1151    dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1152    z = (float)info->src.box.z;
1153    if (nv50_miptree(src)->layout_3d)
1154       z += 0.5f * dz;
1155
1156    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1157    PUSH_DATA (push, 0);
1158    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1159    PUSH_DATA (push, 0x1);
1160
1161    /* Draw a large triangle in screen coordinates covering the whole
1162     * render target, with scissors defining the destination region.
1163     * The vertex is supplied with non-normalized texture coordinates
1164     * arranged in a way to yield the desired offset and scale.
1165     */
1166
1167    minx = info->dst.box.x;
1168    maxx = info->dst.box.x + info->dst.box.width;
1169    miny = info->dst.box.y;
1170    maxy = info->dst.box.y + info->dst.box.height;
1171    if (info->scissor_enable) {
1172       minx = MAX2(minx, info->scissor.minx);
1173       maxx = MIN2(maxx, info->scissor.maxx);
1174       miny = MAX2(miny, info->scissor.miny);
1175       maxy = MIN2(maxy, info->scissor.maxy);
1176    }
1177    BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
1178    PUSH_DATA (push, (maxx << 16) | minx);
1179    PUSH_DATA (push, (maxy << 16) | miny);
1180
1181    for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1182       if (info->dst.box.z + i) {
1183          BEGIN_NV04(push, NV50_3D(LAYER), 1);
1184          PUSH_DATA (push, info->dst.box.z + i);
1185       }
1186       PUSH_SPACE(push, 32);
1187       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1188       PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1189       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1190       PUSH_DATAf(push, x0);
1191       PUSH_DATAf(push, y0);
1192       PUSH_DATAf(push, z);
1193       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1194       PUSH_DATAf(push, 0.0f);
1195       PUSH_DATAf(push, 0.0f);
1196       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1197       PUSH_DATAf(push, x1);
1198       PUSH_DATAf(push, y0);
1199       PUSH_DATAf(push, z);
1200       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1201       PUSH_DATAf(push, tri_x);
1202       PUSH_DATAf(push, 0.0f);
1203       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1204       PUSH_DATAf(push, x0);
1205       PUSH_DATAf(push, y1);
1206       PUSH_DATAf(push, z);
1207       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1208       PUSH_DATAf(push, 0.0f);
1209       PUSH_DATAf(push, tri_y);
1210       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1211       PUSH_DATA (push, 0);
1212    }
1213    if (info->dst.box.z + info->dst.box.depth - 1) {
1214       BEGIN_NV04(push, NV50_3D(LAYER), 1);
1215       PUSH_DATA (push, 0);
1216    }
1217
1218    /* re-enable normally constant state */
1219
1220    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1221    PUSH_DATA (push, 1);
1222
1223    nv50_blitctx_post_blit(blit);
1224 }
1225
1226 static void
1227 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1228 {
1229    struct nouveau_pushbuf *push = nv50->base.pushbuf;
1230    struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1231    struct nv50_miptree *src = nv50_miptree(info->src.resource);
1232    const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1233    const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1234    const int32_t dz = info->dst.box.z;
1235    const int32_t sz = info->src.box.z;
1236    uint32_t dstw, dsth;
1237    int32_t dstx, dsty;
1238    int64_t srcx, srcy;
1239    int64_t du_dx, dv_dy;
1240    int i;
1241    uint32_t mode;
1242    uint32_t mask = nv50_blit_eng2d_get_mask(info);
1243    boolean b;
1244
1245    mode = nv50_blit_get_filter(info) ?
1246       NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1247       NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1248    mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1249       NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1250
1251    du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1252    dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1253
1254    b = info->dst.format == info->src.format;
1255    nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1256    nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1257
1258    if (info->scissor_enable) {
1259       BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1260       PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1261       PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1262       PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1263       PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1264       PUSH_DATA (push, 1); /* enable */
1265    }
1266
1267    if (nv50->cond_query && info->render_condition_enable) {
1268       BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1269       PUSH_DATA (push, NV50_2D_COND_MODE_RES_NON_ZERO);
1270    }
1271
1272    if (mask != 0xffffffff) {
1273       BEGIN_NV04(push, NV50_2D(ROP), 1);
1274       PUSH_DATA (push, 0xca); /* DPSDxax */
1275       BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1276       PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_32BPP);
1277       BEGIN_NV04(push, NV50_2D(PATTERN_COLOR(0)), 4);
1278       PUSH_DATA (push, 0x00000000);
1279       PUSH_DATA (push, mask);
1280       PUSH_DATA (push, 0xffffffff);
1281       PUSH_DATA (push, 0xffffffff);
1282       BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1283       PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1284    } else
1285    if (info->src.format != info->dst.format) {
1286       if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1287           info->src.format == PIPE_FORMAT_R16_UNORM ||
1288           info->src.format == PIPE_FORMAT_R16_FLOAT ||
1289           info->src.format == PIPE_FORMAT_R32_FLOAT) {
1290          mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1291          BEGIN_NV04(push, NV50_2D(BETA4), 2);
1292          PUSH_DATA (push, mask);
1293          PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1294       }
1295    }
1296
1297    if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1298       /* ms_x is always >= ms_y */
1299       du_dx <<= src->ms_x - dst->ms_x;
1300       dv_dy <<= src->ms_y - dst->ms_y;
1301    } else {
1302       du_dx >>= dst->ms_x - src->ms_x;
1303       dv_dy >>= dst->ms_y - src->ms_y;
1304    }
1305
1306    srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1307    srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1308
1309    if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1310       /* center src coorinates for proper MS resolve filtering */
1311       srcx += (int64_t)1 << (src->ms_x + 31);
1312       srcy += (int64_t)1 << (src->ms_y + 31);
1313    }
1314
1315    dstx = info->dst.box.x << dst->ms_x;
1316    dsty = info->dst.box.y << dst->ms_y;
1317
1318    dstw = info->dst.box.width << dst->ms_x;
1319    dsth = info->dst.box.height << dst->ms_y;
1320
1321    if (dstx < 0) {
1322       dstw += dstx;
1323       srcx -= du_dx * dstx;
1324       dstx = 0;
1325    }
1326    if (dsty < 0) {
1327       dsth += dsty;
1328       srcy -= dv_dy * dsty;
1329       dsty = 0;
1330    }
1331
1332    BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1333    PUSH_DATA (push, mode);
1334    BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1335    PUSH_DATA (push, dstx);
1336    PUSH_DATA (push, dsty);
1337    PUSH_DATA (push, dstw);
1338    PUSH_DATA (push, dsth);
1339    BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1340    PUSH_DATA (push, du_dx);
1341    PUSH_DATA (push, du_dx >> 32);
1342    PUSH_DATA (push, dv_dy);
1343    PUSH_DATA (push, dv_dy >> 32);
1344
1345    BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1346    BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1347    nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1348    if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1349       return;
1350
1351    for (i = 0; i < info->dst.box.depth; ++i) {
1352       if (i > 0) {
1353          /* no scaling in z-direction possible for eng2d blits */
1354          if (dst->layout_3d) {
1355             BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1356             PUSH_DATA (push, info->dst.box.z + i);
1357          } else {
1358             const unsigned z = info->dst.box.z + i;
1359             BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1360             PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
1361             PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
1362          }
1363          if (src->layout_3d) {
1364             /* not possible because of depth tiling */
1365             assert(0);
1366          } else {
1367             const unsigned z = info->src.box.z + i;
1368             BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1369             PUSH_DATAh(push, src->base.address + z * src->layer_stride);
1370             PUSH_DATA (push, src->base.address + z * src->layer_stride);
1371          }
1372          BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1373          PUSH_DATA (push, srcy >> 32);
1374       } else {
1375          BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1376          PUSH_DATA (push, srcx);
1377          PUSH_DATA (push, srcx >> 32);
1378          PUSH_DATA (push, srcy);
1379          PUSH_DATA (push, srcy >> 32);
1380       }
1381    }
1382    nv50_bufctx_fence(nv50->bufctx, FALSE);
1383
1384    nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1385
1386    if (info->scissor_enable) {
1387       BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1388       PUSH_DATA (push, 0);
1389    }
1390    if (mask != 0xffffffff) {
1391       BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1392       PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1393    }
1394    if (nv50->cond_query && info->render_condition_enable) {
1395       BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1396       PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1397    }
1398 }
1399
1400 static void
1401 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1402 {
1403    struct nv50_context *nv50 = nv50_context(pipe);
1404    boolean eng3d = FALSE;
1405
1406    if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1407       if (!(info->mask & PIPE_MASK_ZS))
1408          return;
1409       if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1410           info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1411          eng3d = TRUE;
1412       if (info->filter != PIPE_TEX_FILTER_NEAREST)
1413          eng3d = TRUE;
1414    } else {
1415       if (!(info->mask & PIPE_MASK_RGBA))
1416          return;
1417       if (info->mask != PIPE_MASK_RGBA)
1418          eng3d = TRUE;
1419    }
1420
1421    if (nv50_miptree(info->src.resource)->layout_3d) {
1422       eng3d = TRUE;
1423    } else
1424    if (info->src.box.depth != info->dst.box.depth) {
1425       eng3d = TRUE;
1426       debug_printf("blit: cannot filter array or cube textures in z direction");
1427    }
1428
1429    if (!eng3d && info->dst.format != info->src.format) {
1430       if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1431           !nv50_2d_src_format_faithful(info->src.format)) {
1432          eng3d = TRUE;
1433       } else
1434       if (!nv50_2d_src_format_faithful(info->src.format)) {
1435          if (!util_format_is_luminance(info->src.format)) {
1436             if (util_format_is_intensity(info->src.format))
1437                eng3d = TRUE;
1438             else
1439             if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1440                eng3d = TRUE;
1441             else
1442                eng3d = !nv50_2d_format_supported(info->src.format);
1443          }
1444       } else
1445       if (util_format_is_luminance_alpha(info->src.format))
1446          eng3d = TRUE;
1447    }
1448
1449    if (info->src.resource->nr_samples == 8 &&
1450        info->dst.resource->nr_samples <= 1)
1451       eng3d = TRUE;
1452
1453    /* FIXME: can't make this work with eng2d anymore */
1454    if ((info->src.resource->nr_samples | 1) !=
1455        (info->dst.resource->nr_samples | 1))
1456       eng3d = TRUE;
1457
1458    /* FIXME: find correct src coordinate adjustments */
1459    if ((info->src.box.width !=  info->dst.box.width &&
1460         info->src.box.width != -info->dst.box.width) ||
1461        (info->src.box.height !=  info->dst.box.height &&
1462         info->src.box.height != -info->dst.box.height))
1463       eng3d = TRUE;
1464
1465    if (!eng3d)
1466       nv50_blit_eng2d(nv50, info);
1467    else
1468       nv50_blit_3d(nv50, info);
1469 }
1470
1471 static void
1472 nv50_flush_resource(struct pipe_context *ctx,
1473                     struct pipe_resource *resource)
1474 {
1475 }
1476
1477 boolean
1478 nv50_blitter_create(struct nv50_screen *screen)
1479 {
1480    screen->blitter = CALLOC_STRUCT(nv50_blitter);
1481    if (!screen->blitter) {
1482       NOUVEAU_ERR("failed to allocate blitter struct\n");
1483       return FALSE;
1484    }
1485
1486    pipe_mutex_init(screen->blitter->mutex);
1487
1488    nv50_blitter_make_vp(screen->blitter);
1489    nv50_blitter_make_sampler(screen->blitter);
1490
1491    return TRUE;
1492 }
1493
1494 void
1495 nv50_blitter_destroy(struct nv50_screen *screen)
1496 {
1497    struct nv50_blitter *blitter = screen->blitter;
1498    unsigned i, m;
1499
1500    for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1501       for (m = 0; m < NV50_BLIT_MODES; ++m) {
1502          struct nv50_program *prog = blitter->fp[i][m];
1503          if (prog) {
1504             nv50_program_destroy(NULL, prog);
1505             FREE((void *)prog->pipe.tokens);
1506             FREE(prog);
1507          }
1508       }
1509    }
1510
1511    FREE(blitter);
1512 }
1513
1514 boolean
1515 nv50_blitctx_create(struct nv50_context *nv50)
1516 {
1517    nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1518    if (!nv50->blit) {
1519       NOUVEAU_ERR("failed to allocate blit context\n");
1520       return FALSE;
1521    }
1522
1523    nv50->blit->nv50 = nv50;
1524
1525    nv50->blit->rast.pipe.half_pixel_center = 1;
1526
1527    return TRUE;
1528 }
1529
1530 void
1531 nv50_init_surface_functions(struct nv50_context *nv50)
1532 {
1533    struct pipe_context *pipe = &nv50->base.pipe;
1534
1535    pipe->resource_copy_region = nv50_resource_copy_region;
1536    pipe->blit = nv50_blit;
1537    pipe->flush_resource = nv50_flush_resource;
1538    pipe->clear_render_target = nv50_clear_render_target;
1539    pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1540    pipe->clear_buffer = nv50_clear_buffer;
1541 }