projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_math.h"
31 #include "util/u_surface.h"
32
33 #include "tgsi/tgsi_ureg.h"
34
35 #include "os/os_thread.h"
36
37 #include "nv50/nv50_context.h"
38 #include "nv50/nv50_resource.h"
39
40 #include "nv50/nv50_defs.xml.h"
41 #include "nv50/nv50_texture.xml.h"
42
43 /* these are used in nv50_blit.h */
44 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
45 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
47 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
48 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
49
50 #define NOUVEAU_DRIVER 0x50
51 #include "nv50/nv50_blit.h"
52
53 static inline uint8_t
54 nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
55 {
56 uint8_t id = nv50_format_table[format].rt;
57
58 /* Hardware values for color formats range from 0xc0 to 0xff,
59 * but the 2D engine doesn't support all of them.
60 */
61 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
62 return id;
63 assert(dst_src_equal);
64
65 switch (util_format_get_blocksize(format)) {
66 case 1:
67 return NV50_SURFACE_FORMAT_R8_UNORM;
68 case 2:
69 return NV50_SURFACE_FORMAT_R16_UNORM;
70 case 4:
71 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
72 case 8:
73 return NV50_SURFACE_FORMAT_RGBA16_FLOAT;
74 case 16:
75 return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
76 default:
77 return 0;
78 }
79 }
80
81 static int
82 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
83 struct nv50_miptree *mt, unsigned level, unsigned layer,
84 enum pipe_format pformat, bool dst_src_pformat_equal)
85 {
86 struct nouveau_bo *bo = mt->base.bo;
87 uint32_t width, height, depth;
88 uint32_t format;
89 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
90 uint32_t offset = mt->level[level].offset;
91
92 format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
93 if (!format) {
94 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
95 util_format_name(pformat));
96 return 1;
97 }
98
99 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
100 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
101 depth = u_minify(mt->base.base.depth0, level);
102
103 offset = mt->level[level].offset;
104 if (!mt->layout_3d) {
105 offset += mt->layer_stride * layer;
106 depth = 1;
107 layer = 0;
108 } else
109 if (!dst) {
110 offset += nv50_mt_zslice_offset(mt, level, layer);
111 layer = 0;
112 }
113
114 if (!nouveau_bo_memtype(bo)) {
115 BEGIN_NV04(push, SUBC_2D(mthd), 2);
116 PUSH_DATA (push, format);
117 PUSH_DATA (push, 1);
118 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
119 PUSH_DATA (push, mt->level[level].pitch);
120 PUSH_DATA (push, width);
121 PUSH_DATA (push, height);
122 PUSH_DATAh(push, mt->base.address + offset);
123 PUSH_DATA (push, mt->base.address + offset);
124 } else {
125 BEGIN_NV04(push, SUBC_2D(mthd), 5);
126 PUSH_DATA (push, format);
127 PUSH_DATA (push, 0);
128 PUSH_DATA (push, mt->level[level].tile_mode);
129 PUSH_DATA (push, depth);
130 PUSH_DATA (push, layer);
131 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
132 PUSH_DATA (push, width);
133 PUSH_DATA (push, height);
134 PUSH_DATAh(push, mt->base.address + offset);
135 PUSH_DATA (push, mt->base.address + offset);
136 }
137
138 #if 0
139 if (dst) {
140 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
141 PUSH_DATA (push, 0);
142 PUSH_DATA (push, 0);
143 PUSH_DATA (push, width);
144 PUSH_DATA (push, height);
145 }
146 #endif
147 return 0;
148 }
149
150 static int
151 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
152 struct nv50_miptree *dst, unsigned dst_level,
153 unsigned dx, unsigned dy, unsigned dz,
154 struct nv50_miptree *src, unsigned src_level,
155 unsigned sx, unsigned sy, unsigned sz,
156 unsigned w, unsigned h)
157 {
158 const enum pipe_format dfmt = dst->base.base.format;
159 const enum pipe_format sfmt = src->base.base.format;
160 int ret;
161 bool eqfmt = dfmt == sfmt;
162
163 if (!PUSH_SPACE(push, 2 * 16 + 32))
164 return PIPE_ERROR;
165
166 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
167 if (ret)
168 return ret;
169
170 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
171 if (ret)
172 return ret;
173
174 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
175 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
176 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
177 PUSH_DATA (push, dx << dst->ms_x);
178 PUSH_DATA (push, dy << dst->ms_y);
179 PUSH_DATA (push, w << dst->ms_x);
180 PUSH_DATA (push, h << dst->ms_y);
181 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
182 PUSH_DATA (push, 0);
183 PUSH_DATA (push, 1);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, 1);
186 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
187 PUSH_DATA (push, 0);
188 PUSH_DATA (push, sx << src->ms_x);
189 PUSH_DATA (push, 0);
190 PUSH_DATA (push, sy << src->ms_y);
191
192 return 0;
193 }
194
195 static void
196 nv50_resource_copy_region(struct pipe_context *pipe,
197 struct pipe_resource *dst, unsigned dst_level,
198 unsigned dstx, unsigned dsty, unsigned dstz,
199 struct pipe_resource *src, unsigned src_level,
200 const struct pipe_box *src_box)
201 {
202 struct nv50_context *nv50 = nv50_context(pipe);
203 int ret;
204 bool m2mf;
205 unsigned dst_layer = dstz, src_layer = src_box->z;
206
207 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
208 nouveau_copy_buffer(&nv50->base,
209 nv04_resource(dst), dstx,
210 nv04_resource(src), src_box->x, src_box->width);
211 return;
212 }
213
214 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
215 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
216
217 m2mf = (src->format == dst->format) ||
218 (util_format_get_blocksizebits(src->format) ==
219 util_format_get_blocksizebits(dst->format));
220
221 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
222
223 if (m2mf) {
224 struct nv50_miptree *src_mt = nv50_miptree(src);
225 struct nv50_miptree *dst_mt = nv50_miptree(dst);
226 struct nv50_m2mf_rect drect, srect;
227 unsigned i;
228 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
229 << src_mt->ms_x;
230 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
231 << src_mt->ms_y;
232
233 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
234 nv50_m2mf_rect_setup(&srect, src, src_level,
235 src_box->x, src_box->y, src_box->z);
236
237 for (i = 0; i < src_box->depth; ++i) {
238 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
239
240 if (dst_mt->layout_3d)
241 drect.z++;
242 else
243 drect.base += dst_mt->layer_stride;
244
245 if (src_mt->layout_3d)
246 srect.z++;
247 else
248 srect.base += src_mt->layer_stride;
249 }
250 return;
251 }
252
253 assert((src->format == dst->format) ||
254 (nv50_2d_src_format_faithful(src->format) &&
255 nv50_2d_dst_format_faithful(dst->format)));
256
257 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
258 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
259 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
260 nouveau_pushbuf_validate(nv50->base.pushbuf);
261
262 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
263 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
264 nv50_miptree(dst), dst_level,
265 dstx, dsty, dst_layer,
266 nv50_miptree(src), src_level,
267 src_box->x, src_box->y, src_layer,
268 src_box->width, src_box->height);
269 if (ret)
270 break;
271 }
272 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
273 }
274
275 static void
276 nv50_clear_render_target(struct pipe_context *pipe,
277 struct pipe_surface *dst,
278 const union pipe_color_union *color,
279 unsigned dstx, unsigned dsty,
280 unsigned width, unsigned height)
281 {
282 struct nv50_context *nv50 = nv50_context(pipe);
283 struct nouveau_pushbuf *push = nv50->base.pushbuf;
284 struct nv50_miptree *mt = nv50_miptree(dst->texture);
285 struct nv50_surface *sf = nv50_surface(dst);
286 struct nouveau_bo *bo = mt->base.bo;
287 unsigned z;
288
289 assert(dst->texture->target != PIPE_BUFFER);
290
291 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
292 PUSH_DATAf(push, color->f[0]);
293 PUSH_DATAf(push, color->f[1]);
294 PUSH_DATAf(push, color->f[2]);
295 PUSH_DATAf(push, color->f[3]);
296
297 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
298 return;
299
300 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
301
302 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
303 PUSH_DATA (push, ( width << 16) | dstx);
304 PUSH_DATA (push, (height << 16) | dsty);
305 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
306 PUSH_DATA (push, 8192 << 16);
307 PUSH_DATA (push, 8192 << 16);
308 nv50->scissors_dirty |= 1;
309
310 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
311 PUSH_DATA (push, 1);
312 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
313 PUSH_DATAh(push, mt->base.address + sf->offset);
314 PUSH_DATA (push, mt->base.address + sf->offset);
315 PUSH_DATA (push, nv50_format_table[dst->format].rt);
316 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
317 PUSH_DATA (push, mt->layer_stride >> 2);
318 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
319 if (nouveau_bo_memtype(bo))
320 PUSH_DATA(push, sf->width);
321 else
322 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
323 PUSH_DATA (push, sf->height);
324 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
325 if (mt->layout_3d)
326 PUSH_DATA(push, NV50_3D_RT_ARRAY_MODE_MODE_3D | 512);
327 else
328 PUSH_DATA(push, 512);
329
330 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
331 PUSH_DATA (push, mt->ms_mode);
332
333 if (!nouveau_bo_memtype(bo)) {
334 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
335 PUSH_DATA (push, 0);
336 }
337
338 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
339
340 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
341 PUSH_DATA (push, (width << 16) | dstx);
342 PUSH_DATA (push, (height << 16) | dsty);
343
344 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
345 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
346
347 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
348 for (z = 0; z < sf->depth; ++z) {
349 PUSH_DATA (push, 0x3c |
350 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
351 }
352
353 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
354 PUSH_DATA (push, nv50->cond_condmode);
355
356 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
357 }
358
359 static void
360 nv50_clear_depth_stencil(struct pipe_context *pipe,
361 struct pipe_surface *dst,
362 unsigned clear_flags,
363 double depth,
364 unsigned stencil,
365 unsigned dstx, unsigned dsty,
366 unsigned width, unsigned height)
367 {
368 struct nv50_context *nv50 = nv50_context(pipe);
369 struct nouveau_pushbuf *push = nv50->base.pushbuf;
370 struct nv50_miptree *mt = nv50_miptree(dst->texture);
371 struct nv50_surface *sf = nv50_surface(dst);
372 struct nouveau_bo *bo = mt->base.bo;
373 uint32_t mode = 0;
374 unsigned z;
375
376 assert(dst->texture->target != PIPE_BUFFER);
377 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
378
379 if (clear_flags & PIPE_CLEAR_DEPTH) {
380 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
381 PUSH_DATAf(push, depth);
382 mode |= NV50_3D_CLEAR_BUFFERS_Z;
383 }
384
385 if (clear_flags & PIPE_CLEAR_STENCIL) {
386 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
387 PUSH_DATA (push, stencil & 0xff);
388 mode |= NV50_3D_CLEAR_BUFFERS_S;
389 }
390
391 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
392 return;
393
394 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
395
396 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
397 PUSH_DATA (push, ( width << 16) | dstx);
398 PUSH_DATA (push, (height << 16) | dsty);
399 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
400 PUSH_DATA (push, 8192 << 16);
401 PUSH_DATA (push, 8192 << 16);
402 nv50->scissors_dirty |= 1;
403
404 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
405 PUSH_DATAh(push, mt->base.address + sf->offset);
406 PUSH_DATA (push, mt->base.address + sf->offset);
407 PUSH_DATA (push, nv50_format_table[dst->format].rt);
408 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
409 PUSH_DATA (push, mt->layer_stride >> 2);
410 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
411 PUSH_DATA (push, 1);
412 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
413 PUSH_DATA (push, sf->width);
414 PUSH_DATA (push, sf->height);
415 PUSH_DATA (push, (1 << 16) | 1);
416
417 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
418 PUSH_DATA (push, 512);
419
420 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
421 PUSH_DATA (push, mt->ms_mode);
422
423 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
424 PUSH_DATA (push, (width << 16) | dstx);
425 PUSH_DATA (push, (height << 16) | dsty);
426
427 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
428 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
429
430 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
431 for (z = 0; z < sf->depth; ++z) {
432 PUSH_DATA (push, mode |
433 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
434 }
435
436 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
437 PUSH_DATA (push, nv50->cond_condmode);
438
439 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
440 }
441
442 void
443 nv50_clear_texture(struct pipe_context *pipe,
444 struct pipe_resource *res,
445 unsigned level,
446 const struct pipe_box *box,
447 const void *data)
448 {
449 struct pipe_surface tmpl = {{0}}, *sf;
450
451 tmpl.format = res->format;
452 tmpl.u.tex.first_layer = box->z;
453 tmpl.u.tex.last_layer = box->z + box->depth - 1;
454 tmpl.u.tex.level = level;
455 sf = pipe->create_surface(pipe, res, &tmpl);
456 if (!sf)
457 return;
458
459 if (util_format_is_depth_or_stencil(res->format)) {
460 float depth = 0;
461 uint8_t stencil = 0;
462 unsigned clear = 0;
463 const struct util_format_description *desc =
464 util_format_description(res->format);
465
466 if (util_format_has_depth(desc)) {
467 clear |= PIPE_CLEAR_DEPTH;
468 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
469 }
470 if (util_format_has_stencil(desc)) {
471 clear |= PIPE_CLEAR_STENCIL;
472 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
473 }
474 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
475 box->x, box->y, box->width, box->height);
476 } else {
477 union pipe_color_union color;
478
479 switch (util_format_get_blocksizebits(res->format)) {
480 case 128:
481 sf->format = PIPE_FORMAT_R32G32B32A32_UINT;
482 memcpy(&color.ui, data, 128 / 8);
483 break;
484 case 64:
485 sf->format = PIPE_FORMAT_R32G32_UINT;
486 memcpy(&color.ui, data, 64 / 8);
487 memset(&color.ui[2], 0, 64 / 8);
488 break;
489 case 32:
490 sf->format = PIPE_FORMAT_R32_UINT;
491 memcpy(&color.ui, data, 32 / 8);
492 memset(&color.ui[1], 0, 96 / 8);
493 break;
494 case 16:
495 sf->format = PIPE_FORMAT_R16_UINT;
496 color.ui[0] = util_cpu_to_le32(
497 util_le16_to_cpu(*(unsigned short *)data));
498 memset(&color.ui[1], 0, 96 / 8);
499 break;
500 case 8:
501 sf->format = PIPE_FORMAT_R8_UINT;
502 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
503 memset(&color.ui[1], 0, 96 / 8);
504 break;
505 default:
506 assert(!"Unknown texel element size");
507 return;
508 }
509
510 pipe->clear_render_target(pipe, sf, &color,
511 box->x, box->y, box->width, box->height);
512 }
513 pipe->surface_destroy(pipe, sf);
514 }
515
516 void
517 nv50_clear(struct pipe_context *pipe, unsigned buffers,
518 const union pipe_color_union *color,
519 double depth, unsigned stencil)
520 {
521 struct nv50_context *nv50 = nv50_context(pipe);
522 struct nouveau_pushbuf *push = nv50->base.pushbuf;
523 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
524 unsigned i, j, k;
525 uint32_t mode = 0;
526
527 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
528 if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
529 return;
530
531 /* We have to clear ALL of the layers, not up to the min number of layers
532 * of any attachment. */
533 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
534 PUSH_DATA (push, (nv50->rt_array_mode & NV50_3D_RT_ARRAY_MODE_MODE_3D) | 512);
535
536 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
537 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
538 PUSH_DATAf(push, color->f[0]);
539 PUSH_DATAf(push, color->f[1]);
540 PUSH_DATAf(push, color->f[2]);
541 PUSH_DATAf(push, color->f[3]);
542 if (buffers & PIPE_CLEAR_COLOR0)
543 mode =
544 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
545 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
546 }
547
548 if (buffers & PIPE_CLEAR_DEPTH) {
549 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
550 PUSH_DATA (push, fui(depth));
551 mode |= NV50_3D_CLEAR_BUFFERS_Z;
552 }
553
554 if (buffers & PIPE_CLEAR_STENCIL) {
555 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
556 PUSH_DATA (push, stencil & 0xff);
557 mode |= NV50_3D_CLEAR_BUFFERS_S;
558 }
559
560 if (mode) {
561 int zs_layers = 0, color0_layers = 0;
562 if (fb->cbufs[0] && (mode & 0x3c))
563 color0_layers = nv50_surface(fb->cbufs[0])->depth;
564 if (fb->zsbuf && (mode & ~0x3c))
565 zs_layers = nv50_surface(fb->zsbuf)->depth;
566
567 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
568 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
569 PUSH_DATA(push, mode | (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
570 }
571 for (k = j; k < zs_layers; k++) {
572 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
573 PUSH_DATA(push, (mode & ~0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
574 }
575 for (k = j; k < color0_layers; k++) {
576 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
577 PUSH_DATA(push, (mode & 0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
578 }
579 }
580
581 for (i = 1; i < fb->nr_cbufs; i++) {
582 struct pipe_surface *sf = fb->cbufs[i];
583 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
584 continue;
585 for (j = 0; j < nv50_surface(sf)->depth; j++) {
586 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
587 PUSH_DATA (push, (i << 6) | 0x3c |
588 (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
589 }
590 }
591
592 /* restore the array mode */
593 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
594 PUSH_DATA (push, nv50->rt_array_mode);
595 }
596
597 static void
598 nv50_clear_buffer_push(struct pipe_context *pipe,
599 struct pipe_resource *res,
600 unsigned offset, unsigned size,
601 const void *data, int data_size)
602 {
603 struct nv50_context *nv50 = nv50_context(pipe);
604 struct nouveau_pushbuf *push = nv50->base.pushbuf;
605 struct nv04_resource *buf = nv04_resource(res);
606 unsigned count = (size + 3) / 4;
607 unsigned xcoord = offset & 0xff;
608 unsigned tmp, i;
609
610 if (data_size == 1) {
611 tmp = *(unsigned char *)data;
612 tmp = (tmp << 24) | (tmp << 16) | (tmp << 8) | tmp;
613 data = &tmp;
614 data_size = 4;
615 } else if (data_size == 2) {
616 tmp = *(unsigned short *)data;
617 tmp = (tmp << 16) | tmp;
618 data = &tmp;
619 data_size = 4;
620 }
621
622 unsigned data_words = data_size / 4;
623
624 nouveau_bufctx_refn(nv50->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
625 nouveau_pushbuf_bufctx(push, nv50->bufctx);
626 nouveau_pushbuf_validate(push);
627
628 offset &= ~0xff;
629
630 BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
631 PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
632 PUSH_DATA (push, 1);
633 BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
634 PUSH_DATA (push, 262144);
635 PUSH_DATA (push, 65536);
636 PUSH_DATA (push, 1);
637 PUSH_DATAh(push, buf->address + offset);
638 PUSH_DATA (push, buf->address + offset);
639 BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
640 PUSH_DATA (push, 0);
641 PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
642 BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
643 PUSH_DATA (push, size);
644 PUSH_DATA (push, 1);
645 PUSH_DATA (push, 0);
646 PUSH_DATA (push, 1);
647 PUSH_DATA (push, 0);
648 PUSH_DATA (push, 1);
649 PUSH_DATA (push, 0);
650 PUSH_DATA (push, xcoord);
651 PUSH_DATA (push, 0);
652 PUSH_DATA (push, 0);
653
654 while (count) {
655 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
656 unsigned nr = nr_data * data_words;
657
658 BEGIN_NI04(push, NV50_2D(SIFC_DATA), nr);
659 for (i = 0; i < nr_data; i++)
660 PUSH_DATAp(push, data, data_words);
661
662 count -= nr;
663 }
664
665 if (buf->mm) {
666 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
667 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
668 }
669
670 nouveau_bufctx_reset(nv50->bufctx, 0);
671 }
672
673 static void
674 nv50_clear_buffer(struct pipe_context *pipe,
675 struct pipe_resource *res,
676 unsigned offset, unsigned size,
677 const void *data, int data_size)
678 {
679 struct nv50_context *nv50 = nv50_context(pipe);
680 struct nouveau_pushbuf *push = nv50->base.pushbuf;
681 struct nv04_resource *buf = (struct nv04_resource *)res;
682 union pipe_color_union color;
683 enum pipe_format dst_fmt;
684 unsigned width, height, elements;
685
686 assert(res->target == PIPE_BUFFER);
687 assert(nouveau_bo_memtype(buf->bo) == 0);
688
689 switch (data_size) {
690 case 16:
691 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
692 memcpy(&color.ui, data, 16);
693 break;
694 case 8:
695 dst_fmt = PIPE_FORMAT_R32G32_UINT;
696 memcpy(&color.ui, data, 8);
697 memset(&color.ui[2], 0, 8);
698 break;
699 case 4:
700 dst_fmt = PIPE_FORMAT_R32_UINT;
701 memcpy(&color.ui, data, 4);
702 memset(&color.ui[1], 0, 12);
703 break;
704 case 2:
705 dst_fmt = PIPE_FORMAT_R16_UINT;
706 color.ui[0] = util_cpu_to_le32(
707 util_le16_to_cpu(*(unsigned short *)data));
708 memset(&color.ui[1], 0, 12);
709 break;
710 case 1:
711 dst_fmt = PIPE_FORMAT_R8_UINT;
712 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
713 memset(&color.ui[1], 0, 12);
714 break;
715 default:
716 assert(!"Unsupported element size");
717 return;
718 }
719
720 assert(size % data_size == 0);
721
722 if (offset & 0xff) {
723 unsigned fixup_size = MIN2(size, align(offset, 0x100) - offset);
724 assert(fixup_size % data_size == 0);
725 nv50_clear_buffer_push(pipe, res, offset, fixup_size, data, data_size);
726 offset += fixup_size;
727 size -= fixup_size;
728 if (!size)
729 return;
730 }
731
732 elements = size / data_size;
733 height = (elements + 8191) / 8192;
734 width = elements / height;
735 if (height > 1)
736 width &= ~0xff;
737 assert(width > 0);
738
739 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
740 PUSH_DATAf(push, color.f[0]);
741 PUSH_DATAf(push, color.f[1]);
742 PUSH_DATAf(push, color.f[2]);
743 PUSH_DATAf(push, color.f[3]);
744
745 if (nouveau_pushbuf_space(push, 32, 1, 0))
746 return;
747
748 PUSH_REFN(push, buf->bo, buf->domain | NOUVEAU_BO_WR);
749
750 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
751 PUSH_DATA (push, width << 16);
752 PUSH_DATA (push, height << 16);
753 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
754 PUSH_DATA (push, 8192 << 16);
755 PUSH_DATA (push, 8192 << 16);
756 nv50->scissors_dirty |= 1;
757
758 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
759 PUSH_DATA (push, 1);
760 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
761 PUSH_DATAh(push, buf->address + offset);
762 PUSH_DATA (push, buf->address + offset);
763 PUSH_DATA (push, nv50_format_table[dst_fmt].rt);
764 PUSH_DATA (push, 0);
765 PUSH_DATA (push, 0);
766 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
767 PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | align(width * data_size, 0x100));
768 PUSH_DATA (push, height);
769 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
770 PUSH_DATA (push, 0);
771 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
772 PUSH_DATA (push, 0);
773
774 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
775
776 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
777 PUSH_DATA (push, (width << 16));
778 PUSH_DATA (push, (height << 16));
779
780 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
781 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
782
783 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
784 PUSH_DATA (push, 0x3c);
785
786 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
787 PUSH_DATA (push, nv50->cond_condmode);
788
789 if (buf->mm) {
790 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
791 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
792 }
793
794 if (width * height != elements) {
795 offset += width * height * data_size;
796 width = elements - width * height;
797 nv50_clear_buffer_push(pipe, res, offset, width * data_size,
798 data, data_size);
799 }
800
801 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
802 }
803
804 /* =============================== BLIT CODE ===================================
805 */
806
807 struct nv50_blitter
808 {
809 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
810 struct nv50_program vp;
811
812 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
813
814 pipe_mutex mutex;
815 };
816
817 struct nv50_blitctx
818 {
819 struct nv50_context *nv50;
820 struct nv50_program *fp;
821 uint8_t mode;
822 uint16_t color_mask;
823 uint8_t filter;
824 uint8_t render_condition_enable;
825 enum pipe_texture_target target;
826 struct {
827 struct pipe_framebuffer_state fb;
828 struct nv50_rasterizer_stateobj *rast;
829 struct nv50_program *vp;
830 struct nv50_program *gp;
831 struct nv50_program *fp;
832 unsigned num_textures[3];
833 unsigned num_samplers[3];
834 struct pipe_sampler_view *texture[2];
835 struct nv50_tsc_entry *sampler[2];
836 unsigned min_samples;
837 uint32_t dirty;
838 } saved;
839 struct nv50_rasterizer_stateobj rast;
840 };
841
842 static void
843 nv50_blitter_make_vp(struct nv50_blitter *blit)
844 {
845 static const uint32_t code[] =
846 {
847 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
848 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
849 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
850 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
851 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
852 };
853
854 blit->vp.type = PIPE_SHADER_VERTEX;
855 blit->vp.translated = true;
856 blit->vp.code = (uint32_t *)code; /* const_cast */
857 blit->vp.code_size = sizeof(code);
858 blit->vp.max_gpr = 4;
859 blit->vp.max_out = 5;
860 blit->vp.out_nr = 2;
861 blit->vp.out[0].mask = 0x3;
862 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
863 blit->vp.out[1].hw = 2;
864 blit->vp.out[1].mask = 0x7;
865 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
866 blit->vp.out[1].si = 0;
867 blit->vp.vp.attrs[0] = 0x73;
868 blit->vp.vp.psiz = 0x40;
869 blit->vp.vp.edgeflag = 0x40;
870 }
871
872 void *
873 nv50_blitter_make_fp(struct pipe_context *pipe,
874 unsigned mode,
875 enum pipe_texture_target ptarg)
876 {
877 struct ureg_program *ureg;
878 struct ureg_src tc;
879 struct ureg_dst out;
880 struct ureg_dst data;
881
882 const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
883
884 bool tex_rgbaz = false;
885 bool tex_s = false;
886 bool cvt_un8 = false;
887
888 if (mode != NV50_BLIT_MODE_PASS &&
889 mode != NV50_BLIT_MODE_Z24X8 &&
890 mode != NV50_BLIT_MODE_X8Z24)
891 tex_s = true;
892
893 if (mode != NV50_BLIT_MODE_X24S8 &&
894 mode != NV50_BLIT_MODE_S8X24 &&
895 mode != NV50_BLIT_MODE_XS)
896 tex_rgbaz = true;
897
898 if (mode != NV50_BLIT_MODE_PASS &&
899 mode != NV50_BLIT_MODE_ZS &&
900 mode != NV50_BLIT_MODE_XS)
901 cvt_un8 = true;
902
903 ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
904 if (!ureg)
905 return NULL;
906
907 out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
908 tc = ureg_DECL_fs_input(
909 ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
910
911 if (ptarg == PIPE_TEXTURE_1D_ARRAY) {
912 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
913 tc = ureg_swizzle(tc, TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
914 TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Z);
915 }
916
917 data = ureg_DECL_temporary(ureg);
918
919 if (tex_s) {
920 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
921 target, tc, ureg_DECL_sampler(ureg, 1));
922 ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
923 ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
924 }
925 if (tex_rgbaz) {
926 const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
927 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
928 ureg_TEX(ureg, ureg_writemask(data, mask),
929 target, tc, ureg_DECL_sampler(ureg, 0));
930 }
931
932 if (cvt_un8) {
933 struct ureg_src mask;
934 struct ureg_src scale;
935 struct ureg_dst outz;
936 struct ureg_dst outs;
937 struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
938 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
939 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
940 struct ureg_src zsrc3 = ureg_src(data);
941 struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
942 struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
943 struct ureg_src zshuf;
944
945 mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
946 scale = ureg_imm4f(ureg,
947 1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
948 (1 << 24) - 1);
949
950 if (mode == NV50_BLIT_MODE_Z24S8 ||
951 mode == NV50_BLIT_MODE_X24S8 ||
952 mode == NV50_BLIT_MODE_Z24X8) {
953 outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
954 outs = ureg_writemask(out, TGSI_WRITEMASK_W);
955 zshuf = ureg_src(data);
956 } else {
957 outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
958 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
959 zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
960 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
961 }
962
963 if (tex_s) {
964 ureg_I2F(ureg, sdst, ssrc);
965 ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
966 }
967
968 if (tex_rgbaz) {
969 ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
970 ureg_F2I(ureg, zdst, zsrc);
971 ureg_AND(ureg, zdst3, zsrc, mask);
972 ureg_I2F(ureg, zdst3, zsrc3);
973 ureg_MUL(ureg, zdst3, zsrc3, scale);
974 ureg_MOV(ureg, outz, zshuf);
975 }
976 } else {
977 unsigned mask = TGSI_WRITEMASK_XYZW;
978
979 if (mode != NV50_BLIT_MODE_PASS) {
980 mask &= ~TGSI_WRITEMASK_ZW;
981 if (!tex_s)
982 mask = TGSI_WRITEMASK_X;
983 if (!tex_rgbaz)
984 mask = TGSI_WRITEMASK_Y;
985 }
986 ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
987 }
988 ureg_END(ureg);
989
990 return ureg_create_shader_and_destroy(ureg, pipe);
991 }
992
993 static void
994 nv50_blitter_make_sampler(struct nv50_blitter *blit)
995 {
996 /* clamp to edge, min/max lod = 0, nearest filtering */
997
998 blit->sampler[0].id = -1;
999
1000 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
1001 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
1002 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
1003 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
1004 blit->sampler[0].tsc[1] =
1005 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
1006
1007 /* clamp to edge, min/max lod = 0, bilinear filtering */
1008
1009 blit->sampler[1].id = -1;
1010
1011 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
1012 blit->sampler[1].tsc[1] =
1013 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
1014 }
1015
1016 unsigned
1017 nv50_blit_select_mode(const struct pipe_blit_info *info)
1018 {
1019 const unsigned mask = info->mask;
1020
1021 switch (info->dst.resource->format) {
1022 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1023 case PIPE_FORMAT_Z24X8_UNORM:
1024 case PIPE_FORMAT_X24S8_UINT:
1025 switch (mask & PIPE_MASK_ZS) {
1026 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
1027 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
1028 default:
1029 return NV50_BLIT_MODE_X24S8;
1030 }
1031 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1032 case PIPE_FORMAT_X8Z24_UNORM:
1033 case PIPE_FORMAT_S8X24_UINT:
1034 switch (mask & PIPE_MASK_ZS) {
1035 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
1036 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
1037 default:
1038 return NV50_BLIT_MODE_S8X24;
1039 }
1040 case PIPE_FORMAT_Z32_FLOAT:
1041 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1042 case PIPE_FORMAT_X32_S8X24_UINT:
1043 switch (mask & PIPE_MASK_ZS) {
1044 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
1045 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
1046 default:
1047 return NV50_BLIT_MODE_XS;
1048 }
1049 default:
1050 return NV50_BLIT_MODE_PASS;
1051 }
1052 }
1053
1054 static void
1055 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
1056 {
1057 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
1058
1059 const enum pipe_texture_target ptarg =
1060 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
1061
1062 const unsigned targ = nv50_blit_texture_type(ptarg);
1063 const unsigned mode = ctx->mode;
1064
1065 if (!blitter->fp[targ][mode]) {
1066 pipe_mutex_lock(blitter->mutex);
1067 if (!blitter->fp[targ][mode])
1068 blitter->fp[targ][mode] =
1069 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
1070 pipe_mutex_unlock(blitter->mutex);
1071 }
1072 ctx->fp = blitter->fp[targ][mode];
1073 }
1074
1075 static void
1076 nv50_blit_set_dst(struct nv50_blitctx *ctx,
1077 struct pipe_resource *res, unsigned level, unsigned layer,
1078 enum pipe_format format)
1079 {
1080 struct nv50_context *nv50 = ctx->nv50;
1081 struct pipe_context *pipe = &nv50->base.pipe;
1082 struct pipe_surface templ;
1083
1084 if (util_format_is_depth_or_stencil(format))
1085 templ.format = nv50_blit_zeta_to_colour_format(format);
1086 else
1087 templ.format = format;
1088
1089 templ.u.tex.level = level;
1090 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
1091
1092 if (layer == -1) {
1093 templ.u.tex.first_layer = 0;
1094 templ.u.tex.last_layer =
1095 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
1096 }
1097
1098 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
1099 nv50->framebuffer.nr_cbufs = 1;
1100 nv50->framebuffer.zsbuf = NULL;
1101 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
1102 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
1103 }
1104
1105 static void
1106 nv50_blit_set_src(struct nv50_blitctx *blit,
1107 struct pipe_resource *res, unsigned level, unsigned layer,
1108 enum pipe_format format, const uint8_t filter)
1109 {
1110 struct nv50_context *nv50 = blit->nv50;
1111 struct pipe_context *pipe = &nv50->base.pipe;
1112 struct pipe_sampler_view templ;
1113 uint32_t flags;
1114 enum pipe_texture_target target;
1115
1116 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
1117
1118 templ.format = format;
1119 templ.u.tex.first_level = templ.u.tex.last_level = level;
1120 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
1121 templ.swizzle_r = PIPE_SWIZZLE_RED;
1122 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
1123 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
1124 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
1125
1126 if (layer == -1) {
1127 templ.u.tex.first_layer = 0;
1128 templ.u.tex.last_layer =
1129 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
1130 }
1131
1132 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
1133 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
1134 if (filter && res->nr_samples == 8)
1135 flags |= NV50_TEXVIEW_FILTER_MSAA8;
1136
1137 nv50->textures[2][0] = nv50_create_texture_view(
1138 pipe, res, &templ, flags, target);
1139 nv50->textures[2][1] = NULL;
1140
1141 nv50->num_textures[0] = nv50->num_textures[1] = 0;
1142 nv50->num_textures[2] = 1;
1143
1144 templ.format = nv50_zs_to_s_format(format);
1145 if (templ.format != res->format) {
1146 nv50->textures[2][1] = nv50_create_texture_view(
1147 pipe, res, &templ, flags, target);
1148 nv50->num_textures[2] = 2;
1149 }
1150 }
1151
1152 static void
1153 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
1154 {
1155 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
1156
1157 if (blit->nv50->cond_query && !blit->render_condition_enable) {
1158 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
1159 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
1160 }
1161
1162 /* blend state */
1163 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
1164 PUSH_DATA (push, blit->color_mask);
1165 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
1166 PUSH_DATA (push, 0);
1167 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
1168 PUSH_DATA (push, 0);
1169
1170 /* rasterizer state */
1171 #ifndef NV50_SCISSORS_CLIPPING
1172 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
1173 PUSH_DATA (push, 1);
1174 #endif
1175 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
1176 PUSH_DATA (push, 0);
1177 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
1178 PUSH_DATA (push, 0);
1179 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
1180 PUSH_DATA (push, 0);
1181 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
1182 PUSH_DATA (push, 0xffff);
1183 PUSH_DATA (push, 0xffff);
1184 PUSH_DATA (push, 0xffff);
1185 PUSH_DATA (push, 0xffff);
1186 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
1187 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
1188 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
1189 PUSH_DATA (push, 0);
1190 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
1191 PUSH_DATA (push, 0);
1192 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
1193 PUSH_DATA (push, 0);
1194 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
1195 PUSH_DATA (push, 0);
1196
1197 /* zsa state */
1198 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
1199 PUSH_DATA (push, 0);
1200 BEGIN_NV04(push, NV50_3D(DEPTH_BOUNDS_EN), 1);
1201 PUSH_DATA (push, 0);
1202 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
1203 PUSH_DATA (push, 0);
1204 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
1205 PUSH_DATA (push, 0);
1206 }
1207
1208 static void
1209 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
1210 {
1211 struct nv50_context *nv50 = ctx->nv50;
1212 struct nv50_blitter *blitter = nv50->screen->blitter;
1213 int s;
1214
1215 ctx->saved.fb.width = nv50->framebuffer.width;
1216 ctx->saved.fb.height = nv50->framebuffer.height;
1217 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
1218 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
1219 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
1220
1221 ctx->saved.rast = nv50->rast;
1222
1223 ctx->saved.vp = nv50->vertprog;
1224 ctx->saved.gp = nv50->gmtyprog;
1225 ctx->saved.fp = nv50->fragprog;
1226
1227 ctx->saved.min_samples = nv50->min_samples;
1228
1229 nv50->rast = &ctx->rast;
1230
1231 nv50->vertprog = &blitter->vp;
1232 nv50->gmtyprog = NULL;
1233 nv50->fragprog = ctx->fp;
1234
1235 for (s = 0; s < 3; ++s) {
1236 ctx->saved.num_textures[s] = nv50->num_textures[s];
1237 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
1238 }
1239 ctx->saved.texture[0] = nv50->textures[2][0];
1240 ctx->saved.texture[1] = nv50->textures[2][1];
1241 ctx->saved.sampler[0] = nv50->samplers[2][0];
1242 ctx->saved.sampler[1] = nv50->samplers[2][1];
1243
1244 nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
1245 nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
1246
1247 nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
1248 nv50->num_samplers[2] = 2;
1249
1250 nv50->min_samples = 1;
1251
1252 ctx->saved.dirty = nv50->dirty;
1253
1254 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
1255 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
1256
1257 nv50->dirty =
1258 NV50_NEW_FRAMEBUFFER | NV50_NEW_MIN_SAMPLES |
1259 NV50_NEW_VERTPROG | NV50_NEW_FRAGPROG | NV50_NEW_GMTYPROG |
1260 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS;
1261 }
1262
1263 static void
1264 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
1265 {
1266 struct nv50_context *nv50 = blit->nv50;
1267 int s;
1268
1269 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
1270
1271 nv50->framebuffer.width = blit->saved.fb.width;
1272 nv50->framebuffer.height = blit->saved.fb.height;
1273 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1274 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1275 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1276
1277 nv50->rast = blit->saved.rast;
1278
1279 nv50->vertprog = blit->saved.vp;
1280 nv50->gmtyprog = blit->saved.gp;
1281 nv50->fragprog = blit->saved.fp;
1282
1283 nv50->min_samples = blit->saved.min_samples;
1284
1285 pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
1286 pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
1287
1288 for (s = 0; s < 3; ++s) {
1289 nv50->num_textures[s] = blit->saved.num_textures[s];
1290 nv50->num_samplers[s] = blit->saved.num_samplers[s];
1291 }
1292 nv50->textures[2][0] = blit->saved.texture[0];
1293 nv50->textures[2][1] = blit->saved.texture[1];
1294 nv50->samplers[2][0] = blit->saved.sampler[0];
1295 nv50->samplers[2][1] = blit->saved.sampler[1];
1296
1297 if (nv50->cond_query && !blit->render_condition_enable)
1298 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
1299 nv50->cond_cond, nv50->cond_mode);
1300
1301 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
1302 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
1303
1304 nv50->dirty = blit->saved.dirty |
1305 (NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR | NV50_NEW_SAMPLE_MASK |
1306 NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
1307 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
1308 NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
1309 nv50->scissors_dirty |= 1;
1310
1311 nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
1312 }
1313
1314
1315 static void
1316 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1317 {
1318 struct nv50_blitctx *blit = nv50->blit;
1319 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1320 struct pipe_resource *src = info->src.resource;
1321 struct pipe_resource *dst = info->dst.resource;
1322 int32_t minx, maxx, miny, maxy;
1323 int32_t i;
1324 float x0, x1, y0, y1, z;
1325 float dz;
1326 float x_range, y_range;
1327 float tri_x, tri_y;
1328
1329 blit->mode = nv50_blit_select_mode(info);
1330 blit->color_mask = nv50_blit_derive_color_mask(info);
1331 blit->filter = nv50_blit_get_filter(info);
1332 blit->render_condition_enable = info->render_condition_enable;
1333
1334 nv50_blit_select_fp(blit, info);
1335 nv50_blitctx_pre_blit(blit);
1336
1337 nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1338 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1339 blit->filter);
1340
1341 nv50_blitctx_prepare_state(blit);
1342
1343 nv50_state_validate(nv50, ~0, 36);
1344
1345 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1346 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1347
1348 tri_x = 16384 << nv50_miptree(dst)->ms_x;
1349 tri_y = 16384 << nv50_miptree(dst)->ms_y;
1350
1351 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1352 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1353
1354 x1 = x0 + tri_x * x_range;
1355 y1 = y0 + tri_y * y_range;
1356
1357 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1358 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1359 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1360 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1361
1362 /* XXX: multiply by 6 for cube arrays ? */
1363 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1364 z = (float)info->src.box.z;
1365 if (nv50_miptree(src)->layout_3d)
1366 z += 0.5f * dz;
1367
1368 if (src->last_level > 0) {
1369 /* If there are mip maps, GPU always assumes normalized coordinates. */
1370 const unsigned l = info->src.level;
1371 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1372 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1373 x0 /= fh;
1374 x1 /= fh;
1375 y0 /= fv;
1376 y1 /= fv;
1377 if (nv50_miptree(src)->layout_3d) {
1378 z /= u_minify(src->depth0, l);
1379 dz /= u_minify(src->depth0, l);
1380 }
1381 }
1382
1383 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1384 PUSH_DATA (push, 0);
1385 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1386 PUSH_DATA (push, 0x1);
1387
1388 /* Draw a large triangle in screen coordinates covering the whole
1389 * render target, with scissors defining the destination region.
1390 * The vertex is supplied with non-normalized texture coordinates
1391 * arranged in a way to yield the desired offset and scale.
1392 */
1393
1394 minx = info->dst.box.x;
1395 maxx = info->dst.box.x + info->dst.box.width;
1396 miny = info->dst.box.y;
1397 maxy = info->dst.box.y + info->dst.box.height;
1398 if (info->scissor_enable) {
1399 minx = MAX2(minx, info->scissor.minx);
1400 maxx = MIN2(maxx, info->scissor.maxx);
1401 miny = MAX2(miny, info->scissor.miny);
1402 maxy = MIN2(maxy, info->scissor.maxy);
1403 }
1404 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
1405 PUSH_DATA (push, (maxx << 16) | minx);
1406 PUSH_DATA (push, (maxy << 16) | miny);
1407
1408 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1409 if (info->dst.box.z + i) {
1410 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1411 PUSH_DATA (push, info->dst.box.z + i);
1412 }
1413 PUSH_SPACE(push, 32);
1414 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1415 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1416 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1417 PUSH_DATAf(push, x0);
1418 PUSH_DATAf(push, y0);
1419 PUSH_DATAf(push, z);
1420 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1421 PUSH_DATAf(push, 0.0f);
1422 PUSH_DATAf(push, 0.0f);
1423 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1424 PUSH_DATAf(push, x1);
1425 PUSH_DATAf(push, y0);
1426 PUSH_DATAf(push, z);
1427 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1428 PUSH_DATAf(push, tri_x);
1429 PUSH_DATAf(push, 0.0f);
1430 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1431 PUSH_DATAf(push, x0);
1432 PUSH_DATAf(push, y1);
1433 PUSH_DATAf(push, z);
1434 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1435 PUSH_DATAf(push, 0.0f);
1436 PUSH_DATAf(push, tri_y);
1437 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1438 PUSH_DATA (push, 0);
1439 }
1440 if (info->dst.box.z + info->dst.box.depth - 1) {
1441 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1442 PUSH_DATA (push, 0);
1443 }
1444
1445 /* re-enable normally constant state */
1446
1447 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1448 PUSH_DATA (push, 1);
1449
1450 nv50_blitctx_post_blit(blit);
1451 }
1452
1453 static void
1454 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1455 {
1456 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1457 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1458 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1459 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1460 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1461 const int32_t dz = info->dst.box.z;
1462 const int32_t sz = info->src.box.z;
1463 uint32_t dstw, dsth;
1464 int32_t dstx, dsty;
1465 int64_t srcx, srcy;
1466 int64_t du_dx, dv_dy;
1467 int i;
1468 uint32_t mode;
1469 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1470 bool b;
1471
1472 mode = nv50_blit_get_filter(info) ?
1473 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1474 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1475 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1476 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1477
1478 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1479 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1480
1481 b = info->dst.format == info->src.format;
1482 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1483 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1484
1485 if (info->scissor_enable) {
1486 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1487 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1488 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1489 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1490 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1491 PUSH_DATA (push, 1); /* enable */
1492 }
1493
1494 if (nv50->cond_query && info->render_condition_enable) {
1495 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1496 PUSH_DATA (push, nv50->cond_condmode);
1497 }
1498
1499 if (mask != 0xffffffff) {
1500 BEGIN_NV04(push, NV50_2D(ROP), 1);
1501 PUSH_DATA (push, 0xca); /* DPSDxax */
1502 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1503 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1504 BEGIN_NV04(push, NV50_2D(PATTERN_BITMAP_COLOR(0)), 4);
1505 PUSH_DATA (push, 0x00000000);
1506 PUSH_DATA (push, mask);
1507 PUSH_DATA (push, 0xffffffff);
1508 PUSH_DATA (push, 0xffffffff);
1509 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1510 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1511 } else
1512 if (info->src.format != info->dst.format) {
1513 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1514 info->src.format == PIPE_FORMAT_R16_UNORM ||
1515 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1516 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1517 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1518 BEGIN_NV04(push, NV50_2D(BETA4), 2);
1519 PUSH_DATA (push, mask);
1520 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1521 }
1522 }
1523
1524 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1525 /* ms_x is always >= ms_y */
1526 du_dx <<= src->ms_x - dst->ms_x;
1527 dv_dy <<= src->ms_y - dst->ms_y;
1528 } else {
1529 du_dx >>= dst->ms_x - src->ms_x;
1530 dv_dy >>= dst->ms_y - src->ms_y;
1531 }
1532
1533 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1534 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1535
1536 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1537 /* center src coorinates for proper MS resolve filtering */
1538 srcx += (int64_t)1 << (src->ms_x + 31);
1539 srcy += (int64_t)1 << (src->ms_y + 31);
1540 }
1541
1542 dstx = info->dst.box.x << dst->ms_x;
1543 dsty = info->dst.box.y << dst->ms_y;
1544
1545 dstw = info->dst.box.width << dst->ms_x;
1546 dsth = info->dst.box.height << dst->ms_y;
1547
1548 if (dstx < 0) {
1549 dstw += dstx;
1550 srcx -= du_dx * dstx;
1551 dstx = 0;
1552 }
1553 if (dsty < 0) {
1554 dsth += dsty;
1555 srcy -= dv_dy * dsty;
1556 dsty = 0;
1557 }
1558
1559 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1560 PUSH_DATA (push, mode);
1561 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1562 PUSH_DATA (push, dstx);
1563 PUSH_DATA (push, dsty);
1564 PUSH_DATA (push, dstw);
1565 PUSH_DATA (push, dsth);
1566 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1567 PUSH_DATA (push, du_dx);
1568 PUSH_DATA (push, du_dx >> 32);
1569 PUSH_DATA (push, dv_dy);
1570 PUSH_DATA (push, dv_dy >> 32);
1571
1572 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1573 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1574 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1575 if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1576 return;
1577
1578 for (i = 0; i < info->dst.box.depth; ++i) {
1579 if (i > 0) {
1580 /* no scaling in z-direction possible for eng2d blits */
1581 if (dst->layout_3d) {
1582 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1583 PUSH_DATA (push, info->dst.box.z + i);
1584 } else {
1585 const unsigned z = info->dst.box.z + i;
1586 const uint64_t address = dst->base.address +
1587 dst->level[info->dst.level].offset +
1588 z * dst->layer_stride;
1589 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1590 PUSH_DATAh(push, address);
1591 PUSH_DATA (push, address);
1592 }
1593 if (src->layout_3d) {
1594 /* not possible because of depth tiling */
1595 assert(0);
1596 } else {
1597 const unsigned z = info->src.box.z + i;
1598 const uint64_t address = src->base.address +
1599 src->level[info->src.level].offset +
1600 z * src->layer_stride;
1601 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1602 PUSH_DATAh(push, address);
1603 PUSH_DATA (push, address);
1604 }
1605 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1606 PUSH_DATA (push, srcy >> 32);
1607 } else {
1608 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1609 PUSH_DATA (push, srcx);
1610 PUSH_DATA (push, srcx >> 32);
1611 PUSH_DATA (push, srcy);
1612 PUSH_DATA (push, srcy >> 32);
1613 }
1614 }
1615 nv50_bufctx_fence(nv50->bufctx, false);
1616
1617 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1618
1619 if (info->scissor_enable) {
1620 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1621 PUSH_DATA (push, 0);
1622 }
1623 if (mask != 0xffffffff) {
1624 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1625 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1626 }
1627 if (nv50->cond_query && info->render_condition_enable) {
1628 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1629 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1630 }
1631 }
1632
1633 static void
1634 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1635 {
1636 struct nv50_context *nv50 = nv50_context(pipe);
1637 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1638 bool eng3d = FALSE;
1639
1640 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1641 if (!(info->mask & PIPE_MASK_ZS))
1642 return;
1643 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1644 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1645 eng3d = true;
1646 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1647 eng3d = true;
1648 } else {
1649 if (!(info->mask & PIPE_MASK_RGBA))
1650 return;
1651 if (info->mask != PIPE_MASK_RGBA)
1652 eng3d = true;
1653 }
1654
1655 if (nv50_miptree(info->src.resource)->layout_3d) {
1656 eng3d = true;
1657 } else
1658 if (info->src.box.depth != info->dst.box.depth) {
1659 eng3d = true;
1660 debug_printf("blit: cannot filter array or cube textures in z direction");
1661 }
1662
1663 if (!eng3d && info->dst.format != info->src.format) {
1664 if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1665 !nv50_2d_src_format_faithful(info->src.format)) {
1666 eng3d = true;
1667 } else
1668 if (!nv50_2d_src_format_faithful(info->src.format)) {
1669 if (!util_format_is_luminance(info->src.format)) {
1670 if (util_format_is_intensity(info->src.format))
1671 eng3d = true;
1672 else
1673 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1674 eng3d = true;
1675 else
1676 eng3d = !nv50_2d_format_supported(info->src.format);
1677 }
1678 } else
1679 if (util_format_is_luminance_alpha(info->src.format))
1680 eng3d = true;
1681 }
1682
1683 if (info->src.resource->nr_samples == 8 &&
1684 info->dst.resource->nr_samples <= 1)
1685 eng3d = true;
1686
1687 /* FIXME: can't make this work with eng2d anymore */
1688 if ((info->src.resource->nr_samples | 1) !=
1689 (info->dst.resource->nr_samples | 1))
1690 eng3d = true;
1691
1692 /* FIXME: find correct src coordinate adjustments */
1693 if ((info->src.box.width != info->dst.box.width &&
1694 info->src.box.width != -info->dst.box.width) ||
1695 (info->src.box.height != info->dst.box.height &&
1696 info->src.box.height != -info->dst.box.height))
1697 eng3d = true;
1698
1699 if (nv50->screen->num_occlusion_queries_active) {
1700 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1701 PUSH_DATA (push, 0);
1702 }
1703
1704 if (!eng3d)
1705 nv50_blit_eng2d(nv50, info);
1706 else
1707 nv50_blit_3d(nv50, info);
1708
1709 if (nv50->screen->num_occlusion_queries_active) {
1710 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1711 PUSH_DATA (push, 1);
1712 }
1713 }
1714
1715 static void
1716 nv50_flush_resource(struct pipe_context *ctx,
1717 struct pipe_resource *resource)
1718 {
1719 }
1720
1721 bool
1722 nv50_blitter_create(struct nv50_screen *screen)
1723 {
1724 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1725 if (!screen->blitter) {
1726 NOUVEAU_ERR("failed to allocate blitter struct\n");
1727 return false;
1728 }
1729
1730 pipe_mutex_init(screen->blitter->mutex);
1731
1732 nv50_blitter_make_vp(screen->blitter);
1733 nv50_blitter_make_sampler(screen->blitter);
1734
1735 return true;
1736 }
1737
1738 void
1739 nv50_blitter_destroy(struct nv50_screen *screen)
1740 {
1741 struct nv50_blitter *blitter = screen->blitter;
1742 unsigned i, m;
1743
1744 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1745 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1746 struct nv50_program *prog = blitter->fp[i][m];
1747 if (prog) {
1748 nv50_program_destroy(NULL, prog);
1749 FREE((void *)prog->pipe.tokens);
1750 FREE(prog);
1751 }
1752 }
1753 }
1754
1755 FREE(blitter);
1756 }
1757
1758 bool
1759 nv50_blitctx_create(struct nv50_context *nv50)
1760 {
1761 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1762 if (!nv50->blit) {
1763 NOUVEAU_ERR("failed to allocate blit context\n");
1764 return false;
1765 }
1766
1767 nv50->blit->nv50 = nv50;
1768
1769 nv50->blit->rast.pipe.half_pixel_center = 1;
1770
1771 return true;
1772 }
1773
1774 void
1775 nv50_init_surface_functions(struct nv50_context *nv50)
1776 {
1777 struct pipe_context *pipe = &nv50->base.pipe;
1778
1779 pipe->resource_copy_region = nv50_resource_copy_region;
1780 pipe->blit = nv50_blit;
1781 pipe->flush_resource = nv50_flush_resource;
1782 pipe->clear_texture = nv50_clear_texture;
1783 pipe->clear_render_target = nv50_clear_render_target;
1784 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1785 pipe->clear_buffer = nv50_clear_buffer;
1786 }