2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
32 #include "tgsi/tgsi_ureg.h"
34 #include "os/os_thread.h"
36 #include "nv50/nv50_context.h"
37 #include "nv50/nv50_resource.h"
39 #include "nv50/nv50_defs.xml.h"
40 #include "nv50/nv50_texture.xml.h"
42 /* these are used in nv50_blit.h */
43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
44 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
45 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
47 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
49 #define NOUVEAU_DRIVER 0x50
50 #include "nv50/nv50_blit.h"
53 nv50_2d_format(enum pipe_format format
, boolean dst
, boolean dst_src_equal
)
55 uint8_t id
= nv50_format_table
[format
].rt
;
57 /* Hardware values for color formats range from 0xc0 to 0xff,
58 * but the 2D engine doesn't support all of them.
60 if ((id
>= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS
& (1ULL << (id
- 0xc0))))
62 assert(dst_src_equal
);
64 switch (util_format_get_blocksize(format
)) {
66 return NV50_SURFACE_FORMAT_R8_UNORM
;
68 return NV50_SURFACE_FORMAT_R16_UNORM
;
70 return NV50_SURFACE_FORMAT_BGRA8_UNORM
;
77 nv50_2d_texture_set(struct nouveau_pushbuf
*push
, int dst
,
78 struct nv50_miptree
*mt
, unsigned level
, unsigned layer
,
79 enum pipe_format pformat
, boolean dst_src_pformat_equal
)
81 struct nouveau_bo
*bo
= mt
->base
.bo
;
82 uint32_t width
, height
, depth
;
84 uint32_t mthd
= dst
? NV50_2D_DST_FORMAT
: NV50_2D_SRC_FORMAT
;
85 uint32_t offset
= mt
->level
[level
].offset
;
87 format
= nv50_2d_format(pformat
, dst
, dst_src_pformat_equal
);
89 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
90 util_format_name(pformat
));
94 width
= u_minify(mt
->base
.base
.width0
, level
) << mt
->ms_x
;
95 height
= u_minify(mt
->base
.base
.height0
, level
) << mt
->ms_y
;
96 depth
= u_minify(mt
->base
.base
.depth0
, level
);
98 offset
= mt
->level
[level
].offset
;
100 offset
+= mt
->layer_stride
* layer
;
105 offset
+= nv50_mt_zslice_offset(mt
, level
, layer
);
109 if (!nouveau_bo_memtype(bo
)) {
110 BEGIN_NV04(push
, SUBC_2D(mthd
), 2);
111 PUSH_DATA (push
, format
);
113 BEGIN_NV04(push
, SUBC_2D(mthd
+ 0x14), 5);
114 PUSH_DATA (push
, mt
->level
[level
].pitch
);
115 PUSH_DATA (push
, width
);
116 PUSH_DATA (push
, height
);
117 PUSH_DATAh(push
, mt
->base
.address
+ offset
);
118 PUSH_DATA (push
, mt
->base
.address
+ offset
);
120 BEGIN_NV04(push
, SUBC_2D(mthd
), 5);
121 PUSH_DATA (push
, format
);
123 PUSH_DATA (push
, mt
->level
[level
].tile_mode
);
124 PUSH_DATA (push
, depth
);
125 PUSH_DATA (push
, layer
);
126 BEGIN_NV04(push
, SUBC_2D(mthd
+ 0x18), 4);
127 PUSH_DATA (push
, width
);
128 PUSH_DATA (push
, height
);
129 PUSH_DATAh(push
, mt
->base
.address
+ offset
);
130 PUSH_DATA (push
, mt
->base
.address
+ offset
);
135 BEGIN_NV04(push
, SUBC_2D(NV50_2D_CLIP_X
), 4);
138 PUSH_DATA (push
, width
);
139 PUSH_DATA (push
, height
);
146 nv50_2d_texture_do_copy(struct nouveau_pushbuf
*push
,
147 struct nv50_miptree
*dst
, unsigned dst_level
,
148 unsigned dx
, unsigned dy
, unsigned dz
,
149 struct nv50_miptree
*src
, unsigned src_level
,
150 unsigned sx
, unsigned sy
, unsigned sz
,
151 unsigned w
, unsigned h
)
153 const enum pipe_format dfmt
= dst
->base
.base
.format
;
154 const enum pipe_format sfmt
= src
->base
.base
.format
;
156 boolean eqfmt
= dfmt
== sfmt
;
158 if (!PUSH_SPACE(push
, 2 * 16 + 32))
161 ret
= nv50_2d_texture_set(push
, 1, dst
, dst_level
, dz
, dfmt
, eqfmt
);
165 ret
= nv50_2d_texture_set(push
, 0, src
, src_level
, sz
, sfmt
, eqfmt
);
169 BEGIN_NV04(push
, NV50_2D(BLIT_CONTROL
), 1);
170 PUSH_DATA (push
, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE
);
171 BEGIN_NV04(push
, NV50_2D(BLIT_DST_X
), 4);
172 PUSH_DATA (push
, dx
<< dst
->ms_x
);
173 PUSH_DATA (push
, dy
<< dst
->ms_y
);
174 PUSH_DATA (push
, w
<< dst
->ms_x
);
175 PUSH_DATA (push
, h
<< dst
->ms_y
);
176 BEGIN_NV04(push
, NV50_2D(BLIT_DU_DX_FRACT
), 4);
181 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_X_FRACT
), 4);
183 PUSH_DATA (push
, sx
<< src
->ms_x
);
185 PUSH_DATA (push
, sy
<< src
->ms_y
);
191 nv50_resource_copy_region(struct pipe_context
*pipe
,
192 struct pipe_resource
*dst
, unsigned dst_level
,
193 unsigned dstx
, unsigned dsty
, unsigned dstz
,
194 struct pipe_resource
*src
, unsigned src_level
,
195 const struct pipe_box
*src_box
)
197 struct nv50_context
*nv50
= nv50_context(pipe
);
200 unsigned dst_layer
= dstz
, src_layer
= src_box
->z
;
202 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
203 nouveau_copy_buffer(&nv50
->base
,
204 nv04_resource(dst
), dstx
,
205 nv04_resource(src
), src_box
->x
, src_box
->width
);
209 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
210 assert((src
->nr_samples
| 1) == (dst
->nr_samples
| 1));
212 m2mf
= (src
->format
== dst
->format
) ||
213 (util_format_get_blocksizebits(src
->format
) ==
214 util_format_get_blocksizebits(dst
->format
));
216 nv04_resource(dst
)->status
|= NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
219 struct nv50_m2mf_rect drect
, srect
;
221 unsigned nx
= util_format_get_nblocksx(src
->format
, src_box
->width
);
222 unsigned ny
= util_format_get_nblocksy(src
->format
, src_box
->height
);
224 nv50_m2mf_rect_setup(&drect
, dst
, dst_level
, dstx
, dsty
, dstz
);
225 nv50_m2mf_rect_setup(&srect
, src
, src_level
,
226 src_box
->x
, src_box
->y
, src_box
->z
);
228 for (i
= 0; i
< src_box
->depth
; ++i
) {
229 nv50_m2mf_transfer_rect(nv50
, &drect
, &srect
, nx
, ny
);
231 if (nv50_miptree(dst
)->layout_3d
)
234 drect
.base
+= nv50_miptree(dst
)->layer_stride
;
236 if (nv50_miptree(src
)->layout_3d
)
239 srect
.base
+= nv50_miptree(src
)->layer_stride
;
244 assert((src
->format
== dst
->format
) ||
245 (nv50_2d_src_format_faithful(src
->format
) &&
246 nv50_2d_dst_format_faithful(dst
->format
)));
248 BCTX_REFN(nv50
->bufctx
, 2D
, nv04_resource(src
), RD
);
249 BCTX_REFN(nv50
->bufctx
, 2D
, nv04_resource(dst
), WR
);
250 nouveau_pushbuf_bufctx(nv50
->base
.pushbuf
, nv50
->bufctx
);
251 nouveau_pushbuf_validate(nv50
->base
.pushbuf
);
253 for (; dst_layer
< dstz
+ src_box
->depth
; ++dst_layer
, ++src_layer
) {
254 ret
= nv50_2d_texture_do_copy(nv50
->base
.pushbuf
,
255 nv50_miptree(dst
), dst_level
,
256 dstx
, dsty
, dst_layer
,
257 nv50_miptree(src
), src_level
,
258 src_box
->x
, src_box
->y
, src_layer
,
259 src_box
->width
, src_box
->height
);
263 nouveau_bufctx_reset(nv50
->bufctx
, NV50_BIND_2D
);
267 nv50_clear_render_target(struct pipe_context
*pipe
,
268 struct pipe_surface
*dst
,
269 const union pipe_color_union
*color
,
270 unsigned dstx
, unsigned dsty
,
271 unsigned width
, unsigned height
)
273 struct nv50_context
*nv50
= nv50_context(pipe
);
274 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
275 struct nv50_miptree
*mt
= nv50_miptree(dst
->texture
);
276 struct nv50_surface
*sf
= nv50_surface(dst
);
277 struct nouveau_bo
*bo
= mt
->base
.bo
;
280 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
281 PUSH_DATAf(push
, color
->f
[0]);
282 PUSH_DATAf(push
, color
->f
[1]);
283 PUSH_DATAf(push
, color
->f
[2]);
284 PUSH_DATAf(push
, color
->f
[3]);
286 if (nouveau_pushbuf_space(push
, 32 + sf
->depth
, 1, 0))
289 PUSH_REFN(push
, bo
, mt
->base
.domain
| NOUVEAU_BO_WR
);
291 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
292 PUSH_DATA (push
, ( width
<< 16) | dstx
);
293 PUSH_DATA (push
, (height
<< 16) | dsty
);
294 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
295 PUSH_DATA (push
, 8192 << 16);
296 PUSH_DATA (push
, 8192 << 16);
297 nv50
->scissors_dirty
|= 1;
299 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
301 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
302 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
303 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
304 PUSH_DATA (push
, nv50_format_table
[dst
->format
].rt
);
305 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
306 PUSH_DATA (push
, mt
->layer_stride
>> 2);
307 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(0)), 2);
308 if (nouveau_bo_memtype(bo
))
309 PUSH_DATA(push
, sf
->width
);
311 PUSH_DATA(push
, NV50_3D_RT_HORIZ_LINEAR
| mt
->level
[0].pitch
);
312 PUSH_DATA (push
, sf
->height
);
313 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
315 PUSH_DATA(push
, NV50_3D_RT_ARRAY_MODE_MODE_3D
| 512);
317 PUSH_DATA(push
, 512);
319 if (!nouveau_bo_memtype(bo
)) {
320 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
324 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
326 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
327 PUSH_DATA (push
, (width
<< 16) | dstx
);
328 PUSH_DATA (push
, (height
<< 16) | dsty
);
330 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), sf
->depth
);
331 for (z
= 0; z
< sf
->depth
; ++z
) {
332 PUSH_DATA (push
, 0x3c |
333 (z
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
336 nv50
->dirty
|= NV50_NEW_FRAMEBUFFER
| NV50_NEW_SCISSOR
;
340 nv50_clear_depth_stencil(struct pipe_context
*pipe
,
341 struct pipe_surface
*dst
,
342 unsigned clear_flags
,
345 unsigned dstx
, unsigned dsty
,
346 unsigned width
, unsigned height
)
348 struct nv50_context
*nv50
= nv50_context(pipe
);
349 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
350 struct nv50_miptree
*mt
= nv50_miptree(dst
->texture
);
351 struct nv50_surface
*sf
= nv50_surface(dst
);
352 struct nouveau_bo
*bo
= mt
->base
.bo
;
356 assert(nouveau_bo_memtype(bo
)); /* ZETA cannot be linear */
358 if (clear_flags
& PIPE_CLEAR_DEPTH
) {
359 BEGIN_NV04(push
, NV50_3D(CLEAR_DEPTH
), 1);
360 PUSH_DATAf(push
, depth
);
361 mode
|= NV50_3D_CLEAR_BUFFERS_Z
;
364 if (clear_flags
& PIPE_CLEAR_STENCIL
) {
365 BEGIN_NV04(push
, NV50_3D(CLEAR_STENCIL
), 1);
366 PUSH_DATA (push
, stencil
& 0xff);
367 mode
|= NV50_3D_CLEAR_BUFFERS_S
;
370 if (nouveau_pushbuf_space(push
, 32 + sf
->depth
, 1, 0))
373 PUSH_REFN(push
, bo
, mt
->base
.domain
| NOUVEAU_BO_WR
);
375 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
376 PUSH_DATA (push
, ( width
<< 16) | dstx
);
377 PUSH_DATA (push
, (height
<< 16) | dsty
);
378 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
379 PUSH_DATA (push
, 8192 << 16);
380 PUSH_DATA (push
, 8192 << 16);
381 nv50
->scissors_dirty
|= 1;
383 BEGIN_NV04(push
, NV50_3D(ZETA_ADDRESS_HIGH
), 5);
384 PUSH_DATAh(push
, mt
->base
.address
+ sf
->offset
);
385 PUSH_DATA (push
, mt
->base
.address
+ sf
->offset
);
386 PUSH_DATA (push
, nv50_format_table
[dst
->format
].rt
);
387 PUSH_DATA (push
, mt
->level
[sf
->base
.u
.tex
.level
].tile_mode
);
388 PUSH_DATA (push
, mt
->layer_stride
>> 2);
389 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
391 BEGIN_NV04(push
, NV50_3D(ZETA_HORIZ
), 3);
392 PUSH_DATA (push
, sf
->width
);
393 PUSH_DATA (push
, sf
->height
);
394 PUSH_DATA (push
, (1 << 16) | 1);
396 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
397 PUSH_DATA (push
, 512);
399 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
400 PUSH_DATA (push
, (width
<< 16) | dstx
);
401 PUSH_DATA (push
, (height
<< 16) | dsty
);
403 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), sf
->depth
);
404 for (z
= 0; z
< sf
->depth
; ++z
) {
405 PUSH_DATA (push
, mode
|
406 (z
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
409 nv50
->dirty
|= NV50_NEW_FRAMEBUFFER
| NV50_NEW_SCISSOR
;
413 nv50_clear(struct pipe_context
*pipe
, unsigned buffers
,
414 const union pipe_color_union
*color
,
415 double depth
, unsigned stencil
)
417 struct nv50_context
*nv50
= nv50_context(pipe
);
418 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
419 struct pipe_framebuffer_state
*fb
= &nv50
->framebuffer
;
423 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
424 if (!nv50_state_validate(nv50
, NV50_NEW_FRAMEBUFFER
, 9 + (fb
->nr_cbufs
* 2)))
427 /* We have to clear ALL of the layers, not up to the min number of layers
428 * of any attachment. */
429 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
430 PUSH_DATA (push
, (nv50
->rt_array_mode
& NV50_3D_RT_ARRAY_MODE_MODE_3D
) | 512);
432 if (buffers
& PIPE_CLEAR_COLOR
&& fb
->nr_cbufs
) {
433 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
434 PUSH_DATAf(push
, color
->f
[0]);
435 PUSH_DATAf(push
, color
->f
[1]);
436 PUSH_DATAf(push
, color
->f
[2]);
437 PUSH_DATAf(push
, color
->f
[3]);
438 if (buffers
& PIPE_CLEAR_COLOR0
)
440 NV50_3D_CLEAR_BUFFERS_R
| NV50_3D_CLEAR_BUFFERS_G
|
441 NV50_3D_CLEAR_BUFFERS_B
| NV50_3D_CLEAR_BUFFERS_A
;
444 if (buffers
& PIPE_CLEAR_DEPTH
) {
445 BEGIN_NV04(push
, NV50_3D(CLEAR_DEPTH
), 1);
446 PUSH_DATA (push
, fui(depth
));
447 mode
|= NV50_3D_CLEAR_BUFFERS_Z
;
450 if (buffers
& PIPE_CLEAR_STENCIL
) {
451 BEGIN_NV04(push
, NV50_3D(CLEAR_STENCIL
), 1);
452 PUSH_DATA (push
, stencil
& 0xff);
453 mode
|= NV50_3D_CLEAR_BUFFERS_S
;
457 int zs_layers
= 0, color0_layers
= 0;
458 if (fb
->cbufs
[0] && (mode
& 0x3c))
459 color0_layers
= fb
->cbufs
[0]->u
.tex
.last_layer
-
460 fb
->cbufs
[0]->u
.tex
.first_layer
+ 1;
461 if (fb
->zsbuf
&& (mode
& ~0x3c))
462 zs_layers
= fb
->zsbuf
->u
.tex
.last_layer
-
463 fb
->zsbuf
->u
.tex
.first_layer
+ 1;
465 for (j
= 0; j
< MIN2(zs_layers
, color0_layers
); j
++) {
466 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
467 PUSH_DATA(push
, mode
| (j
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
469 for (k
= j
; k
< zs_layers
; k
++) {
470 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
471 PUSH_DATA(push
, (mode
& ~0x3c) | (k
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
473 for (k
= j
; k
< color0_layers
; k
++) {
474 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
475 PUSH_DATA(push
, (mode
& 0x3c) | (k
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
479 for (i
= 1; i
< fb
->nr_cbufs
; i
++) {
480 struct pipe_surface
*sf
= fb
->cbufs
[i
];
481 if (!sf
|| !(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
483 for (j
= 0; j
<= sf
->u
.tex
.last_layer
- sf
->u
.tex
.first_layer
; j
++) {
484 BEGIN_NV04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
485 PUSH_DATA (push
, (i
<< 6) | 0x3c |
486 (j
<< NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT
));
490 /* restore the array mode */
491 BEGIN_NV04(push
, NV50_3D(RT_ARRAY_MODE
), 1);
492 PUSH_DATA (push
, nv50
->rt_array_mode
);
496 nv50_clear_buffer(struct pipe_context
*pipe
,
497 struct pipe_resource
*res
,
498 unsigned offset
, unsigned size
,
499 const void *data
, int data_size
)
501 struct nv50_context
*nv50
= nv50_context(pipe
);
502 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
503 struct nv04_resource
*buf
= (struct nv04_resource
*)res
;
504 union pipe_color_union color
;
505 enum pipe_format dst_fmt
;
506 unsigned width
, height
, elements
;
508 assert(res
->target
== PIPE_BUFFER
);
509 assert(nouveau_bo_memtype(buf
->bo
) == 0);
513 dst_fmt
= PIPE_FORMAT_R32G32B32A32_UINT
;
514 memcpy(&color
.ui
, data
, 16);
517 dst_fmt
= PIPE_FORMAT_R32G32_UINT
;
518 memcpy(&color
.ui
, data
, 8);
519 memset(&color
.ui
[2], 0, 8);
522 dst_fmt
= PIPE_FORMAT_R32_UINT
;
523 memcpy(&color
.ui
, data
, 4);
524 memset(&color
.ui
[1], 0, 12);
527 dst_fmt
= PIPE_FORMAT_R16_UINT
;
528 color
.ui
[0] = util_cpu_to_le32(
529 util_le16_to_cpu(*(unsigned short *)data
));
530 memset(&color
.ui
[1], 0, 12);
533 dst_fmt
= PIPE_FORMAT_R8_UINT
;
534 color
.ui
[0] = util_cpu_to_le32(*(unsigned char *)data
);
535 memset(&color
.ui
[1], 0, 12);
538 assert(!"Unsupported element size");
542 assert(size
% data_size
== 0);
544 elements
= size
/ data_size
;
545 height
= (elements
+ 8191) / 8192;
546 width
= elements
/ height
;
548 BEGIN_NV04(push
, NV50_3D(CLEAR_COLOR(0)), 4);
549 PUSH_DATAf(push
, color
.f
[0]);
550 PUSH_DATAf(push
, color
.f
[1]);
551 PUSH_DATAf(push
, color
.f
[2]);
552 PUSH_DATAf(push
, color
.f
[3]);
554 if (nouveau_pushbuf_space(push
, 32, 1, 0))
557 PUSH_REFN(push
, buf
->bo
, buf
->domain
| NOUVEAU_BO_WR
);
559 BEGIN_NV04(push
, NV50_3D(SCREEN_SCISSOR_HORIZ
), 2);
560 PUSH_DATA (push
, width
<< 16);
561 PUSH_DATA (push
, height
<< 16);
562 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
563 PUSH_DATA (push
, 8192 << 16);
564 PUSH_DATA (push
, 8192 << 16);
565 nv50
->scissors_dirty
|= 1;
567 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
569 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
570 PUSH_DATAh(push
, buf
->bo
->offset
+ buf
->offset
+ offset
);
571 PUSH_DATA (push
, buf
->bo
->offset
+ buf
->offset
+ offset
);
572 PUSH_DATA (push
, nv50_format_table
[dst_fmt
].rt
);
575 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(0)), 2);
576 PUSH_DATA (push
, NV50_3D_RT_HORIZ_LINEAR
| (width
* data_size
));
577 PUSH_DATA (push
, height
);
578 BEGIN_NV04(push
, NV50_3D(ZETA_ENABLE
), 1);
581 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
583 BEGIN_NV04(push
, NV50_3D(VIEWPORT_HORIZ(0)), 2);
584 PUSH_DATA (push
, (width
<< 16));
585 PUSH_DATA (push
, (height
<< 16));
587 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
588 PUSH_DATA (push
, 0x3c);
590 if (width
* height
!= elements
) {
591 offset
+= width
* height
* data_size
;
592 width
= elements
- width
* height
;
594 BEGIN_NV04(push
, NV50_3D(RT_ADDRESS_HIGH(0)), 2);
595 PUSH_DATAh(push
, buf
->bo
->offset
+ buf
->offset
+ offset
);
596 PUSH_DATA (push
, buf
->bo
->offset
+ buf
->offset
+ offset
);
597 BEGIN_NV04(push
, NV50_3D(RT_HORIZ(0)), 2);
598 PUSH_DATA (push
, NV50_3D_RT_HORIZ_LINEAR
| (width
* data_size
));
599 PUSH_DATA (push
, height
);
600 BEGIN_NI04(push
, NV50_3D(CLEAR_BUFFERS
), 1);
601 PUSH_DATA (push
, 0x3c);
604 nouveau_fence_ref(nv50
->screen
->base
.fence
.current
, &buf
->fence
);
605 nouveau_fence_ref(nv50
->screen
->base
.fence
.current
, &buf
->fence_wr
);
607 nv50
->dirty
|= NV50_NEW_FRAMEBUFFER
| NV50_NEW_SCISSOR
;
610 /* =============================== BLIT CODE ===================================
615 struct nv50_program
*fp
[NV50_BLIT_MAX_TEXTURE_TYPES
][NV50_BLIT_MODES
];
616 struct nv50_program vp
;
618 struct nv50_tsc_entry sampler
[2]; /* nearest, bilinear */
625 struct nv50_context
*nv50
;
626 struct nv50_program
*fp
;
630 uint8_t render_condition_enable
;
631 enum pipe_texture_target target
;
633 struct pipe_framebuffer_state fb
;
634 struct nv50_rasterizer_stateobj
*rast
;
635 struct nv50_program
*vp
;
636 struct nv50_program
*gp
;
637 struct nv50_program
*fp
;
638 unsigned num_textures
[3];
639 unsigned num_samplers
[3];
640 struct pipe_sampler_view
*texture
[2];
641 struct nv50_tsc_entry
*sampler
[2];
642 unsigned min_samples
;
645 struct nv50_rasterizer_stateobj rast
;
649 nv50_blitter_make_vp(struct nv50_blitter
*blit
)
651 static const uint32_t code
[] =
653 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
654 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
655 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
656 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
657 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
660 blit
->vp
.type
= PIPE_SHADER_VERTEX
;
661 blit
->vp
.translated
= TRUE
;
662 blit
->vp
.code
= (uint32_t *)code
; /* const_cast */
663 blit
->vp
.code_size
= sizeof(code
);
664 blit
->vp
.max_gpr
= 4;
665 blit
->vp
.max_out
= 5;
667 blit
->vp
.out
[0].mask
= 0x3;
668 blit
->vp
.out
[0].sn
= TGSI_SEMANTIC_POSITION
;
669 blit
->vp
.out
[1].hw
= 2;
670 blit
->vp
.out
[1].mask
= 0x7;
671 blit
->vp
.out
[1].sn
= TGSI_SEMANTIC_GENERIC
;
672 blit
->vp
.out
[1].si
= 0;
673 blit
->vp
.vp
.attrs
[0] = 0x73;
674 blit
->vp
.vp
.psiz
= 0x40;
675 blit
->vp
.vp
.edgeflag
= 0x40;
679 nv50_blitter_make_fp(struct pipe_context
*pipe
,
681 enum pipe_texture_target ptarg
)
683 struct ureg_program
*ureg
;
686 struct ureg_dst data
;
688 const unsigned target
= nv50_blit_get_tgsi_texture_target(ptarg
);
690 boolean tex_rgbaz
= FALSE
;
691 boolean tex_s
= FALSE
;
692 boolean cvt_un8
= FALSE
;
694 if (mode
!= NV50_BLIT_MODE_PASS
&&
695 mode
!= NV50_BLIT_MODE_Z24X8
&&
696 mode
!= NV50_BLIT_MODE_X8Z24
)
699 if (mode
!= NV50_BLIT_MODE_X24S8
&&
700 mode
!= NV50_BLIT_MODE_S8X24
&&
701 mode
!= NV50_BLIT_MODE_XS
)
704 if (mode
!= NV50_BLIT_MODE_PASS
&&
705 mode
!= NV50_BLIT_MODE_ZS
&&
706 mode
!= NV50_BLIT_MODE_XS
)
709 ureg
= ureg_create(TGSI_PROCESSOR_FRAGMENT
);
713 out
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_COLOR
, 0);
714 tc
= ureg_DECL_fs_input(
715 ureg
, TGSI_SEMANTIC_GENERIC
, 0, TGSI_INTERPOLATE_LINEAR
);
717 if (ptarg
== PIPE_TEXTURE_1D_ARRAY
) {
718 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
719 tc
= ureg_swizzle(tc
, TGSI_SWIZZLE_X
, TGSI_SWIZZLE_Z
,
720 TGSI_SWIZZLE_Z
, TGSI_SWIZZLE_Z
);
723 data
= ureg_DECL_temporary(ureg
);
726 ureg_TEX(ureg
, ureg_writemask(data
, TGSI_WRITEMASK_X
),
727 target
, tc
, ureg_DECL_sampler(ureg
, 1));
728 ureg_MOV(ureg
, ureg_writemask(data
, TGSI_WRITEMASK_Y
),
729 ureg_scalar(ureg_src(data
), TGSI_SWIZZLE_X
));
732 const unsigned mask
= (mode
== NV50_BLIT_MODE_PASS
) ?
733 TGSI_WRITEMASK_XYZW
: TGSI_WRITEMASK_X
;
734 ureg_TEX(ureg
, ureg_writemask(data
, mask
),
735 target
, tc
, ureg_DECL_sampler(ureg
, 0));
739 struct ureg_src mask
;
740 struct ureg_src scale
;
741 struct ureg_dst outz
;
742 struct ureg_dst outs
;
743 struct ureg_dst zdst3
= ureg_writemask(data
, TGSI_WRITEMASK_XYZ
);
744 struct ureg_dst zdst
= ureg_writemask(data
, TGSI_WRITEMASK_X
);
745 struct ureg_dst sdst
= ureg_writemask(data
, TGSI_WRITEMASK_Y
);
746 struct ureg_src zsrc3
= ureg_src(data
);
747 struct ureg_src zsrc
= ureg_scalar(zsrc3
, TGSI_SWIZZLE_X
);
748 struct ureg_src ssrc
= ureg_scalar(zsrc3
, TGSI_SWIZZLE_Y
);
749 struct ureg_src zshuf
;
751 mask
= ureg_imm3u(ureg
, 0x0000ff, 0x00ff00, 0xff0000);
752 scale
= ureg_imm4f(ureg
,
753 1.0f
/ 0x0000ff, 1.0f
/ 0x00ff00, 1.0f
/ 0xff0000,
756 if (mode
== NV50_BLIT_MODE_Z24S8
||
757 mode
== NV50_BLIT_MODE_X24S8
||
758 mode
== NV50_BLIT_MODE_Z24X8
) {
759 outz
= ureg_writemask(out
, TGSI_WRITEMASK_XYZ
);
760 outs
= ureg_writemask(out
, TGSI_WRITEMASK_W
);
761 zshuf
= ureg_src(data
);
763 outz
= ureg_writemask(out
, TGSI_WRITEMASK_YZW
);
764 outs
= ureg_writemask(out
, TGSI_WRITEMASK_X
);
765 zshuf
= ureg_swizzle(zsrc3
, TGSI_SWIZZLE_W
,
766 TGSI_SWIZZLE_X
, TGSI_SWIZZLE_Y
, TGSI_SWIZZLE_Z
);
770 ureg_I2F(ureg
, sdst
, ssrc
);
771 ureg_MUL(ureg
, outs
, ssrc
, ureg_scalar(scale
, TGSI_SWIZZLE_X
));
775 ureg_MUL(ureg
, zdst
, zsrc
, ureg_scalar(scale
, TGSI_SWIZZLE_W
));
776 ureg_F2I(ureg
, zdst
, zsrc
);
777 ureg_AND(ureg
, zdst3
, zsrc
, mask
);
778 ureg_I2F(ureg
, zdst3
, zsrc3
);
779 ureg_MUL(ureg
, zdst3
, zsrc3
, scale
);
780 ureg_MOV(ureg
, outz
, zshuf
);
783 unsigned mask
= TGSI_WRITEMASK_XYZW
;
785 if (mode
!= NV50_BLIT_MODE_PASS
) {
786 mask
&= ~TGSI_WRITEMASK_ZW
;
788 mask
= TGSI_WRITEMASK_X
;
790 mask
= TGSI_WRITEMASK_Y
;
792 ureg_MOV(ureg
, ureg_writemask(out
, mask
), ureg_src(data
));
796 return ureg_create_shader_and_destroy(ureg
, pipe
);
800 nv50_blitter_make_sampler(struct nv50_blitter
*blit
)
802 /* clamp to edge, min/max lod = 0, nearest filtering */
804 blit
->sampler
[0].id
= -1;
806 blit
->sampler
[0].tsc
[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED
|
807 (NV50_TSC_WRAP_CLAMP_TO_EDGE
<< NV50_TSC_0_WRAPS__SHIFT
) |
808 (NV50_TSC_WRAP_CLAMP_TO_EDGE
<< NV50_TSC_0_WRAPT__SHIFT
) |
809 (NV50_TSC_WRAP_CLAMP_TO_EDGE
<< NV50_TSC_0_WRAPR__SHIFT
);
810 blit
->sampler
[0].tsc
[1] =
811 NV50_TSC_1_MAGF_NEAREST
| NV50_TSC_1_MINF_NEAREST
| NV50_TSC_1_MIPF_NONE
;
813 /* clamp to edge, min/max lod = 0, bilinear filtering */
815 blit
->sampler
[1].id
= -1;
817 blit
->sampler
[1].tsc
[0] = blit
->sampler
[0].tsc
[0];
818 blit
->sampler
[1].tsc
[1] =
819 NV50_TSC_1_MAGF_LINEAR
| NV50_TSC_1_MINF_LINEAR
| NV50_TSC_1_MIPF_NONE
;
823 nv50_blit_select_mode(const struct pipe_blit_info
*info
)
825 const unsigned mask
= info
->mask
;
827 switch (info
->dst
.resource
->format
) {
828 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
829 case PIPE_FORMAT_Z24X8_UNORM
:
830 switch (mask
& PIPE_MASK_ZS
) {
831 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_Z24S8
;
832 case PIPE_MASK_Z
: return NV50_BLIT_MODE_Z24X8
;
834 return NV50_BLIT_MODE_X24S8
;
836 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
837 switch (mask
& PIPE_MASK_ZS
) {
838 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_S8Z24
;
839 case PIPE_MASK_Z
: return NV50_BLIT_MODE_X8Z24
;
841 return NV50_BLIT_MODE_S8X24
;
843 case PIPE_FORMAT_Z32_FLOAT
:
844 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
845 switch (mask
& PIPE_MASK_ZS
) {
846 case PIPE_MASK_ZS
: return NV50_BLIT_MODE_ZS
;
847 case PIPE_MASK_Z
: return NV50_BLIT_MODE_PASS
;
849 return NV50_BLIT_MODE_XS
;
852 return NV50_BLIT_MODE_PASS
;
857 nv50_blit_select_fp(struct nv50_blitctx
*ctx
, const struct pipe_blit_info
*info
)
859 struct nv50_blitter
*blitter
= ctx
->nv50
->screen
->blitter
;
861 const enum pipe_texture_target ptarg
=
862 nv50_blit_reinterpret_pipe_texture_target(info
->src
.resource
->target
);
864 const unsigned targ
= nv50_blit_texture_type(ptarg
);
865 const unsigned mode
= ctx
->mode
;
867 if (!blitter
->fp
[targ
][mode
]) {
868 pipe_mutex_lock(blitter
->mutex
);
869 if (!blitter
->fp
[targ
][mode
])
870 blitter
->fp
[targ
][mode
] =
871 nv50_blitter_make_fp(&ctx
->nv50
->base
.pipe
, mode
, ptarg
);
872 pipe_mutex_unlock(blitter
->mutex
);
874 ctx
->fp
= blitter
->fp
[targ
][mode
];
878 nv50_blit_set_dst(struct nv50_blitctx
*ctx
,
879 struct pipe_resource
*res
, unsigned level
, unsigned layer
,
880 enum pipe_format format
)
882 struct nv50_context
*nv50
= ctx
->nv50
;
883 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
884 struct pipe_surface templ
;
886 if (util_format_is_depth_or_stencil(format
))
887 templ
.format
= nv50_blit_zeta_to_colour_format(format
);
889 templ
.format
= format
;
891 templ
.u
.tex
.level
= level
;
892 templ
.u
.tex
.first_layer
= templ
.u
.tex
.last_layer
= layer
;
895 templ
.u
.tex
.first_layer
= 0;
896 templ
.u
.tex
.last_layer
=
897 (res
->target
== PIPE_TEXTURE_3D
? res
->depth0
: res
->array_size
) - 1;
900 nv50
->framebuffer
.cbufs
[0] = nv50_miptree_surface_new(pipe
, res
, &templ
);
901 nv50
->framebuffer
.nr_cbufs
= 1;
902 nv50
->framebuffer
.zsbuf
= NULL
;
903 nv50
->framebuffer
.width
= nv50
->framebuffer
.cbufs
[0]->width
;
904 nv50
->framebuffer
.height
= nv50
->framebuffer
.cbufs
[0]->height
;
908 nv50_blit_set_src(struct nv50_blitctx
*blit
,
909 struct pipe_resource
*res
, unsigned level
, unsigned layer
,
910 enum pipe_format format
, const uint8_t filter
)
912 struct nv50_context
*nv50
= blit
->nv50
;
913 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
914 struct pipe_sampler_view templ
;
916 enum pipe_texture_target target
;
918 target
= nv50_blit_reinterpret_pipe_texture_target(res
->target
);
920 templ
.format
= format
;
921 templ
.u
.tex
.first_level
= templ
.u
.tex
.last_level
= level
;
922 templ
.u
.tex
.first_layer
= templ
.u
.tex
.last_layer
= layer
;
923 templ
.swizzle_r
= PIPE_SWIZZLE_RED
;
924 templ
.swizzle_g
= PIPE_SWIZZLE_GREEN
;
925 templ
.swizzle_b
= PIPE_SWIZZLE_BLUE
;
926 templ
.swizzle_a
= PIPE_SWIZZLE_ALPHA
;
929 templ
.u
.tex
.first_layer
= 0;
930 templ
.u
.tex
.last_layer
=
931 (res
->target
== PIPE_TEXTURE_3D
? res
->depth0
: res
->array_size
) - 1;
934 flags
= res
->last_level
? 0 : NV50_TEXVIEW_SCALED_COORDS
;
935 flags
|= NV50_TEXVIEW_ACCESS_RESOLVE
;
936 if (filter
&& res
->nr_samples
== 8)
937 flags
|= NV50_TEXVIEW_FILTER_MSAA8
;
939 nv50
->textures
[2][0] = nv50_create_texture_view(
940 pipe
, res
, &templ
, flags
, target
);
941 nv50
->textures
[2][1] = NULL
;
943 nv50
->num_textures
[0] = nv50
->num_textures
[1] = 0;
944 nv50
->num_textures
[2] = 1;
946 templ
.format
= nv50_zs_to_s_format(format
);
947 if (templ
.format
!= res
->format
) {
948 nv50
->textures
[2][1] = nv50_create_texture_view(
949 pipe
, res
, &templ
, flags
, target
);
950 nv50
->num_textures
[2] = 2;
955 nv50_blitctx_prepare_state(struct nv50_blitctx
*blit
)
957 struct nouveau_pushbuf
*push
= blit
->nv50
->base
.pushbuf
;
959 if (blit
->nv50
->cond_query
&& !blit
->render_condition_enable
) {
960 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
961 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
965 BEGIN_NV04(push
, NV50_3D(COLOR_MASK(0)), 1);
966 PUSH_DATA (push
, blit
->color_mask
);
967 BEGIN_NV04(push
, NV50_3D(BLEND_ENABLE(0)), 1);
969 BEGIN_NV04(push
, NV50_3D(LOGIC_OP_ENABLE
), 1);
972 /* rasterizer state */
973 #ifndef NV50_SCISSORS_CLIPPING
974 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(0)), 1);
977 BEGIN_NV04(push
, NV50_3D(VERTEX_TWO_SIDE_ENABLE
), 1);
979 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
981 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
983 BEGIN_NV04(push
, NV50_3D(MSAA_MASK(0)), 4);
984 PUSH_DATA (push
, 0xffff);
985 PUSH_DATA (push
, 0xffff);
986 PUSH_DATA (push
, 0xffff);
987 PUSH_DATA (push
, 0xffff);
988 BEGIN_NV04(push
, NV50_3D(POLYGON_MODE_FRONT
), 3);
989 PUSH_DATA (push
, NV50_3D_POLYGON_MODE_FRONT_FILL
);
990 PUSH_DATA (push
, NV50_3D_POLYGON_MODE_BACK_FILL
);
992 BEGIN_NV04(push
, NV50_3D(CULL_FACE_ENABLE
), 1);
994 BEGIN_NV04(push
, NV50_3D(POLYGON_STIPPLE_ENABLE
), 1);
996 BEGIN_NV04(push
, NV50_3D(POLYGON_OFFSET_FILL_ENABLE
), 1);
1000 BEGIN_NV04(push
, NV50_3D(DEPTH_TEST_ENABLE
), 1);
1001 PUSH_DATA (push
, 0);
1002 BEGIN_NV04(push
, NV50_3D(STENCIL_ENABLE
), 1);
1003 PUSH_DATA (push
, 0);
1004 BEGIN_NV04(push
, NV50_3D(ALPHA_TEST_ENABLE
), 1);
1005 PUSH_DATA (push
, 0);
1009 nv50_blitctx_pre_blit(struct nv50_blitctx
*ctx
)
1011 struct nv50_context
*nv50
= ctx
->nv50
;
1012 struct nv50_blitter
*blitter
= nv50
->screen
->blitter
;
1015 ctx
->saved
.fb
.width
= nv50
->framebuffer
.width
;
1016 ctx
->saved
.fb
.height
= nv50
->framebuffer
.height
;
1017 ctx
->saved
.fb
.nr_cbufs
= nv50
->framebuffer
.nr_cbufs
;
1018 ctx
->saved
.fb
.cbufs
[0] = nv50
->framebuffer
.cbufs
[0];
1019 ctx
->saved
.fb
.zsbuf
= nv50
->framebuffer
.zsbuf
;
1021 ctx
->saved
.rast
= nv50
->rast
;
1023 ctx
->saved
.vp
= nv50
->vertprog
;
1024 ctx
->saved
.gp
= nv50
->gmtyprog
;
1025 ctx
->saved
.fp
= nv50
->fragprog
;
1027 ctx
->saved
.min_samples
= nv50
->min_samples
;
1029 nv50
->rast
= &ctx
->rast
;
1031 nv50
->vertprog
= &blitter
->vp
;
1032 nv50
->gmtyprog
= NULL
;
1033 nv50
->fragprog
= ctx
->fp
;
1035 for (s
= 0; s
< 3; ++s
) {
1036 ctx
->saved
.num_textures
[s
] = nv50
->num_textures
[s
];
1037 ctx
->saved
.num_samplers
[s
] = nv50
->num_samplers
[s
];
1039 ctx
->saved
.texture
[0] = nv50
->textures
[2][0];
1040 ctx
->saved
.texture
[1] = nv50
->textures
[2][1];
1041 ctx
->saved
.sampler
[0] = nv50
->samplers
[2][0];
1042 ctx
->saved
.sampler
[1] = nv50
->samplers
[2][1];
1044 nv50
->samplers
[2][0] = &blitter
->sampler
[ctx
->filter
];
1045 nv50
->samplers
[2][1] = &blitter
->sampler
[ctx
->filter
];
1047 nv50
->num_samplers
[0] = nv50
->num_samplers
[1] = 0;
1048 nv50
->num_samplers
[2] = 2;
1050 nv50
->min_samples
= 1;
1052 ctx
->saved
.dirty
= nv50
->dirty
;
1054 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_FB
);
1055 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_TEXTURES
);
1058 NV50_NEW_FRAMEBUFFER
| NV50_NEW_MIN_SAMPLES
|
1059 NV50_NEW_VERTPROG
| NV50_NEW_FRAGPROG
| NV50_NEW_GMTYPROG
|
1060 NV50_NEW_TEXTURES
| NV50_NEW_SAMPLERS
;
1064 nv50_blitctx_post_blit(struct nv50_blitctx
*blit
)
1066 struct nv50_context
*nv50
= blit
->nv50
;
1069 pipe_surface_reference(&nv50
->framebuffer
.cbufs
[0], NULL
);
1071 nv50
->framebuffer
.width
= blit
->saved
.fb
.width
;
1072 nv50
->framebuffer
.height
= blit
->saved
.fb
.height
;
1073 nv50
->framebuffer
.nr_cbufs
= blit
->saved
.fb
.nr_cbufs
;
1074 nv50
->framebuffer
.cbufs
[0] = blit
->saved
.fb
.cbufs
[0];
1075 nv50
->framebuffer
.zsbuf
= blit
->saved
.fb
.zsbuf
;
1077 nv50
->rast
= blit
->saved
.rast
;
1079 nv50
->vertprog
= blit
->saved
.vp
;
1080 nv50
->gmtyprog
= blit
->saved
.gp
;
1081 nv50
->fragprog
= blit
->saved
.fp
;
1083 nv50
->min_samples
= blit
->saved
.min_samples
;
1085 pipe_sampler_view_reference(&nv50
->textures
[2][0], NULL
);
1086 pipe_sampler_view_reference(&nv50
->textures
[2][1], NULL
);
1088 for (s
= 0; s
< 3; ++s
) {
1089 nv50
->num_textures
[s
] = blit
->saved
.num_textures
[s
];
1090 nv50
->num_samplers
[s
] = blit
->saved
.num_samplers
[s
];
1092 nv50
->textures
[2][0] = blit
->saved
.texture
[0];
1093 nv50
->textures
[2][1] = blit
->saved
.texture
[1];
1094 nv50
->samplers
[2][0] = blit
->saved
.sampler
[0];
1095 nv50
->samplers
[2][1] = blit
->saved
.sampler
[1];
1097 if (nv50
->cond_query
&& !blit
->render_condition_enable
)
1098 nv50
->base
.pipe
.render_condition(&nv50
->base
.pipe
, nv50
->cond_query
,
1099 nv50
->cond_cond
, nv50
->cond_mode
);
1101 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_FB
);
1102 nouveau_bufctx_reset(nv50
->bufctx_3d
, NV50_BIND_TEXTURES
);
1104 nv50
->dirty
= blit
->saved
.dirty
|
1105 (NV50_NEW_FRAMEBUFFER
| NV50_NEW_SCISSOR
| NV50_NEW_SAMPLE_MASK
|
1106 NV50_NEW_RASTERIZER
| NV50_NEW_ZSA
| NV50_NEW_BLEND
|
1107 NV50_NEW_TEXTURES
| NV50_NEW_SAMPLERS
|
1108 NV50_NEW_VERTPROG
| NV50_NEW_GMTYPROG
| NV50_NEW_FRAGPROG
);
1109 nv50
->scissors_dirty
|= 1;
1111 nv50
->base
.pipe
.set_min_samples(&nv50
->base
.pipe
, blit
->saved
.min_samples
);
1116 nv50_blit_3d(struct nv50_context
*nv50
, const struct pipe_blit_info
*info
)
1118 struct nv50_blitctx
*blit
= nv50
->blit
;
1119 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
1120 struct pipe_resource
*src
= info
->src
.resource
;
1121 struct pipe_resource
*dst
= info
->dst
.resource
;
1122 int32_t minx
, maxx
, miny
, maxy
;
1124 float x0
, x1
, y0
, y1
, z
;
1126 float x_range
, y_range
;
1129 blit
->mode
= nv50_blit_select_mode(info
);
1130 blit
->color_mask
= nv50_blit_derive_color_mask(info
);
1131 blit
->filter
= nv50_blit_get_filter(info
);
1132 blit
->render_condition_enable
= info
->render_condition_enable
;
1134 nv50_blit_select_fp(blit
, info
);
1135 nv50_blitctx_pre_blit(blit
);
1137 nv50_blit_set_dst(blit
, dst
, info
->dst
.level
, -1, info
->dst
.format
);
1138 nv50_blit_set_src(blit
, src
, info
->src
.level
, -1, info
->src
.format
,
1141 nv50_blitctx_prepare_state(blit
);
1143 nv50_state_validate(nv50
, ~0, 36);
1145 x_range
= (float)info
->src
.box
.width
/ (float)info
->dst
.box
.width
;
1146 y_range
= (float)info
->src
.box
.height
/ (float)info
->dst
.box
.height
;
1148 tri_x
= 16384 << nv50_miptree(dst
)->ms_x
;
1149 tri_y
= 16384 << nv50_miptree(dst
)->ms_y
;
1151 x0
= (float)info
->src
.box
.x
- x_range
* (float)info
->dst
.box
.x
;
1152 y0
= (float)info
->src
.box
.y
- y_range
* (float)info
->dst
.box
.y
;
1154 x1
= x0
+ tri_x
* x_range
;
1155 y1
= y0
+ tri_y
* y_range
;
1157 x0
*= (float)(1 << nv50_miptree(src
)->ms_x
);
1158 x1
*= (float)(1 << nv50_miptree(src
)->ms_x
);
1159 y0
*= (float)(1 << nv50_miptree(src
)->ms_y
);
1160 y1
*= (float)(1 << nv50_miptree(src
)->ms_y
);
1162 /* XXX: multiply by 6 for cube arrays ? */
1163 dz
= (float)info
->src
.box
.depth
/ (float)info
->dst
.box
.depth
;
1164 z
= (float)info
->src
.box
.z
;
1165 if (nv50_miptree(src
)->layout_3d
)
1168 if (src
->last_level
> 0) {
1169 /* If there are mip maps, GPU always assumes normalized coordinates. */
1170 const unsigned l
= info
->src
.level
;
1171 const float fh
= u_minify(src
->width0
<< nv50_miptree(src
)->ms_x
, l
);
1172 const float fv
= u_minify(src
->height0
<< nv50_miptree(src
)->ms_y
, l
);
1177 if (nv50_miptree(src
)->layout_3d
) {
1178 z
/= u_minify(src
->depth0
, l
);
1179 dz
/= u_minify(src
->depth0
, l
);
1183 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
1184 PUSH_DATA (push
, 0);
1185 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
1186 PUSH_DATA (push
, 0x1);
1188 /* Draw a large triangle in screen coordinates covering the whole
1189 * render target, with scissors defining the destination region.
1190 * The vertex is supplied with non-normalized texture coordinates
1191 * arranged in a way to yield the desired offset and scale.
1194 minx
= info
->dst
.box
.x
;
1195 maxx
= info
->dst
.box
.x
+ info
->dst
.box
.width
;
1196 miny
= info
->dst
.box
.y
;
1197 maxy
= info
->dst
.box
.y
+ info
->dst
.box
.height
;
1198 if (info
->scissor_enable
) {
1199 minx
= MAX2(minx
, info
->scissor
.minx
);
1200 maxx
= MIN2(maxx
, info
->scissor
.maxx
);
1201 miny
= MAX2(miny
, info
->scissor
.miny
);
1202 maxy
= MIN2(maxy
, info
->scissor
.maxy
);
1204 BEGIN_NV04(push
, NV50_3D(SCISSOR_HORIZ(0)), 2);
1205 PUSH_DATA (push
, (maxx
<< 16) | minx
);
1206 PUSH_DATA (push
, (maxy
<< 16) | miny
);
1208 for (i
= 0; i
< info
->dst
.box
.depth
; ++i
, z
+= dz
) {
1209 if (info
->dst
.box
.z
+ i
) {
1210 BEGIN_NV04(push
, NV50_3D(LAYER
), 1);
1211 PUSH_DATA (push
, info
->dst
.box
.z
+ i
);
1213 PUSH_SPACE(push
, 32);
1214 BEGIN_NV04(push
, NV50_3D(VERTEX_BEGIN_GL
), 1);
1215 PUSH_DATA (push
, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES
);
1216 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1217 PUSH_DATAf(push
, x0
);
1218 PUSH_DATAf(push
, y0
);
1219 PUSH_DATAf(push
, z
);
1220 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1221 PUSH_DATAf(push
, 0.0f
);
1222 PUSH_DATAf(push
, 0.0f
);
1223 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1224 PUSH_DATAf(push
, x1
);
1225 PUSH_DATAf(push
, y0
);
1226 PUSH_DATAf(push
, z
);
1227 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1228 PUSH_DATAf(push
, tri_x
);
1229 PUSH_DATAf(push
, 0.0f
);
1230 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1231 PUSH_DATAf(push
, x0
);
1232 PUSH_DATAf(push
, y1
);
1233 PUSH_DATAf(push
, z
);
1234 BEGIN_NV04(push
, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1235 PUSH_DATAf(push
, 0.0f
);
1236 PUSH_DATAf(push
, tri_y
);
1237 BEGIN_NV04(push
, NV50_3D(VERTEX_END_GL
), 1);
1238 PUSH_DATA (push
, 0);
1240 if (info
->dst
.box
.z
+ info
->dst
.box
.depth
- 1) {
1241 BEGIN_NV04(push
, NV50_3D(LAYER
), 1);
1242 PUSH_DATA (push
, 0);
1245 /* re-enable normally constant state */
1247 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
1248 PUSH_DATA (push
, 1);
1250 nv50_blitctx_post_blit(blit
);
1254 nv50_blit_eng2d(struct nv50_context
*nv50
, const struct pipe_blit_info
*info
)
1256 struct nouveau_pushbuf
*push
= nv50
->base
.pushbuf
;
1257 struct nv50_miptree
*dst
= nv50_miptree(info
->dst
.resource
);
1258 struct nv50_miptree
*src
= nv50_miptree(info
->src
.resource
);
1259 const int32_t srcx_adj
= info
->src
.box
.width
< 0 ? -1 : 0;
1260 const int32_t srcy_adj
= info
->src
.box
.height
< 0 ? -1 : 0;
1261 const int32_t dz
= info
->dst
.box
.z
;
1262 const int32_t sz
= info
->src
.box
.z
;
1263 uint32_t dstw
, dsth
;
1266 int64_t du_dx
, dv_dy
;
1269 uint32_t mask
= nv50_blit_eng2d_get_mask(info
);
1272 mode
= nv50_blit_get_filter(info
) ?
1273 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR
:
1274 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE
;
1275 mode
|= (src
->base
.base
.nr_samples
> dst
->base
.base
.nr_samples
) ?
1276 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER
: NV50_2D_BLIT_CONTROL_ORIGIN_CENTER
;
1278 du_dx
= ((int64_t)info
->src
.box
.width
<< 32) / info
->dst
.box
.width
;
1279 dv_dy
= ((int64_t)info
->src
.box
.height
<< 32) / info
->dst
.box
.height
;
1281 b
= info
->dst
.format
== info
->src
.format
;
1282 nv50_2d_texture_set(push
, 1, dst
, info
->dst
.level
, dz
, info
->dst
.format
, b
);
1283 nv50_2d_texture_set(push
, 0, src
, info
->src
.level
, sz
, info
->src
.format
, b
);
1285 if (info
->scissor_enable
) {
1286 BEGIN_NV04(push
, NV50_2D(CLIP_X
), 5);
1287 PUSH_DATA (push
, info
->scissor
.minx
<< dst
->ms_x
);
1288 PUSH_DATA (push
, info
->scissor
.miny
<< dst
->ms_y
);
1289 PUSH_DATA (push
, (info
->scissor
.maxx
- info
->scissor
.minx
) << dst
->ms_x
);
1290 PUSH_DATA (push
, (info
->scissor
.maxy
- info
->scissor
.miny
) << dst
->ms_y
);
1291 PUSH_DATA (push
, 1); /* enable */
1294 if (nv50
->cond_query
&& info
->render_condition_enable
) {
1295 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
1296 PUSH_DATA (push
, NV50_2D_COND_MODE_RES_NON_ZERO
);
1299 if (mask
!= 0xffffffff) {
1300 BEGIN_NV04(push
, NV50_2D(ROP
), 1);
1301 PUSH_DATA (push
, 0xca); /* DPSDxax */
1302 BEGIN_NV04(push
, NV50_2D(PATTERN_COLOR_FORMAT
), 1);
1303 PUSH_DATA (push
, NV50_2D_PATTERN_COLOR_FORMAT_32BPP
);
1304 BEGIN_NV04(push
, NV50_2D(PATTERN_COLOR(0)), 4);
1305 PUSH_DATA (push
, 0x00000000);
1306 PUSH_DATA (push
, mask
);
1307 PUSH_DATA (push
, 0xffffffff);
1308 PUSH_DATA (push
, 0xffffffff);
1309 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
1310 PUSH_DATA (push
, NV50_2D_OPERATION_ROP
);
1312 if (info
->src
.format
!= info
->dst
.format
) {
1313 if (info
->src
.format
== PIPE_FORMAT_R8_UNORM
||
1314 info
->src
.format
== PIPE_FORMAT_R16_UNORM
||
1315 info
->src
.format
== PIPE_FORMAT_R16_FLOAT
||
1316 info
->src
.format
== PIPE_FORMAT_R32_FLOAT
) {
1317 mask
= 0xffff0000; /* also makes condition for OPERATION reset true */
1318 BEGIN_NV04(push
, NV50_2D(BETA4
), 2);
1319 PUSH_DATA (push
, mask
);
1320 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY_PREMULT
);
1324 if (src
->ms_x
> dst
->ms_x
|| src
->ms_y
> dst
->ms_y
) {
1325 /* ms_x is always >= ms_y */
1326 du_dx
<<= src
->ms_x
- dst
->ms_x
;
1327 dv_dy
<<= src
->ms_y
- dst
->ms_y
;
1329 du_dx
>>= dst
->ms_x
- src
->ms_x
;
1330 dv_dy
>>= dst
->ms_y
- src
->ms_y
;
1333 srcx
= (int64_t)(info
->src
.box
.x
+ srcx_adj
) << (src
->ms_x
+ 32);
1334 srcy
= (int64_t)(info
->src
.box
.y
+ srcy_adj
) << (src
->ms_y
+ 32);
1336 if (src
->base
.base
.nr_samples
> dst
->base
.base
.nr_samples
) {
1337 /* center src coorinates for proper MS resolve filtering */
1338 srcx
+= (int64_t)1 << (src
->ms_x
+ 31);
1339 srcy
+= (int64_t)1 << (src
->ms_y
+ 31);
1342 dstx
= info
->dst
.box
.x
<< dst
->ms_x
;
1343 dsty
= info
->dst
.box
.y
<< dst
->ms_y
;
1345 dstw
= info
->dst
.box
.width
<< dst
->ms_x
;
1346 dsth
= info
->dst
.box
.height
<< dst
->ms_y
;
1350 srcx
-= du_dx
* dstx
;
1355 srcy
-= dv_dy
* dsty
;
1359 BEGIN_NV04(push
, NV50_2D(BLIT_CONTROL
), 1);
1360 PUSH_DATA (push
, mode
);
1361 BEGIN_NV04(push
, NV50_2D(BLIT_DST_X
), 4);
1362 PUSH_DATA (push
, dstx
);
1363 PUSH_DATA (push
, dsty
);
1364 PUSH_DATA (push
, dstw
);
1365 PUSH_DATA (push
, dsth
);
1366 BEGIN_NV04(push
, NV50_2D(BLIT_DU_DX_FRACT
), 4);
1367 PUSH_DATA (push
, du_dx
);
1368 PUSH_DATA (push
, du_dx
>> 32);
1369 PUSH_DATA (push
, dv_dy
);
1370 PUSH_DATA (push
, dv_dy
>> 32);
1372 BCTX_REFN(nv50
->bufctx
, 2D
, &dst
->base
, WR
);
1373 BCTX_REFN(nv50
->bufctx
, 2D
, &src
->base
, RD
);
1374 nouveau_pushbuf_bufctx(nv50
->base
.pushbuf
, nv50
->bufctx
);
1375 if (nouveau_pushbuf_validate(nv50
->base
.pushbuf
))
1378 for (i
= 0; i
< info
->dst
.box
.depth
; ++i
) {
1380 /* no scaling in z-direction possible for eng2d blits */
1381 if (dst
->layout_3d
) {
1382 BEGIN_NV04(push
, NV50_2D(DST_LAYER
), 1);
1383 PUSH_DATA (push
, info
->dst
.box
.z
+ i
);
1385 const unsigned z
= info
->dst
.box
.z
+ i
;
1386 BEGIN_NV04(push
, NV50_2D(DST_ADDRESS_HIGH
), 2);
1387 PUSH_DATAh(push
, dst
->base
.address
+ z
* dst
->layer_stride
);
1388 PUSH_DATA (push
, dst
->base
.address
+ z
* dst
->layer_stride
);
1390 if (src
->layout_3d
) {
1391 /* not possible because of depth tiling */
1394 const unsigned z
= info
->src
.box
.z
+ i
;
1395 BEGIN_NV04(push
, NV50_2D(SRC_ADDRESS_HIGH
), 2);
1396 PUSH_DATAh(push
, src
->base
.address
+ z
* src
->layer_stride
);
1397 PUSH_DATA (push
, src
->base
.address
+ z
* src
->layer_stride
);
1399 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_Y_INT
), 1); /* trigger */
1400 PUSH_DATA (push
, srcy
>> 32);
1402 BEGIN_NV04(push
, NV50_2D(BLIT_SRC_X_FRACT
), 4);
1403 PUSH_DATA (push
, srcx
);
1404 PUSH_DATA (push
, srcx
>> 32);
1405 PUSH_DATA (push
, srcy
);
1406 PUSH_DATA (push
, srcy
>> 32);
1409 nv50_bufctx_fence(nv50
->bufctx
, FALSE
);
1411 nouveau_bufctx_reset(nv50
->bufctx
, NV50_BIND_2D
);
1413 if (info
->scissor_enable
) {
1414 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
1415 PUSH_DATA (push
, 0);
1417 if (mask
!= 0xffffffff) {
1418 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
1419 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
1421 if (nv50
->cond_query
&& info
->render_condition_enable
) {
1422 BEGIN_NV04(push
, NV50_2D(COND_MODE
), 1);
1423 PUSH_DATA (push
, NV50_2D_COND_MODE_ALWAYS
);
1428 nv50_blit(struct pipe_context
*pipe
, const struct pipe_blit_info
*info
)
1430 struct nv50_context
*nv50
= nv50_context(pipe
);
1431 boolean eng3d
= FALSE
;
1433 if (util_format_is_depth_or_stencil(info
->dst
.resource
->format
)) {
1434 if (!(info
->mask
& PIPE_MASK_ZS
))
1436 if (info
->dst
.resource
->format
== PIPE_FORMAT_Z32_FLOAT
||
1437 info
->dst
.resource
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)
1439 if (info
->filter
!= PIPE_TEX_FILTER_NEAREST
)
1442 if (!(info
->mask
& PIPE_MASK_RGBA
))
1444 if (info
->mask
!= PIPE_MASK_RGBA
)
1448 if (nv50_miptree(info
->src
.resource
)->layout_3d
) {
1451 if (info
->src
.box
.depth
!= info
->dst
.box
.depth
) {
1453 debug_printf("blit: cannot filter array or cube textures in z direction");
1456 if (!eng3d
&& info
->dst
.format
!= info
->src
.format
) {
1457 if (!nv50_2d_dst_format_faithful(info
->dst
.format
) ||
1458 !nv50_2d_src_format_faithful(info
->src
.format
)) {
1461 if (!nv50_2d_src_format_faithful(info
->src
.format
)) {
1462 if (!util_format_is_luminance(info
->src
.format
)) {
1463 if (util_format_is_intensity(info
->src
.format
))
1466 if (!nv50_2d_dst_format_ops_supported(info
->dst
.format
))
1469 eng3d
= !nv50_2d_format_supported(info
->src
.format
);
1472 if (util_format_is_luminance_alpha(info
->src
.format
))
1476 if (info
->src
.resource
->nr_samples
== 8 &&
1477 info
->dst
.resource
->nr_samples
<= 1)
1480 /* FIXME: can't make this work with eng2d anymore */
1481 if ((info
->src
.resource
->nr_samples
| 1) !=
1482 (info
->dst
.resource
->nr_samples
| 1))
1485 /* FIXME: find correct src coordinate adjustments */
1486 if ((info
->src
.box
.width
!= info
->dst
.box
.width
&&
1487 info
->src
.box
.width
!= -info
->dst
.box
.width
) ||
1488 (info
->src
.box
.height
!= info
->dst
.box
.height
&&
1489 info
->src
.box
.height
!= -info
->dst
.box
.height
))
1493 nv50_blit_eng2d(nv50
, info
);
1495 nv50_blit_3d(nv50
, info
);
1499 nv50_flush_resource(struct pipe_context
*ctx
,
1500 struct pipe_resource
*resource
)
1505 nv50_blitter_create(struct nv50_screen
*screen
)
1507 screen
->blitter
= CALLOC_STRUCT(nv50_blitter
);
1508 if (!screen
->blitter
) {
1509 NOUVEAU_ERR("failed to allocate blitter struct\n");
1513 pipe_mutex_init(screen
->blitter
->mutex
);
1515 nv50_blitter_make_vp(screen
->blitter
);
1516 nv50_blitter_make_sampler(screen
->blitter
);
1522 nv50_blitter_destroy(struct nv50_screen
*screen
)
1524 struct nv50_blitter
*blitter
= screen
->blitter
;
1527 for (i
= 0; i
< NV50_BLIT_MAX_TEXTURE_TYPES
; ++i
) {
1528 for (m
= 0; m
< NV50_BLIT_MODES
; ++m
) {
1529 struct nv50_program
*prog
= blitter
->fp
[i
][m
];
1531 nv50_program_destroy(NULL
, prog
);
1532 FREE((void *)prog
->pipe
.tokens
);
1542 nv50_blitctx_create(struct nv50_context
*nv50
)
1544 nv50
->blit
= CALLOC_STRUCT(nv50_blitctx
);
1546 NOUVEAU_ERR("failed to allocate blit context\n");
1550 nv50
->blit
->nv50
= nv50
;
1552 nv50
->blit
->rast
.pipe
.half_pixel_center
= 1;
1558 nv50_init_surface_functions(struct nv50_context
*nv50
)
1560 struct pipe_context
*pipe
= &nv50
->base
.pipe
;
1562 pipe
->resource_copy_region
= nv50_resource_copy_region
;
1563 pipe
->blit
= nv50_blit
;
1564 pipe
->flush_resource
= nv50_flush_resource
;
1565 pipe
->clear_render_target
= nv50_clear_render_target
;
1566 pipe
->clear_depth_stencil
= nv50_clear_depth_stencil
;
1567 pipe
->clear_buffer
= nv50_clear_buffer
;