projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nv50: add ARB_copy_image support
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "tgsi/tgsi_ureg.h"
33
34 #include "os/os_thread.h"
35
36 #include "nv50/nv50_context.h"
37 #include "nv50/nv50_resource.h"
38
39 #include "nv50/nv50_defs.xml.h"
40 #include "nv50/nv50_texture.xml.h"
41
42 /* these are used in nv50_blit.h */
43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
44 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
45 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
47 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
48
49 #define NOUVEAU_DRIVER 0x50
50 #include "nv50/nv50_blit.h"
51
52 static inline uint8_t
53 nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
54 {
55 uint8_t id = nv50_format_table[format].rt;
56
57 /* Hardware values for color formats range from 0xc0 to 0xff,
58 * but the 2D engine doesn't support all of them.
59 */
60 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
61 return id;
62 assert(dst_src_equal);
63
64 switch (util_format_get_blocksize(format)) {
65 case 1:
66 return NV50_SURFACE_FORMAT_R8_UNORM;
67 case 2:
68 return NV50_SURFACE_FORMAT_R16_UNORM;
69 case 4:
70 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
71 case 8:
72 return NV50_SURFACE_FORMAT_RGBA16_FLOAT;
73 case 16:
74 return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
75 default:
76 return 0;
77 }
78 }
79
80 static int
81 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
82 struct nv50_miptree *mt, unsigned level, unsigned layer,
83 enum pipe_format pformat, bool dst_src_pformat_equal)
84 {
85 struct nouveau_bo *bo = mt->base.bo;
86 uint32_t width, height, depth;
87 uint32_t format;
88 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
89 uint32_t offset = mt->level[level].offset;
90
91 format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
92 if (!format) {
93 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
94 util_format_name(pformat));
95 return 1;
96 }
97
98 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
99 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
100 depth = u_minify(mt->base.base.depth0, level);
101
102 offset = mt->level[level].offset;
103 if (!mt->layout_3d) {
104 offset += mt->layer_stride * layer;
105 depth = 1;
106 layer = 0;
107 } else
108 if (!dst) {
109 offset += nv50_mt_zslice_offset(mt, level, layer);
110 layer = 0;
111 }
112
113 if (!nouveau_bo_memtype(bo)) {
114 BEGIN_NV04(push, SUBC_2D(mthd), 2);
115 PUSH_DATA (push, format);
116 PUSH_DATA (push, 1);
117 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
118 PUSH_DATA (push, mt->level[level].pitch);
119 PUSH_DATA (push, width);
120 PUSH_DATA (push, height);
121 PUSH_DATAh(push, mt->base.address + offset);
122 PUSH_DATA (push, mt->base.address + offset);
123 } else {
124 BEGIN_NV04(push, SUBC_2D(mthd), 5);
125 PUSH_DATA (push, format);
126 PUSH_DATA (push, 0);
127 PUSH_DATA (push, mt->level[level].tile_mode);
128 PUSH_DATA (push, depth);
129 PUSH_DATA (push, layer);
130 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
131 PUSH_DATA (push, width);
132 PUSH_DATA (push, height);
133 PUSH_DATAh(push, mt->base.address + offset);
134 PUSH_DATA (push, mt->base.address + offset);
135 }
136
137 #if 0
138 if (dst) {
139 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
140 PUSH_DATA (push, 0);
141 PUSH_DATA (push, 0);
142 PUSH_DATA (push, width);
143 PUSH_DATA (push, height);
144 }
145 #endif
146 return 0;
147 }
148
149 static int
150 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
151 struct nv50_miptree *dst, unsigned dst_level,
152 unsigned dx, unsigned dy, unsigned dz,
153 struct nv50_miptree *src, unsigned src_level,
154 unsigned sx, unsigned sy, unsigned sz,
155 unsigned w, unsigned h)
156 {
157 const enum pipe_format dfmt = dst->base.base.format;
158 const enum pipe_format sfmt = src->base.base.format;
159 int ret;
160 bool eqfmt = dfmt == sfmt;
161
162 if (!PUSH_SPACE(push, 2 * 16 + 32))
163 return PIPE_ERROR;
164
165 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
166 if (ret)
167 return ret;
168
169 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
170 if (ret)
171 return ret;
172
173 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
174 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
175 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
176 PUSH_DATA (push, dx << dst->ms_x);
177 PUSH_DATA (push, dy << dst->ms_y);
178 PUSH_DATA (push, w << dst->ms_x);
179 PUSH_DATA (push, h << dst->ms_y);
180 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
181 PUSH_DATA (push, 0);
182 PUSH_DATA (push, 1);
183 PUSH_DATA (push, 0);
184 PUSH_DATA (push, 1);
185 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
186 PUSH_DATA (push, 0);
187 PUSH_DATA (push, sx << src->ms_x);
188 PUSH_DATA (push, 0);
189 PUSH_DATA (push, sy << src->ms_y);
190
191 return 0;
192 }
193
194 static void
195 nv50_resource_copy_region(struct pipe_context *pipe,
196 struct pipe_resource *dst, unsigned dst_level,
197 unsigned dstx, unsigned dsty, unsigned dstz,
198 struct pipe_resource *src, unsigned src_level,
199 const struct pipe_box *src_box)
200 {
201 struct nv50_context *nv50 = nv50_context(pipe);
202 int ret;
203 bool m2mf;
204 unsigned dst_layer = dstz, src_layer = src_box->z;
205
206 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
207 nouveau_copy_buffer(&nv50->base,
208 nv04_resource(dst), dstx,
209 nv04_resource(src), src_box->x, src_box->width);
210 return;
211 }
212
213 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
214 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
215
216 m2mf = (src->format == dst->format) ||
217 (util_format_get_blocksizebits(src->format) ==
218 util_format_get_blocksizebits(dst->format));
219
220 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
221
222 if (m2mf) {
223 struct nv50_miptree *src_mt = nv50_miptree(src);
224 struct nv50_miptree *dst_mt = nv50_miptree(dst);
225 struct nv50_m2mf_rect drect, srect;
226 unsigned i;
227 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
228 << src_mt->ms_x;
229 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
230 << src_mt->ms_y;
231
232 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
233 nv50_m2mf_rect_setup(&srect, src, src_level,
234 src_box->x, src_box->y, src_box->z);
235
236 for (i = 0; i < src_box->depth; ++i) {
237 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
238
239 if (dst_mt->layout_3d)
240 drect.z++;
241 else
242 drect.base += dst_mt->layer_stride;
243
244 if (src_mt->layout_3d)
245 srect.z++;
246 else
247 srect.base += src_mt->layer_stride;
248 }
249 return;
250 }
251
252 assert((src->format == dst->format) ||
253 (nv50_2d_src_format_faithful(src->format) &&
254 nv50_2d_dst_format_faithful(dst->format)));
255
256 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
257 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
258 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
259 nouveau_pushbuf_validate(nv50->base.pushbuf);
260
261 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
262 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
263 nv50_miptree(dst), dst_level,
264 dstx, dsty, dst_layer,
265 nv50_miptree(src), src_level,
266 src_box->x, src_box->y, src_layer,
267 src_box->width, src_box->height);
268 if (ret)
269 break;
270 }
271 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
272 }
273
274 static void
275 nv50_clear_render_target(struct pipe_context *pipe,
276 struct pipe_surface *dst,
277 const union pipe_color_union *color,
278 unsigned dstx, unsigned dsty,
279 unsigned width, unsigned height)
280 {
281 struct nv50_context *nv50 = nv50_context(pipe);
282 struct nouveau_pushbuf *push = nv50->base.pushbuf;
283 struct nv50_miptree *mt = nv50_miptree(dst->texture);
284 struct nv50_surface *sf = nv50_surface(dst);
285 struct nouveau_bo *bo = mt->base.bo;
286 unsigned z;
287
288 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
289 PUSH_DATAf(push, color->f[0]);
290 PUSH_DATAf(push, color->f[1]);
291 PUSH_DATAf(push, color->f[2]);
292 PUSH_DATAf(push, color->f[3]);
293
294 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
295 return;
296
297 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
298
299 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
300 PUSH_DATA (push, ( width << 16) | dstx);
301 PUSH_DATA (push, (height << 16) | dsty);
302 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
303 PUSH_DATA (push, 8192 << 16);
304 PUSH_DATA (push, 8192 << 16);
305 nv50->scissors_dirty |= 1;
306
307 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
308 PUSH_DATA (push, 1);
309 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
310 PUSH_DATAh(push, mt->base.address + sf->offset);
311 PUSH_DATA (push, mt->base.address + sf->offset);
312 PUSH_DATA (push, nv50_format_table[dst->format].rt);
313 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
314 PUSH_DATA (push, mt->layer_stride >> 2);
315 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
316 if (nouveau_bo_memtype(bo))
317 PUSH_DATA(push, sf->width);
318 else
319 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
320 PUSH_DATA (push, sf->height);
321 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
322 if (mt->layout_3d)
323 PUSH_DATA(push, NV50_3D_RT_ARRAY_MODE_MODE_3D | 512);
324 else
325 PUSH_DATA(push, 512);
326
327 if (!nouveau_bo_memtype(bo)) {
328 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
329 PUSH_DATA (push, 0);
330 }
331
332 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
333
334 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
335 PUSH_DATA (push, (width << 16) | dstx);
336 PUSH_DATA (push, (height << 16) | dsty);
337
338 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
339 for (z = 0; z < sf->depth; ++z) {
340 PUSH_DATA (push, 0x3c |
341 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
342 }
343
344 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
345 }
346
347 static void
348 nv50_clear_depth_stencil(struct pipe_context *pipe,
349 struct pipe_surface *dst,
350 unsigned clear_flags,
351 double depth,
352 unsigned stencil,
353 unsigned dstx, unsigned dsty,
354 unsigned width, unsigned height)
355 {
356 struct nv50_context *nv50 = nv50_context(pipe);
357 struct nouveau_pushbuf *push = nv50->base.pushbuf;
358 struct nv50_miptree *mt = nv50_miptree(dst->texture);
359 struct nv50_surface *sf = nv50_surface(dst);
360 struct nouveau_bo *bo = mt->base.bo;
361 uint32_t mode = 0;
362 unsigned z;
363
364 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
365
366 if (clear_flags & PIPE_CLEAR_DEPTH) {
367 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
368 PUSH_DATAf(push, depth);
369 mode |= NV50_3D_CLEAR_BUFFERS_Z;
370 }
371
372 if (clear_flags & PIPE_CLEAR_STENCIL) {
373 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
374 PUSH_DATA (push, stencil & 0xff);
375 mode |= NV50_3D_CLEAR_BUFFERS_S;
376 }
377
378 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
379 return;
380
381 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
382
383 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
384 PUSH_DATA (push, ( width << 16) | dstx);
385 PUSH_DATA (push, (height << 16) | dsty);
386 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
387 PUSH_DATA (push, 8192 << 16);
388 PUSH_DATA (push, 8192 << 16);
389 nv50->scissors_dirty |= 1;
390
391 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
392 PUSH_DATAh(push, mt->base.address + sf->offset);
393 PUSH_DATA (push, mt->base.address + sf->offset);
394 PUSH_DATA (push, nv50_format_table[dst->format].rt);
395 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
396 PUSH_DATA (push, mt->layer_stride >> 2);
397 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
398 PUSH_DATA (push, 1);
399 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
400 PUSH_DATA (push, sf->width);
401 PUSH_DATA (push, sf->height);
402 PUSH_DATA (push, (1 << 16) | 1);
403
404 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
405 PUSH_DATA (push, 512);
406
407 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
408 PUSH_DATA (push, (width << 16) | dstx);
409 PUSH_DATA (push, (height << 16) | dsty);
410
411 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
412 for (z = 0; z < sf->depth; ++z) {
413 PUSH_DATA (push, mode |
414 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
415 }
416
417 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
418 }
419
420 void
421 nv50_clear(struct pipe_context *pipe, unsigned buffers,
422 const union pipe_color_union *color,
423 double depth, unsigned stencil)
424 {
425 struct nv50_context *nv50 = nv50_context(pipe);
426 struct nouveau_pushbuf *push = nv50->base.pushbuf;
427 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
428 unsigned i, j, k;
429 uint32_t mode = 0;
430
431 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
432 if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
433 return;
434
435 /* We have to clear ALL of the layers, not up to the min number of layers
436 * of any attachment. */
437 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
438 PUSH_DATA (push, (nv50->rt_array_mode & NV50_3D_RT_ARRAY_MODE_MODE_3D) | 512);
439
440 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
441 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
442 PUSH_DATAf(push, color->f[0]);
443 PUSH_DATAf(push, color->f[1]);
444 PUSH_DATAf(push, color->f[2]);
445 PUSH_DATAf(push, color->f[3]);
446 if (buffers & PIPE_CLEAR_COLOR0)
447 mode =
448 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
449 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
450 }
451
452 if (buffers & PIPE_CLEAR_DEPTH) {
453 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
454 PUSH_DATA (push, fui(depth));
455 mode |= NV50_3D_CLEAR_BUFFERS_Z;
456 }
457
458 if (buffers & PIPE_CLEAR_STENCIL) {
459 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
460 PUSH_DATA (push, stencil & 0xff);
461 mode |= NV50_3D_CLEAR_BUFFERS_S;
462 }
463
464 if (mode) {
465 int zs_layers = 0, color0_layers = 0;
466 if (fb->cbufs[0] && (mode & 0x3c))
467 color0_layers = fb->cbufs[0]->u.tex.last_layer -
468 fb->cbufs[0]->u.tex.first_layer + 1;
469 if (fb->zsbuf && (mode & ~0x3c))
470 zs_layers = fb->zsbuf->u.tex.last_layer -
471 fb->zsbuf->u.tex.first_layer + 1;
472
473 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
474 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
475 PUSH_DATA(push, mode | (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
476 }
477 for (k = j; k < zs_layers; k++) {
478 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
479 PUSH_DATA(push, (mode & ~0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
480 }
481 for (k = j; k < color0_layers; k++) {
482 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
483 PUSH_DATA(push, (mode & 0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
484 }
485 }
486
487 for (i = 1; i < fb->nr_cbufs; i++) {
488 struct pipe_surface *sf = fb->cbufs[i];
489 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
490 continue;
491 for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
492 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
493 PUSH_DATA (push, (i << 6) | 0x3c |
494 (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
495 }
496 }
497
498 /* restore the array mode */
499 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
500 PUSH_DATA (push, nv50->rt_array_mode);
501 }
502
503 static void
504 nv50_clear_buffer(struct pipe_context *pipe,
505 struct pipe_resource *res,
506 unsigned offset, unsigned size,
507 const void *data, int data_size)
508 {
509 struct nv50_context *nv50 = nv50_context(pipe);
510 struct nouveau_pushbuf *push = nv50->base.pushbuf;
511 struct nv04_resource *buf = (struct nv04_resource *)res;
512 union pipe_color_union color;
513 enum pipe_format dst_fmt;
514 unsigned width, height, elements;
515
516 assert(res->target == PIPE_BUFFER);
517 assert(nouveau_bo_memtype(buf->bo) == 0);
518
519 switch (data_size) {
520 case 16:
521 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
522 memcpy(&color.ui, data, 16);
523 break;
524 case 8:
525 dst_fmt = PIPE_FORMAT_R32G32_UINT;
526 memcpy(&color.ui, data, 8);
527 memset(&color.ui[2], 0, 8);
528 break;
529 case 4:
530 dst_fmt = PIPE_FORMAT_R32_UINT;
531 memcpy(&color.ui, data, 4);
532 memset(&color.ui[1], 0, 12);
533 break;
534 case 2:
535 dst_fmt = PIPE_FORMAT_R16_UINT;
536 color.ui[0] = util_cpu_to_le32(
537 util_le16_to_cpu(*(unsigned short *)data));
538 memset(&color.ui[1], 0, 12);
539 break;
540 case 1:
541 dst_fmt = PIPE_FORMAT_R8_UINT;
542 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
543 memset(&color.ui[1], 0, 12);
544 break;
545 default:
546 assert(!"Unsupported element size");
547 return;
548 }
549
550 assert(size % data_size == 0);
551
552 elements = size / data_size;
553 height = (elements + 8191) / 8192;
554 width = elements / height;
555
556 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
557 PUSH_DATAf(push, color.f[0]);
558 PUSH_DATAf(push, color.f[1]);
559 PUSH_DATAf(push, color.f[2]);
560 PUSH_DATAf(push, color.f[3]);
561
562 if (nouveau_pushbuf_space(push, 32, 1, 0))
563 return;
564
565 PUSH_REFN(push, buf->bo, buf->domain | NOUVEAU_BO_WR);
566
567 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
568 PUSH_DATA (push, width << 16);
569 PUSH_DATA (push, height << 16);
570 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
571 PUSH_DATA (push, 8192 << 16);
572 PUSH_DATA (push, 8192 << 16);
573 nv50->scissors_dirty |= 1;
574
575 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
576 PUSH_DATA (push, 1);
577 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
578 PUSH_DATAh(push, buf->bo->offset + buf->offset + offset);
579 PUSH_DATA (push, buf->bo->offset + buf->offset + offset);
580 PUSH_DATA (push, nv50_format_table[dst_fmt].rt);
581 PUSH_DATA (push, 0);
582 PUSH_DATA (push, 0);
583 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
584 PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | (width * data_size));
585 PUSH_DATA (push, height);
586 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
587 PUSH_DATA (push, 0);
588
589 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
590
591 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
592 PUSH_DATA (push, (width << 16));
593 PUSH_DATA (push, (height << 16));
594
595 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
596 PUSH_DATA (push, 0x3c);
597
598 if (width * height != elements) {
599 offset += width * height * data_size;
600 width = elements - width * height;
601 height = 1;
602 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 2);
603 PUSH_DATAh(push, buf->bo->offset + buf->offset + offset);
604 PUSH_DATA (push, buf->bo->offset + buf->offset + offset);
605 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
606 PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | (width * data_size));
607 PUSH_DATA (push, height);
608 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
609 PUSH_DATA (push, 0x3c);
610 }
611
612 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
613 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
614
615 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
616 }
617
618 /* =============================== BLIT CODE ===================================
619 */
620
621 struct nv50_blitter
622 {
623 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
624 struct nv50_program vp;
625
626 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
627
628 pipe_mutex mutex;
629 };
630
631 struct nv50_blitctx
632 {
633 struct nv50_context *nv50;
634 struct nv50_program *fp;
635 uint8_t mode;
636 uint16_t color_mask;
637 uint8_t filter;
638 uint8_t render_condition_enable;
639 enum pipe_texture_target target;
640 struct {
641 struct pipe_framebuffer_state fb;
642 struct nv50_rasterizer_stateobj *rast;
643 struct nv50_program *vp;
644 struct nv50_program *gp;
645 struct nv50_program *fp;
646 unsigned num_textures[3];
647 unsigned num_samplers[3];
648 struct pipe_sampler_view *texture[2];
649 struct nv50_tsc_entry *sampler[2];
650 unsigned min_samples;
651 uint32_t dirty;
652 } saved;
653 struct nv50_rasterizer_stateobj rast;
654 };
655
656 static void
657 nv50_blitter_make_vp(struct nv50_blitter *blit)
658 {
659 static const uint32_t code[] =
660 {
661 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
662 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
663 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
664 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
665 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
666 };
667
668 blit->vp.type = PIPE_SHADER_VERTEX;
669 blit->vp.translated = true;
670 blit->vp.code = (uint32_t *)code; /* const_cast */
671 blit->vp.code_size = sizeof(code);
672 blit->vp.max_gpr = 4;
673 blit->vp.max_out = 5;
674 blit->vp.out_nr = 2;
675 blit->vp.out[0].mask = 0x3;
676 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
677 blit->vp.out[1].hw = 2;
678 blit->vp.out[1].mask = 0x7;
679 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
680 blit->vp.out[1].si = 0;
681 blit->vp.vp.attrs[0] = 0x73;
682 blit->vp.vp.psiz = 0x40;
683 blit->vp.vp.edgeflag = 0x40;
684 }
685
686 void *
687 nv50_blitter_make_fp(struct pipe_context *pipe,
688 unsigned mode,
689 enum pipe_texture_target ptarg)
690 {
691 struct ureg_program *ureg;
692 struct ureg_src tc;
693 struct ureg_dst out;
694 struct ureg_dst data;
695
696 const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
697
698 bool tex_rgbaz = false;
699 bool tex_s = false;
700 bool cvt_un8 = false;
701
702 if (mode != NV50_BLIT_MODE_PASS &&
703 mode != NV50_BLIT_MODE_Z24X8 &&
704 mode != NV50_BLIT_MODE_X8Z24)
705 tex_s = true;
706
707 if (mode != NV50_BLIT_MODE_X24S8 &&
708 mode != NV50_BLIT_MODE_S8X24 &&
709 mode != NV50_BLIT_MODE_XS)
710 tex_rgbaz = true;
711
712 if (mode != NV50_BLIT_MODE_PASS &&
713 mode != NV50_BLIT_MODE_ZS &&
714 mode != NV50_BLIT_MODE_XS)
715 cvt_un8 = true;
716
717 ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
718 if (!ureg)
719 return NULL;
720
721 out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
722 tc = ureg_DECL_fs_input(
723 ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
724
725 if (ptarg == PIPE_TEXTURE_1D_ARRAY) {
726 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
727 tc = ureg_swizzle(tc, TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
728 TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Z);
729 }
730
731 data = ureg_DECL_temporary(ureg);
732
733 if (tex_s) {
734 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
735 target, tc, ureg_DECL_sampler(ureg, 1));
736 ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
737 ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
738 }
739 if (tex_rgbaz) {
740 const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
741 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
742 ureg_TEX(ureg, ureg_writemask(data, mask),
743 target, tc, ureg_DECL_sampler(ureg, 0));
744 }
745
746 if (cvt_un8) {
747 struct ureg_src mask;
748 struct ureg_src scale;
749 struct ureg_dst outz;
750 struct ureg_dst outs;
751 struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
752 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
753 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
754 struct ureg_src zsrc3 = ureg_src(data);
755 struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
756 struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
757 struct ureg_src zshuf;
758
759 mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
760 scale = ureg_imm4f(ureg,
761 1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
762 (1 << 24) - 1);
763
764 if (mode == NV50_BLIT_MODE_Z24S8 ||
765 mode == NV50_BLIT_MODE_X24S8 ||
766 mode == NV50_BLIT_MODE_Z24X8) {
767 outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
768 outs = ureg_writemask(out, TGSI_WRITEMASK_W);
769 zshuf = ureg_src(data);
770 } else {
771 outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
772 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
773 zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
774 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
775 }
776
777 if (tex_s) {
778 ureg_I2F(ureg, sdst, ssrc);
779 ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
780 }
781
782 if (tex_rgbaz) {
783 ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
784 ureg_F2I(ureg, zdst, zsrc);
785 ureg_AND(ureg, zdst3, zsrc, mask);
786 ureg_I2F(ureg, zdst3, zsrc3);
787 ureg_MUL(ureg, zdst3, zsrc3, scale);
788 ureg_MOV(ureg, outz, zshuf);
789 }
790 } else {
791 unsigned mask = TGSI_WRITEMASK_XYZW;
792
793 if (mode != NV50_BLIT_MODE_PASS) {
794 mask &= ~TGSI_WRITEMASK_ZW;
795 if (!tex_s)
796 mask = TGSI_WRITEMASK_X;
797 if (!tex_rgbaz)
798 mask = TGSI_WRITEMASK_Y;
799 }
800 ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
801 }
802 ureg_END(ureg);
803
804 return ureg_create_shader_and_destroy(ureg, pipe);
805 }
806
807 static void
808 nv50_blitter_make_sampler(struct nv50_blitter *blit)
809 {
810 /* clamp to edge, min/max lod = 0, nearest filtering */
811
812 blit->sampler[0].id = -1;
813
814 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
815 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
816 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
817 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
818 blit->sampler[0].tsc[1] =
819 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
820
821 /* clamp to edge, min/max lod = 0, bilinear filtering */
822
823 blit->sampler[1].id = -1;
824
825 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
826 blit->sampler[1].tsc[1] =
827 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
828 }
829
830 unsigned
831 nv50_blit_select_mode(const struct pipe_blit_info *info)
832 {
833 const unsigned mask = info->mask;
834
835 switch (info->dst.resource->format) {
836 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
837 case PIPE_FORMAT_Z24X8_UNORM:
838 case PIPE_FORMAT_X24S8_UINT:
839 switch (mask & PIPE_MASK_ZS) {
840 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
841 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
842 default:
843 return NV50_BLIT_MODE_X24S8;
844 }
845 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
846 case PIPE_FORMAT_X8Z24_UNORM:
847 case PIPE_FORMAT_S8X24_UINT:
848 switch (mask & PIPE_MASK_ZS) {
849 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
850 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
851 default:
852 return NV50_BLIT_MODE_S8X24;
853 }
854 case PIPE_FORMAT_Z32_FLOAT:
855 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
856 case PIPE_FORMAT_X32_S8X24_UINT:
857 switch (mask & PIPE_MASK_ZS) {
858 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
859 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
860 default:
861 return NV50_BLIT_MODE_XS;
862 }
863 default:
864 return NV50_BLIT_MODE_PASS;
865 }
866 }
867
868 static void
869 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
870 {
871 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
872
873 const enum pipe_texture_target ptarg =
874 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
875
876 const unsigned targ = nv50_blit_texture_type(ptarg);
877 const unsigned mode = ctx->mode;
878
879 if (!blitter->fp[targ][mode]) {
880 pipe_mutex_lock(blitter->mutex);
881 if (!blitter->fp[targ][mode])
882 blitter->fp[targ][mode] =
883 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
884 pipe_mutex_unlock(blitter->mutex);
885 }
886 ctx->fp = blitter->fp[targ][mode];
887 }
888
889 static void
890 nv50_blit_set_dst(struct nv50_blitctx *ctx,
891 struct pipe_resource *res, unsigned level, unsigned layer,
892 enum pipe_format format)
893 {
894 struct nv50_context *nv50 = ctx->nv50;
895 struct pipe_context *pipe = &nv50->base.pipe;
896 struct pipe_surface templ;
897
898 if (util_format_is_depth_or_stencil(format))
899 templ.format = nv50_blit_zeta_to_colour_format(format);
900 else
901 templ.format = format;
902
903 templ.u.tex.level = level;
904 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
905
906 if (layer == -1) {
907 templ.u.tex.first_layer = 0;
908 templ.u.tex.last_layer =
909 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
910 }
911
912 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
913 nv50->framebuffer.nr_cbufs = 1;
914 nv50->framebuffer.zsbuf = NULL;
915 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
916 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
917 }
918
919 static void
920 nv50_blit_set_src(struct nv50_blitctx *blit,
921 struct pipe_resource *res, unsigned level, unsigned layer,
922 enum pipe_format format, const uint8_t filter)
923 {
924 struct nv50_context *nv50 = blit->nv50;
925 struct pipe_context *pipe = &nv50->base.pipe;
926 struct pipe_sampler_view templ;
927 uint32_t flags;
928 enum pipe_texture_target target;
929
930 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
931
932 templ.format = format;
933 templ.u.tex.first_level = templ.u.tex.last_level = level;
934 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
935 templ.swizzle_r = PIPE_SWIZZLE_RED;
936 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
937 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
938 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
939
940 if (layer == -1) {
941 templ.u.tex.first_layer = 0;
942 templ.u.tex.last_layer =
943 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
944 }
945
946 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
947 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
948 if (filter && res->nr_samples == 8)
949 flags |= NV50_TEXVIEW_FILTER_MSAA8;
950
951 nv50->textures[2][0] = nv50_create_texture_view(
952 pipe, res, &templ, flags, target);
953 nv50->textures[2][1] = NULL;
954
955 nv50->num_textures[0] = nv50->num_textures[1] = 0;
956 nv50->num_textures[2] = 1;
957
958 templ.format = nv50_zs_to_s_format(format);
959 if (templ.format != res->format) {
960 nv50->textures[2][1] = nv50_create_texture_view(
961 pipe, res, &templ, flags, target);
962 nv50->num_textures[2] = 2;
963 }
964 }
965
966 static void
967 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
968 {
969 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
970
971 if (blit->nv50->cond_query && !blit->render_condition_enable) {
972 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
973 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
974 }
975
976 /* blend state */
977 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
978 PUSH_DATA (push, blit->color_mask);
979 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
980 PUSH_DATA (push, 0);
981 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
982 PUSH_DATA (push, 0);
983
984 /* rasterizer state */
985 #ifndef NV50_SCISSORS_CLIPPING
986 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
987 PUSH_DATA (push, 1);
988 #endif
989 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
990 PUSH_DATA (push, 0);
991 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
992 PUSH_DATA (push, 0);
993 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
994 PUSH_DATA (push, 0);
995 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
996 PUSH_DATA (push, 0xffff);
997 PUSH_DATA (push, 0xffff);
998 PUSH_DATA (push, 0xffff);
999 PUSH_DATA (push, 0xffff);
1000 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
1001 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
1002 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
1003 PUSH_DATA (push, 0);
1004 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
1005 PUSH_DATA (push, 0);
1006 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
1007 PUSH_DATA (push, 0);
1008 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
1009 PUSH_DATA (push, 0);
1010
1011 /* zsa state */
1012 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
1013 PUSH_DATA (push, 0);
1014 BEGIN_NV04(push, NV50_3D(DEPTH_BOUNDS_EN), 1);
1015 PUSH_DATA (push, 0);
1016 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
1017 PUSH_DATA (push, 0);
1018 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
1019 PUSH_DATA (push, 0);
1020 }
1021
1022 static void
1023 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
1024 {
1025 struct nv50_context *nv50 = ctx->nv50;
1026 struct nv50_blitter *blitter = nv50->screen->blitter;
1027 int s;
1028
1029 ctx->saved.fb.width = nv50->framebuffer.width;
1030 ctx->saved.fb.height = nv50->framebuffer.height;
1031 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
1032 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
1033 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
1034
1035 ctx->saved.rast = nv50->rast;
1036
1037 ctx->saved.vp = nv50->vertprog;
1038 ctx->saved.gp = nv50->gmtyprog;
1039 ctx->saved.fp = nv50->fragprog;
1040
1041 ctx->saved.min_samples = nv50->min_samples;
1042
1043 nv50->rast = &ctx->rast;
1044
1045 nv50->vertprog = &blitter->vp;
1046 nv50->gmtyprog = NULL;
1047 nv50->fragprog = ctx->fp;
1048
1049 for (s = 0; s < 3; ++s) {
1050 ctx->saved.num_textures[s] = nv50->num_textures[s];
1051 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
1052 }
1053 ctx->saved.texture[0] = nv50->textures[2][0];
1054 ctx->saved.texture[1] = nv50->textures[2][1];
1055 ctx->saved.sampler[0] = nv50->samplers[2][0];
1056 ctx->saved.sampler[1] = nv50->samplers[2][1];
1057
1058 nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
1059 nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
1060
1061 nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
1062 nv50->num_samplers[2] = 2;
1063
1064 nv50->min_samples = 1;
1065
1066 ctx->saved.dirty = nv50->dirty;
1067
1068 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
1069 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
1070
1071 nv50->dirty =
1072 NV50_NEW_FRAMEBUFFER | NV50_NEW_MIN_SAMPLES |
1073 NV50_NEW_VERTPROG | NV50_NEW_FRAGPROG | NV50_NEW_GMTYPROG |
1074 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS;
1075 }
1076
1077 static void
1078 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
1079 {
1080 struct nv50_context *nv50 = blit->nv50;
1081 int s;
1082
1083 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
1084
1085 nv50->framebuffer.width = blit->saved.fb.width;
1086 nv50->framebuffer.height = blit->saved.fb.height;
1087 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1088 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1089 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1090
1091 nv50->rast = blit->saved.rast;
1092
1093 nv50->vertprog = blit->saved.vp;
1094 nv50->gmtyprog = blit->saved.gp;
1095 nv50->fragprog = blit->saved.fp;
1096
1097 nv50->min_samples = blit->saved.min_samples;
1098
1099 pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
1100 pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
1101
1102 for (s = 0; s < 3; ++s) {
1103 nv50->num_textures[s] = blit->saved.num_textures[s];
1104 nv50->num_samplers[s] = blit->saved.num_samplers[s];
1105 }
1106 nv50->textures[2][0] = blit->saved.texture[0];
1107 nv50->textures[2][1] = blit->saved.texture[1];
1108 nv50->samplers[2][0] = blit->saved.sampler[0];
1109 nv50->samplers[2][1] = blit->saved.sampler[1];
1110
1111 if (nv50->cond_query && !blit->render_condition_enable)
1112 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
1113 nv50->cond_cond, nv50->cond_mode);
1114
1115 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
1116 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
1117
1118 nv50->dirty = blit->saved.dirty |
1119 (NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR | NV50_NEW_SAMPLE_MASK |
1120 NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
1121 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
1122 NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
1123 nv50->scissors_dirty |= 1;
1124
1125 nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
1126 }
1127
1128
1129 static void
1130 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1131 {
1132 struct nv50_blitctx *blit = nv50->blit;
1133 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1134 struct pipe_resource *src = info->src.resource;
1135 struct pipe_resource *dst = info->dst.resource;
1136 int32_t minx, maxx, miny, maxy;
1137 int32_t i;
1138 float x0, x1, y0, y1, z;
1139 float dz;
1140 float x_range, y_range;
1141 float tri_x, tri_y;
1142
1143 blit->mode = nv50_blit_select_mode(info);
1144 blit->color_mask = nv50_blit_derive_color_mask(info);
1145 blit->filter = nv50_blit_get_filter(info);
1146 blit->render_condition_enable = info->render_condition_enable;
1147
1148 nv50_blit_select_fp(blit, info);
1149 nv50_blitctx_pre_blit(blit);
1150
1151 nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1152 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1153 blit->filter);
1154
1155 nv50_blitctx_prepare_state(blit);
1156
1157 nv50_state_validate(nv50, ~0, 36);
1158
1159 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1160 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1161
1162 tri_x = 16384 << nv50_miptree(dst)->ms_x;
1163 tri_y = 16384 << nv50_miptree(dst)->ms_y;
1164
1165 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1166 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1167
1168 x1 = x0 + tri_x * x_range;
1169 y1 = y0 + tri_y * y_range;
1170
1171 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1172 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1173 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1174 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1175
1176 /* XXX: multiply by 6 for cube arrays ? */
1177 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1178 z = (float)info->src.box.z;
1179 if (nv50_miptree(src)->layout_3d)
1180 z += 0.5f * dz;
1181
1182 if (src->last_level > 0) {
1183 /* If there are mip maps, GPU always assumes normalized coordinates. */
1184 const unsigned l = info->src.level;
1185 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1186 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1187 x0 /= fh;
1188 x1 /= fh;
1189 y0 /= fv;
1190 y1 /= fv;
1191 if (nv50_miptree(src)->layout_3d) {
1192 z /= u_minify(src->depth0, l);
1193 dz /= u_minify(src->depth0, l);
1194 }
1195 }
1196
1197 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1198 PUSH_DATA (push, 0);
1199 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1200 PUSH_DATA (push, 0x1);
1201
1202 /* Draw a large triangle in screen coordinates covering the whole
1203 * render target, with scissors defining the destination region.
1204 * The vertex is supplied with non-normalized texture coordinates
1205 * arranged in a way to yield the desired offset and scale.
1206 */
1207
1208 minx = info->dst.box.x;
1209 maxx = info->dst.box.x + info->dst.box.width;
1210 miny = info->dst.box.y;
1211 maxy = info->dst.box.y + info->dst.box.height;
1212 if (info->scissor_enable) {
1213 minx = MAX2(minx, info->scissor.minx);
1214 maxx = MIN2(maxx, info->scissor.maxx);
1215 miny = MAX2(miny, info->scissor.miny);
1216 maxy = MIN2(maxy, info->scissor.maxy);
1217 }
1218 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
1219 PUSH_DATA (push, (maxx << 16) | minx);
1220 PUSH_DATA (push, (maxy << 16) | miny);
1221
1222 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1223 if (info->dst.box.z + i) {
1224 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1225 PUSH_DATA (push, info->dst.box.z + i);
1226 }
1227 PUSH_SPACE(push, 32);
1228 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1229 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1230 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1231 PUSH_DATAf(push, x0);
1232 PUSH_DATAf(push, y0);
1233 PUSH_DATAf(push, z);
1234 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1235 PUSH_DATAf(push, 0.0f);
1236 PUSH_DATAf(push, 0.0f);
1237 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1238 PUSH_DATAf(push, x1);
1239 PUSH_DATAf(push, y0);
1240 PUSH_DATAf(push, z);
1241 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1242 PUSH_DATAf(push, tri_x);
1243 PUSH_DATAf(push, 0.0f);
1244 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1245 PUSH_DATAf(push, x0);
1246 PUSH_DATAf(push, y1);
1247 PUSH_DATAf(push, z);
1248 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1249 PUSH_DATAf(push, 0.0f);
1250 PUSH_DATAf(push, tri_y);
1251 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1252 PUSH_DATA (push, 0);
1253 }
1254 if (info->dst.box.z + info->dst.box.depth - 1) {
1255 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1256 PUSH_DATA (push, 0);
1257 }
1258
1259 /* re-enable normally constant state */
1260
1261 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1262 PUSH_DATA (push, 1);
1263
1264 nv50_blitctx_post_blit(blit);
1265 }
1266
1267 static void
1268 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1269 {
1270 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1271 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1272 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1273 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1274 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1275 const int32_t dz = info->dst.box.z;
1276 const int32_t sz = info->src.box.z;
1277 uint32_t dstw, dsth;
1278 int32_t dstx, dsty;
1279 int64_t srcx, srcy;
1280 int64_t du_dx, dv_dy;
1281 int i;
1282 uint32_t mode;
1283 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1284 bool b;
1285
1286 mode = nv50_blit_get_filter(info) ?
1287 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1288 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1289 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1290 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1291
1292 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1293 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1294
1295 b = info->dst.format == info->src.format;
1296 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1297 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1298
1299 if (info->scissor_enable) {
1300 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1301 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1302 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1303 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1304 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1305 PUSH_DATA (push, 1); /* enable */
1306 }
1307
1308 if (nv50->cond_query && info->render_condition_enable) {
1309 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1310 PUSH_DATA (push, nv50->cond_condmode);
1311 }
1312
1313 if (mask != 0xffffffff) {
1314 BEGIN_NV04(push, NV50_2D(ROP), 1);
1315 PUSH_DATA (push, 0xca); /* DPSDxax */
1316 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1317 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1318 BEGIN_NV04(push, NV50_2D(PATTERN_BITMAP_COLOR(0)), 4);
1319 PUSH_DATA (push, 0x00000000);
1320 PUSH_DATA (push, mask);
1321 PUSH_DATA (push, 0xffffffff);
1322 PUSH_DATA (push, 0xffffffff);
1323 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1324 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1325 } else
1326 if (info->src.format != info->dst.format) {
1327 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1328 info->src.format == PIPE_FORMAT_R16_UNORM ||
1329 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1330 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1331 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1332 BEGIN_NV04(push, NV50_2D(BETA4), 2);
1333 PUSH_DATA (push, mask);
1334 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1335 }
1336 }
1337
1338 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1339 /* ms_x is always >= ms_y */
1340 du_dx <<= src->ms_x - dst->ms_x;
1341 dv_dy <<= src->ms_y - dst->ms_y;
1342 } else {
1343 du_dx >>= dst->ms_x - src->ms_x;
1344 dv_dy >>= dst->ms_y - src->ms_y;
1345 }
1346
1347 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1348 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1349
1350 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1351 /* center src coorinates for proper MS resolve filtering */
1352 srcx += (int64_t)1 << (src->ms_x + 31);
1353 srcy += (int64_t)1 << (src->ms_y + 31);
1354 }
1355
1356 dstx = info->dst.box.x << dst->ms_x;
1357 dsty = info->dst.box.y << dst->ms_y;
1358
1359 dstw = info->dst.box.width << dst->ms_x;
1360 dsth = info->dst.box.height << dst->ms_y;
1361
1362 if (dstx < 0) {
1363 dstw += dstx;
1364 srcx -= du_dx * dstx;
1365 dstx = 0;
1366 }
1367 if (dsty < 0) {
1368 dsth += dsty;
1369 srcy -= dv_dy * dsty;
1370 dsty = 0;
1371 }
1372
1373 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1374 PUSH_DATA (push, mode);
1375 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1376 PUSH_DATA (push, dstx);
1377 PUSH_DATA (push, dsty);
1378 PUSH_DATA (push, dstw);
1379 PUSH_DATA (push, dsth);
1380 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1381 PUSH_DATA (push, du_dx);
1382 PUSH_DATA (push, du_dx >> 32);
1383 PUSH_DATA (push, dv_dy);
1384 PUSH_DATA (push, dv_dy >> 32);
1385
1386 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1387 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1388 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1389 if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1390 return;
1391
1392 for (i = 0; i < info->dst.box.depth; ++i) {
1393 if (i > 0) {
1394 /* no scaling in z-direction possible for eng2d blits */
1395 if (dst->layout_3d) {
1396 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1397 PUSH_DATA (push, info->dst.box.z + i);
1398 } else {
1399 const unsigned z = info->dst.box.z + i;
1400 const uint64_t address = dst->base.address +
1401 dst->level[info->dst.level].offset +
1402 z * dst->layer_stride;
1403 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1404 PUSH_DATAh(push, address);
1405 PUSH_DATA (push, address);
1406 }
1407 if (src->layout_3d) {
1408 /* not possible because of depth tiling */
1409 assert(0);
1410 } else {
1411 const unsigned z = info->src.box.z + i;
1412 const uint64_t address = src->base.address +
1413 src->level[info->src.level].offset +
1414 z * src->layer_stride;
1415 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1416 PUSH_DATAh(push, address);
1417 PUSH_DATA (push, address);
1418 }
1419 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1420 PUSH_DATA (push, srcy >> 32);
1421 } else {
1422 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1423 PUSH_DATA (push, srcx);
1424 PUSH_DATA (push, srcx >> 32);
1425 PUSH_DATA (push, srcy);
1426 PUSH_DATA (push, srcy >> 32);
1427 }
1428 }
1429 nv50_bufctx_fence(nv50->bufctx, false);
1430
1431 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1432
1433 if (info->scissor_enable) {
1434 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1435 PUSH_DATA (push, 0);
1436 }
1437 if (mask != 0xffffffff) {
1438 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1439 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1440 }
1441 if (nv50->cond_query && info->render_condition_enable) {
1442 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1443 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1444 }
1445 }
1446
1447 static void
1448 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1449 {
1450 struct nv50_context *nv50 = nv50_context(pipe);
1451 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1452 bool eng3d = FALSE;
1453
1454 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1455 if (!(info->mask & PIPE_MASK_ZS))
1456 return;
1457 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1458 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1459 eng3d = true;
1460 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1461 eng3d = true;
1462 } else {
1463 if (!(info->mask & PIPE_MASK_RGBA))
1464 return;
1465 if (info->mask != PIPE_MASK_RGBA)
1466 eng3d = true;
1467 }
1468
1469 if (nv50_miptree(info->src.resource)->layout_3d) {
1470 eng3d = true;
1471 } else
1472 if (info->src.box.depth != info->dst.box.depth) {
1473 eng3d = true;
1474 debug_printf("blit: cannot filter array or cube textures in z direction");
1475 }
1476
1477 if (!eng3d && info->dst.format != info->src.format) {
1478 if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1479 !nv50_2d_src_format_faithful(info->src.format)) {
1480 eng3d = true;
1481 } else
1482 if (!nv50_2d_src_format_faithful(info->src.format)) {
1483 if (!util_format_is_luminance(info->src.format)) {
1484 if (util_format_is_intensity(info->src.format))
1485 eng3d = true;
1486 else
1487 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1488 eng3d = true;
1489 else
1490 eng3d = !nv50_2d_format_supported(info->src.format);
1491 }
1492 } else
1493 if (util_format_is_luminance_alpha(info->src.format))
1494 eng3d = true;
1495 }
1496
1497 if (info->src.resource->nr_samples == 8 &&
1498 info->dst.resource->nr_samples <= 1)
1499 eng3d = true;
1500
1501 /* FIXME: can't make this work with eng2d anymore */
1502 if ((info->src.resource->nr_samples | 1) !=
1503 (info->dst.resource->nr_samples | 1))
1504 eng3d = true;
1505
1506 /* FIXME: find correct src coordinate adjustments */
1507 if ((info->src.box.width != info->dst.box.width &&
1508 info->src.box.width != -info->dst.box.width) ||
1509 (info->src.box.height != info->dst.box.height &&
1510 info->src.box.height != -info->dst.box.height))
1511 eng3d = true;
1512
1513 if (nv50->screen->num_occlusion_queries_active) {
1514 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1515 PUSH_DATA (push, 0);
1516 }
1517
1518 if (!eng3d)
1519 nv50_blit_eng2d(nv50, info);
1520 else
1521 nv50_blit_3d(nv50, info);
1522
1523 if (nv50->screen->num_occlusion_queries_active) {
1524 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1525 PUSH_DATA (push, 1);
1526 }
1527 }
1528
1529 static void
1530 nv50_flush_resource(struct pipe_context *ctx,
1531 struct pipe_resource *resource)
1532 {
1533 }
1534
1535 bool
1536 nv50_blitter_create(struct nv50_screen *screen)
1537 {
1538 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1539 if (!screen->blitter) {
1540 NOUVEAU_ERR("failed to allocate blitter struct\n");
1541 return false;
1542 }
1543
1544 pipe_mutex_init(screen->blitter->mutex);
1545
1546 nv50_blitter_make_vp(screen->blitter);
1547 nv50_blitter_make_sampler(screen->blitter);
1548
1549 return true;
1550 }
1551
1552 void
1553 nv50_blitter_destroy(struct nv50_screen *screen)
1554 {
1555 struct nv50_blitter *blitter = screen->blitter;
1556 unsigned i, m;
1557
1558 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1559 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1560 struct nv50_program *prog = blitter->fp[i][m];
1561 if (prog) {
1562 nv50_program_destroy(NULL, prog);
1563 FREE((void *)prog->pipe.tokens);
1564 FREE(prog);
1565 }
1566 }
1567 }
1568
1569 FREE(blitter);
1570 }
1571
1572 bool
1573 nv50_blitctx_create(struct nv50_context *nv50)
1574 {
1575 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1576 if (!nv50->blit) {
1577 NOUVEAU_ERR("failed to allocate blit context\n");
1578 return false;
1579 }
1580
1581 nv50->blit->nv50 = nv50;
1582
1583 nv50->blit->rast.pipe.half_pixel_center = 1;
1584
1585 return true;
1586 }
1587
1588 void
1589 nv50_init_surface_functions(struct nv50_context *nv50)
1590 {
1591 struct pipe_context *pipe = &nv50->base.pipe;
1592
1593 pipe->resource_copy_region = nv50_resource_copy_region;
1594 pipe->blit = nv50_blit;
1595 pipe->flush_resource = nv50_flush_resource;
1596 pipe->clear_render_target = nv50_clear_render_target;
1597 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1598 pipe->clear_buffer = nv50_clear_buffer;
1599 }