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nv50: fix 2d engine blits for 64- and 128-bit formats
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "tgsi/tgsi_ureg.h"
33
34 #include "os/os_thread.h"
35
36 #include "nv50/nv50_context.h"
37 #include "nv50/nv50_resource.h"
38
39 #include "nv50/nv50_defs.xml.h"
40 #include "nv50/nv50_texture.xml.h"
41
42 /* these are used in nv50_blit.h */
43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
44 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
45 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
47 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
48
49 #define NOUVEAU_DRIVER 0x50
50 #include "nv50/nv50_blit.h"
51
52 static inline uint8_t
53 nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
54 {
55 uint8_t id = nv50_format_table[format].rt;
56
57 /* Hardware values for color formats range from 0xc0 to 0xff,
58 * but the 2D engine doesn't support all of them.
59 */
60 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
61 return id;
62 assert(dst_src_equal);
63
64 switch (util_format_get_blocksize(format)) {
65 case 1:
66 return NV50_SURFACE_FORMAT_R8_UNORM;
67 case 2:
68 return NV50_SURFACE_FORMAT_R16_UNORM;
69 case 4:
70 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
71 case 8:
72 return NV50_SURFACE_FORMAT_RGBA16_FLOAT;
73 case 16:
74 return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
75 default:
76 return 0;
77 }
78 }
79
80 static int
81 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
82 struct nv50_miptree *mt, unsigned level, unsigned layer,
83 enum pipe_format pformat, bool dst_src_pformat_equal)
84 {
85 struct nouveau_bo *bo = mt->base.bo;
86 uint32_t width, height, depth;
87 uint32_t format;
88 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
89 uint32_t offset = mt->level[level].offset;
90
91 format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
92 if (!format) {
93 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
94 util_format_name(pformat));
95 return 1;
96 }
97
98 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
99 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
100 depth = u_minify(mt->base.base.depth0, level);
101
102 offset = mt->level[level].offset;
103 if (!mt->layout_3d) {
104 offset += mt->layer_stride * layer;
105 depth = 1;
106 layer = 0;
107 } else
108 if (!dst) {
109 offset += nv50_mt_zslice_offset(mt, level, layer);
110 layer = 0;
111 }
112
113 if (!nouveau_bo_memtype(bo)) {
114 BEGIN_NV04(push, SUBC_2D(mthd), 2);
115 PUSH_DATA (push, format);
116 PUSH_DATA (push, 1);
117 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
118 PUSH_DATA (push, mt->level[level].pitch);
119 PUSH_DATA (push, width);
120 PUSH_DATA (push, height);
121 PUSH_DATAh(push, mt->base.address + offset);
122 PUSH_DATA (push, mt->base.address + offset);
123 } else {
124 BEGIN_NV04(push, SUBC_2D(mthd), 5);
125 PUSH_DATA (push, format);
126 PUSH_DATA (push, 0);
127 PUSH_DATA (push, mt->level[level].tile_mode);
128 PUSH_DATA (push, depth);
129 PUSH_DATA (push, layer);
130 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
131 PUSH_DATA (push, width);
132 PUSH_DATA (push, height);
133 PUSH_DATAh(push, mt->base.address + offset);
134 PUSH_DATA (push, mt->base.address + offset);
135 }
136
137 #if 0
138 if (dst) {
139 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
140 PUSH_DATA (push, 0);
141 PUSH_DATA (push, 0);
142 PUSH_DATA (push, width);
143 PUSH_DATA (push, height);
144 }
145 #endif
146 return 0;
147 }
148
149 static int
150 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
151 struct nv50_miptree *dst, unsigned dst_level,
152 unsigned dx, unsigned dy, unsigned dz,
153 struct nv50_miptree *src, unsigned src_level,
154 unsigned sx, unsigned sy, unsigned sz,
155 unsigned w, unsigned h)
156 {
157 const enum pipe_format dfmt = dst->base.base.format;
158 const enum pipe_format sfmt = src->base.base.format;
159 int ret;
160 bool eqfmt = dfmt == sfmt;
161
162 if (!PUSH_SPACE(push, 2 * 16 + 32))
163 return PIPE_ERROR;
164
165 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
166 if (ret)
167 return ret;
168
169 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
170 if (ret)
171 return ret;
172
173 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
174 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
175 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
176 PUSH_DATA (push, dx << dst->ms_x);
177 PUSH_DATA (push, dy << dst->ms_y);
178 PUSH_DATA (push, w << dst->ms_x);
179 PUSH_DATA (push, h << dst->ms_y);
180 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
181 PUSH_DATA (push, 0);
182 PUSH_DATA (push, 1);
183 PUSH_DATA (push, 0);
184 PUSH_DATA (push, 1);
185 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
186 PUSH_DATA (push, 0);
187 PUSH_DATA (push, sx << src->ms_x);
188 PUSH_DATA (push, 0);
189 PUSH_DATA (push, sy << src->ms_y);
190
191 return 0;
192 }
193
194 static void
195 nv50_resource_copy_region(struct pipe_context *pipe,
196 struct pipe_resource *dst, unsigned dst_level,
197 unsigned dstx, unsigned dsty, unsigned dstz,
198 struct pipe_resource *src, unsigned src_level,
199 const struct pipe_box *src_box)
200 {
201 struct nv50_context *nv50 = nv50_context(pipe);
202 int ret;
203 bool m2mf;
204 unsigned dst_layer = dstz, src_layer = src_box->z;
205
206 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
207 nouveau_copy_buffer(&nv50->base,
208 nv04_resource(dst), dstx,
209 nv04_resource(src), src_box->x, src_box->width);
210 return;
211 }
212
213 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
214 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
215
216 m2mf = (src->format == dst->format) ||
217 (util_format_get_blocksizebits(src->format) ==
218 util_format_get_blocksizebits(dst->format));
219
220 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
221
222 if (m2mf) {
223 struct nv50_m2mf_rect drect, srect;
224 unsigned i;
225 unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
226 unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
227
228 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
229 nv50_m2mf_rect_setup(&srect, src, src_level,
230 src_box->x, src_box->y, src_box->z);
231
232 for (i = 0; i < src_box->depth; ++i) {
233 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
234
235 if (nv50_miptree(dst)->layout_3d)
236 drect.z++;
237 else
238 drect.base += nv50_miptree(dst)->layer_stride;
239
240 if (nv50_miptree(src)->layout_3d)
241 srect.z++;
242 else
243 srect.base += nv50_miptree(src)->layer_stride;
244 }
245 return;
246 }
247
248 assert((src->format == dst->format) ||
249 (nv50_2d_src_format_faithful(src->format) &&
250 nv50_2d_dst_format_faithful(dst->format)));
251
252 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
253 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
254 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
255 nouveau_pushbuf_validate(nv50->base.pushbuf);
256
257 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
258 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
259 nv50_miptree(dst), dst_level,
260 dstx, dsty, dst_layer,
261 nv50_miptree(src), src_level,
262 src_box->x, src_box->y, src_layer,
263 src_box->width, src_box->height);
264 if (ret)
265 break;
266 }
267 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
268 }
269
270 static void
271 nv50_clear_render_target(struct pipe_context *pipe,
272 struct pipe_surface *dst,
273 const union pipe_color_union *color,
274 unsigned dstx, unsigned dsty,
275 unsigned width, unsigned height)
276 {
277 struct nv50_context *nv50 = nv50_context(pipe);
278 struct nouveau_pushbuf *push = nv50->base.pushbuf;
279 struct nv50_miptree *mt = nv50_miptree(dst->texture);
280 struct nv50_surface *sf = nv50_surface(dst);
281 struct nouveau_bo *bo = mt->base.bo;
282 unsigned z;
283
284 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
285 PUSH_DATAf(push, color->f[0]);
286 PUSH_DATAf(push, color->f[1]);
287 PUSH_DATAf(push, color->f[2]);
288 PUSH_DATAf(push, color->f[3]);
289
290 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
291 return;
292
293 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
294
295 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
296 PUSH_DATA (push, ( width << 16) | dstx);
297 PUSH_DATA (push, (height << 16) | dsty);
298 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
299 PUSH_DATA (push, 8192 << 16);
300 PUSH_DATA (push, 8192 << 16);
301 nv50->scissors_dirty |= 1;
302
303 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
304 PUSH_DATA (push, 1);
305 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
306 PUSH_DATAh(push, mt->base.address + sf->offset);
307 PUSH_DATA (push, mt->base.address + sf->offset);
308 PUSH_DATA (push, nv50_format_table[dst->format].rt);
309 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
310 PUSH_DATA (push, mt->layer_stride >> 2);
311 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
312 if (nouveau_bo_memtype(bo))
313 PUSH_DATA(push, sf->width);
314 else
315 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
316 PUSH_DATA (push, sf->height);
317 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
318 if (mt->layout_3d)
319 PUSH_DATA(push, NV50_3D_RT_ARRAY_MODE_MODE_3D | 512);
320 else
321 PUSH_DATA(push, 512);
322
323 if (!nouveau_bo_memtype(bo)) {
324 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
325 PUSH_DATA (push, 0);
326 }
327
328 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
329
330 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
331 PUSH_DATA (push, (width << 16) | dstx);
332 PUSH_DATA (push, (height << 16) | dsty);
333
334 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
335 for (z = 0; z < sf->depth; ++z) {
336 PUSH_DATA (push, 0x3c |
337 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
338 }
339
340 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
341 }
342
343 static void
344 nv50_clear_depth_stencil(struct pipe_context *pipe,
345 struct pipe_surface *dst,
346 unsigned clear_flags,
347 double depth,
348 unsigned stencil,
349 unsigned dstx, unsigned dsty,
350 unsigned width, unsigned height)
351 {
352 struct nv50_context *nv50 = nv50_context(pipe);
353 struct nouveau_pushbuf *push = nv50->base.pushbuf;
354 struct nv50_miptree *mt = nv50_miptree(dst->texture);
355 struct nv50_surface *sf = nv50_surface(dst);
356 struct nouveau_bo *bo = mt->base.bo;
357 uint32_t mode = 0;
358 unsigned z;
359
360 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
361
362 if (clear_flags & PIPE_CLEAR_DEPTH) {
363 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
364 PUSH_DATAf(push, depth);
365 mode |= NV50_3D_CLEAR_BUFFERS_Z;
366 }
367
368 if (clear_flags & PIPE_CLEAR_STENCIL) {
369 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
370 PUSH_DATA (push, stencil & 0xff);
371 mode |= NV50_3D_CLEAR_BUFFERS_S;
372 }
373
374 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
375 return;
376
377 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
378
379 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
380 PUSH_DATA (push, ( width << 16) | dstx);
381 PUSH_DATA (push, (height << 16) | dsty);
382 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
383 PUSH_DATA (push, 8192 << 16);
384 PUSH_DATA (push, 8192 << 16);
385 nv50->scissors_dirty |= 1;
386
387 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
388 PUSH_DATAh(push, mt->base.address + sf->offset);
389 PUSH_DATA (push, mt->base.address + sf->offset);
390 PUSH_DATA (push, nv50_format_table[dst->format].rt);
391 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
392 PUSH_DATA (push, mt->layer_stride >> 2);
393 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
394 PUSH_DATA (push, 1);
395 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
396 PUSH_DATA (push, sf->width);
397 PUSH_DATA (push, sf->height);
398 PUSH_DATA (push, (1 << 16) | 1);
399
400 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
401 PUSH_DATA (push, 512);
402
403 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
404 PUSH_DATA (push, (width << 16) | dstx);
405 PUSH_DATA (push, (height << 16) | dsty);
406
407 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
408 for (z = 0; z < sf->depth; ++z) {
409 PUSH_DATA (push, mode |
410 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
411 }
412
413 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
414 }
415
416 void
417 nv50_clear(struct pipe_context *pipe, unsigned buffers,
418 const union pipe_color_union *color,
419 double depth, unsigned stencil)
420 {
421 struct nv50_context *nv50 = nv50_context(pipe);
422 struct nouveau_pushbuf *push = nv50->base.pushbuf;
423 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
424 unsigned i, j, k;
425 uint32_t mode = 0;
426
427 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
428 if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
429 return;
430
431 /* We have to clear ALL of the layers, not up to the min number of layers
432 * of any attachment. */
433 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
434 PUSH_DATA (push, (nv50->rt_array_mode & NV50_3D_RT_ARRAY_MODE_MODE_3D) | 512);
435
436 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
437 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
438 PUSH_DATAf(push, color->f[0]);
439 PUSH_DATAf(push, color->f[1]);
440 PUSH_DATAf(push, color->f[2]);
441 PUSH_DATAf(push, color->f[3]);
442 if (buffers & PIPE_CLEAR_COLOR0)
443 mode =
444 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
445 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
446 }
447
448 if (buffers & PIPE_CLEAR_DEPTH) {
449 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
450 PUSH_DATA (push, fui(depth));
451 mode |= NV50_3D_CLEAR_BUFFERS_Z;
452 }
453
454 if (buffers & PIPE_CLEAR_STENCIL) {
455 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
456 PUSH_DATA (push, stencil & 0xff);
457 mode |= NV50_3D_CLEAR_BUFFERS_S;
458 }
459
460 if (mode) {
461 int zs_layers = 0, color0_layers = 0;
462 if (fb->cbufs[0] && (mode & 0x3c))
463 color0_layers = fb->cbufs[0]->u.tex.last_layer -
464 fb->cbufs[0]->u.tex.first_layer + 1;
465 if (fb->zsbuf && (mode & ~0x3c))
466 zs_layers = fb->zsbuf->u.tex.last_layer -
467 fb->zsbuf->u.tex.first_layer + 1;
468
469 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
470 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
471 PUSH_DATA(push, mode | (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
472 }
473 for (k = j; k < zs_layers; k++) {
474 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
475 PUSH_DATA(push, (mode & ~0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
476 }
477 for (k = j; k < color0_layers; k++) {
478 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
479 PUSH_DATA(push, (mode & 0x3c) | (k << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
480 }
481 }
482
483 for (i = 1; i < fb->nr_cbufs; i++) {
484 struct pipe_surface *sf = fb->cbufs[i];
485 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
486 continue;
487 for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
488 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
489 PUSH_DATA (push, (i << 6) | 0x3c |
490 (j << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
491 }
492 }
493
494 /* restore the array mode */
495 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
496 PUSH_DATA (push, nv50->rt_array_mode);
497 }
498
499 static void
500 nv50_clear_buffer(struct pipe_context *pipe,
501 struct pipe_resource *res,
502 unsigned offset, unsigned size,
503 const void *data, int data_size)
504 {
505 struct nv50_context *nv50 = nv50_context(pipe);
506 struct nouveau_pushbuf *push = nv50->base.pushbuf;
507 struct nv04_resource *buf = (struct nv04_resource *)res;
508 union pipe_color_union color;
509 enum pipe_format dst_fmt;
510 unsigned width, height, elements;
511
512 assert(res->target == PIPE_BUFFER);
513 assert(nouveau_bo_memtype(buf->bo) == 0);
514
515 switch (data_size) {
516 case 16:
517 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
518 memcpy(&color.ui, data, 16);
519 break;
520 case 8:
521 dst_fmt = PIPE_FORMAT_R32G32_UINT;
522 memcpy(&color.ui, data, 8);
523 memset(&color.ui[2], 0, 8);
524 break;
525 case 4:
526 dst_fmt = PIPE_FORMAT_R32_UINT;
527 memcpy(&color.ui, data, 4);
528 memset(&color.ui[1], 0, 12);
529 break;
530 case 2:
531 dst_fmt = PIPE_FORMAT_R16_UINT;
532 color.ui[0] = util_cpu_to_le32(
533 util_le16_to_cpu(*(unsigned short *)data));
534 memset(&color.ui[1], 0, 12);
535 break;
536 case 1:
537 dst_fmt = PIPE_FORMAT_R8_UINT;
538 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
539 memset(&color.ui[1], 0, 12);
540 break;
541 default:
542 assert(!"Unsupported element size");
543 return;
544 }
545
546 assert(size % data_size == 0);
547
548 elements = size / data_size;
549 height = (elements + 8191) / 8192;
550 width = elements / height;
551
552 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
553 PUSH_DATAf(push, color.f[0]);
554 PUSH_DATAf(push, color.f[1]);
555 PUSH_DATAf(push, color.f[2]);
556 PUSH_DATAf(push, color.f[3]);
557
558 if (nouveau_pushbuf_space(push, 32, 1, 0))
559 return;
560
561 PUSH_REFN(push, buf->bo, buf->domain | NOUVEAU_BO_WR);
562
563 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
564 PUSH_DATA (push, width << 16);
565 PUSH_DATA (push, height << 16);
566 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
567 PUSH_DATA (push, 8192 << 16);
568 PUSH_DATA (push, 8192 << 16);
569 nv50->scissors_dirty |= 1;
570
571 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
572 PUSH_DATA (push, 1);
573 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
574 PUSH_DATAh(push, buf->bo->offset + buf->offset + offset);
575 PUSH_DATA (push, buf->bo->offset + buf->offset + offset);
576 PUSH_DATA (push, nv50_format_table[dst_fmt].rt);
577 PUSH_DATA (push, 0);
578 PUSH_DATA (push, 0);
579 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
580 PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | (width * data_size));
581 PUSH_DATA (push, height);
582 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
583 PUSH_DATA (push, 0);
584
585 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
586
587 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
588 PUSH_DATA (push, (width << 16));
589 PUSH_DATA (push, (height << 16));
590
591 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
592 PUSH_DATA (push, 0x3c);
593
594 if (width * height != elements) {
595 offset += width * height * data_size;
596 width = elements - width * height;
597 height = 1;
598 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 2);
599 PUSH_DATAh(push, buf->bo->offset + buf->offset + offset);
600 PUSH_DATA (push, buf->bo->offset + buf->offset + offset);
601 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
602 PUSH_DATA (push, NV50_3D_RT_HORIZ_LINEAR | (width * data_size));
603 PUSH_DATA (push, height);
604 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), 1);
605 PUSH_DATA (push, 0x3c);
606 }
607
608 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence);
609 nouveau_fence_ref(nv50->screen->base.fence.current, &buf->fence_wr);
610
611 nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
612 }
613
614 /* =============================== BLIT CODE ===================================
615 */
616
617 struct nv50_blitter
618 {
619 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
620 struct nv50_program vp;
621
622 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
623
624 pipe_mutex mutex;
625 };
626
627 struct nv50_blitctx
628 {
629 struct nv50_context *nv50;
630 struct nv50_program *fp;
631 uint8_t mode;
632 uint16_t color_mask;
633 uint8_t filter;
634 uint8_t render_condition_enable;
635 enum pipe_texture_target target;
636 struct {
637 struct pipe_framebuffer_state fb;
638 struct nv50_rasterizer_stateobj *rast;
639 struct nv50_program *vp;
640 struct nv50_program *gp;
641 struct nv50_program *fp;
642 unsigned num_textures[3];
643 unsigned num_samplers[3];
644 struct pipe_sampler_view *texture[2];
645 struct nv50_tsc_entry *sampler[2];
646 unsigned min_samples;
647 uint32_t dirty;
648 } saved;
649 struct nv50_rasterizer_stateobj rast;
650 };
651
652 static void
653 nv50_blitter_make_vp(struct nv50_blitter *blit)
654 {
655 static const uint32_t code[] =
656 {
657 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
658 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
659 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
660 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
661 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
662 };
663
664 blit->vp.type = PIPE_SHADER_VERTEX;
665 blit->vp.translated = true;
666 blit->vp.code = (uint32_t *)code; /* const_cast */
667 blit->vp.code_size = sizeof(code);
668 blit->vp.max_gpr = 4;
669 blit->vp.max_out = 5;
670 blit->vp.out_nr = 2;
671 blit->vp.out[0].mask = 0x3;
672 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
673 blit->vp.out[1].hw = 2;
674 blit->vp.out[1].mask = 0x7;
675 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
676 blit->vp.out[1].si = 0;
677 blit->vp.vp.attrs[0] = 0x73;
678 blit->vp.vp.psiz = 0x40;
679 blit->vp.vp.edgeflag = 0x40;
680 }
681
682 void *
683 nv50_blitter_make_fp(struct pipe_context *pipe,
684 unsigned mode,
685 enum pipe_texture_target ptarg)
686 {
687 struct ureg_program *ureg;
688 struct ureg_src tc;
689 struct ureg_dst out;
690 struct ureg_dst data;
691
692 const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
693
694 bool tex_rgbaz = false;
695 bool tex_s = false;
696 bool cvt_un8 = false;
697
698 if (mode != NV50_BLIT_MODE_PASS &&
699 mode != NV50_BLIT_MODE_Z24X8 &&
700 mode != NV50_BLIT_MODE_X8Z24)
701 tex_s = true;
702
703 if (mode != NV50_BLIT_MODE_X24S8 &&
704 mode != NV50_BLIT_MODE_S8X24 &&
705 mode != NV50_BLIT_MODE_XS)
706 tex_rgbaz = true;
707
708 if (mode != NV50_BLIT_MODE_PASS &&
709 mode != NV50_BLIT_MODE_ZS &&
710 mode != NV50_BLIT_MODE_XS)
711 cvt_un8 = true;
712
713 ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
714 if (!ureg)
715 return NULL;
716
717 out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
718 tc = ureg_DECL_fs_input(
719 ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
720
721 if (ptarg == PIPE_TEXTURE_1D_ARRAY) {
722 /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
723 tc = ureg_swizzle(tc, TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
724 TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Z);
725 }
726
727 data = ureg_DECL_temporary(ureg);
728
729 if (tex_s) {
730 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
731 target, tc, ureg_DECL_sampler(ureg, 1));
732 ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
733 ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
734 }
735 if (tex_rgbaz) {
736 const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
737 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
738 ureg_TEX(ureg, ureg_writemask(data, mask),
739 target, tc, ureg_DECL_sampler(ureg, 0));
740 }
741
742 if (cvt_un8) {
743 struct ureg_src mask;
744 struct ureg_src scale;
745 struct ureg_dst outz;
746 struct ureg_dst outs;
747 struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
748 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
749 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
750 struct ureg_src zsrc3 = ureg_src(data);
751 struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
752 struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
753 struct ureg_src zshuf;
754
755 mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
756 scale = ureg_imm4f(ureg,
757 1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
758 (1 << 24) - 1);
759
760 if (mode == NV50_BLIT_MODE_Z24S8 ||
761 mode == NV50_BLIT_MODE_X24S8 ||
762 mode == NV50_BLIT_MODE_Z24X8) {
763 outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
764 outs = ureg_writemask(out, TGSI_WRITEMASK_W);
765 zshuf = ureg_src(data);
766 } else {
767 outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
768 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
769 zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
770 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
771 }
772
773 if (tex_s) {
774 ureg_I2F(ureg, sdst, ssrc);
775 ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
776 }
777
778 if (tex_rgbaz) {
779 ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
780 ureg_F2I(ureg, zdst, zsrc);
781 ureg_AND(ureg, zdst3, zsrc, mask);
782 ureg_I2F(ureg, zdst3, zsrc3);
783 ureg_MUL(ureg, zdst3, zsrc3, scale);
784 ureg_MOV(ureg, outz, zshuf);
785 }
786 } else {
787 unsigned mask = TGSI_WRITEMASK_XYZW;
788
789 if (mode != NV50_BLIT_MODE_PASS) {
790 mask &= ~TGSI_WRITEMASK_ZW;
791 if (!tex_s)
792 mask = TGSI_WRITEMASK_X;
793 if (!tex_rgbaz)
794 mask = TGSI_WRITEMASK_Y;
795 }
796 ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
797 }
798 ureg_END(ureg);
799
800 return ureg_create_shader_and_destroy(ureg, pipe);
801 }
802
803 static void
804 nv50_blitter_make_sampler(struct nv50_blitter *blit)
805 {
806 /* clamp to edge, min/max lod = 0, nearest filtering */
807
808 blit->sampler[0].id = -1;
809
810 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
811 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
812 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
813 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
814 blit->sampler[0].tsc[1] =
815 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
816
817 /* clamp to edge, min/max lod = 0, bilinear filtering */
818
819 blit->sampler[1].id = -1;
820
821 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
822 blit->sampler[1].tsc[1] =
823 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
824 }
825
826 unsigned
827 nv50_blit_select_mode(const struct pipe_blit_info *info)
828 {
829 const unsigned mask = info->mask;
830
831 switch (info->dst.resource->format) {
832 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
833 case PIPE_FORMAT_Z24X8_UNORM:
834 case PIPE_FORMAT_X24S8_UINT:
835 switch (mask & PIPE_MASK_ZS) {
836 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
837 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
838 default:
839 return NV50_BLIT_MODE_X24S8;
840 }
841 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
842 case PIPE_FORMAT_X8Z24_UNORM:
843 case PIPE_FORMAT_S8X24_UINT:
844 switch (mask & PIPE_MASK_ZS) {
845 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
846 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
847 default:
848 return NV50_BLIT_MODE_S8X24;
849 }
850 case PIPE_FORMAT_Z32_FLOAT:
851 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
852 case PIPE_FORMAT_X32_S8X24_UINT:
853 switch (mask & PIPE_MASK_ZS) {
854 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
855 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
856 default:
857 return NV50_BLIT_MODE_XS;
858 }
859 default:
860 return NV50_BLIT_MODE_PASS;
861 }
862 }
863
864 static void
865 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
866 {
867 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
868
869 const enum pipe_texture_target ptarg =
870 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
871
872 const unsigned targ = nv50_blit_texture_type(ptarg);
873 const unsigned mode = ctx->mode;
874
875 if (!blitter->fp[targ][mode]) {
876 pipe_mutex_lock(blitter->mutex);
877 if (!blitter->fp[targ][mode])
878 blitter->fp[targ][mode] =
879 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
880 pipe_mutex_unlock(blitter->mutex);
881 }
882 ctx->fp = blitter->fp[targ][mode];
883 }
884
885 static void
886 nv50_blit_set_dst(struct nv50_blitctx *ctx,
887 struct pipe_resource *res, unsigned level, unsigned layer,
888 enum pipe_format format)
889 {
890 struct nv50_context *nv50 = ctx->nv50;
891 struct pipe_context *pipe = &nv50->base.pipe;
892 struct pipe_surface templ;
893
894 if (util_format_is_depth_or_stencil(format))
895 templ.format = nv50_blit_zeta_to_colour_format(format);
896 else
897 templ.format = format;
898
899 templ.u.tex.level = level;
900 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
901
902 if (layer == -1) {
903 templ.u.tex.first_layer = 0;
904 templ.u.tex.last_layer =
905 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
906 }
907
908 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
909 nv50->framebuffer.nr_cbufs = 1;
910 nv50->framebuffer.zsbuf = NULL;
911 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
912 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
913 }
914
915 static void
916 nv50_blit_set_src(struct nv50_blitctx *blit,
917 struct pipe_resource *res, unsigned level, unsigned layer,
918 enum pipe_format format, const uint8_t filter)
919 {
920 struct nv50_context *nv50 = blit->nv50;
921 struct pipe_context *pipe = &nv50->base.pipe;
922 struct pipe_sampler_view templ;
923 uint32_t flags;
924 enum pipe_texture_target target;
925
926 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
927
928 templ.format = format;
929 templ.u.tex.first_level = templ.u.tex.last_level = level;
930 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
931 templ.swizzle_r = PIPE_SWIZZLE_RED;
932 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
933 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
934 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
935
936 if (layer == -1) {
937 templ.u.tex.first_layer = 0;
938 templ.u.tex.last_layer =
939 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
940 }
941
942 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
943 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
944 if (filter && res->nr_samples == 8)
945 flags |= NV50_TEXVIEW_FILTER_MSAA8;
946
947 nv50->textures[2][0] = nv50_create_texture_view(
948 pipe, res, &templ, flags, target);
949 nv50->textures[2][1] = NULL;
950
951 nv50->num_textures[0] = nv50->num_textures[1] = 0;
952 nv50->num_textures[2] = 1;
953
954 templ.format = nv50_zs_to_s_format(format);
955 if (templ.format != res->format) {
956 nv50->textures[2][1] = nv50_create_texture_view(
957 pipe, res, &templ, flags, target);
958 nv50->num_textures[2] = 2;
959 }
960 }
961
962 static void
963 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
964 {
965 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
966
967 if (blit->nv50->cond_query && !blit->render_condition_enable) {
968 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
969 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
970 }
971
972 /* blend state */
973 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
974 PUSH_DATA (push, blit->color_mask);
975 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
976 PUSH_DATA (push, 0);
977 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
978 PUSH_DATA (push, 0);
979
980 /* rasterizer state */
981 #ifndef NV50_SCISSORS_CLIPPING
982 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
983 PUSH_DATA (push, 1);
984 #endif
985 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
986 PUSH_DATA (push, 0);
987 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
988 PUSH_DATA (push, 0);
989 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
990 PUSH_DATA (push, 0);
991 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
992 PUSH_DATA (push, 0xffff);
993 PUSH_DATA (push, 0xffff);
994 PUSH_DATA (push, 0xffff);
995 PUSH_DATA (push, 0xffff);
996 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
997 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
998 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
999 PUSH_DATA (push, 0);
1000 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
1001 PUSH_DATA (push, 0);
1002 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
1003 PUSH_DATA (push, 0);
1004 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
1005 PUSH_DATA (push, 0);
1006
1007 /* zsa state */
1008 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
1009 PUSH_DATA (push, 0);
1010 BEGIN_NV04(push, NV50_3D(DEPTH_BOUNDS_EN), 1);
1011 PUSH_DATA (push, 0);
1012 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
1013 PUSH_DATA (push, 0);
1014 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
1015 PUSH_DATA (push, 0);
1016 }
1017
1018 static void
1019 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
1020 {
1021 struct nv50_context *nv50 = ctx->nv50;
1022 struct nv50_blitter *blitter = nv50->screen->blitter;
1023 int s;
1024
1025 ctx->saved.fb.width = nv50->framebuffer.width;
1026 ctx->saved.fb.height = nv50->framebuffer.height;
1027 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
1028 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
1029 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
1030
1031 ctx->saved.rast = nv50->rast;
1032
1033 ctx->saved.vp = nv50->vertprog;
1034 ctx->saved.gp = nv50->gmtyprog;
1035 ctx->saved.fp = nv50->fragprog;
1036
1037 ctx->saved.min_samples = nv50->min_samples;
1038
1039 nv50->rast = &ctx->rast;
1040
1041 nv50->vertprog = &blitter->vp;
1042 nv50->gmtyprog = NULL;
1043 nv50->fragprog = ctx->fp;
1044
1045 for (s = 0; s < 3; ++s) {
1046 ctx->saved.num_textures[s] = nv50->num_textures[s];
1047 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
1048 }
1049 ctx->saved.texture[0] = nv50->textures[2][0];
1050 ctx->saved.texture[1] = nv50->textures[2][1];
1051 ctx->saved.sampler[0] = nv50->samplers[2][0];
1052 ctx->saved.sampler[1] = nv50->samplers[2][1];
1053
1054 nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
1055 nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
1056
1057 nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
1058 nv50->num_samplers[2] = 2;
1059
1060 nv50->min_samples = 1;
1061
1062 ctx->saved.dirty = nv50->dirty;
1063
1064 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
1065 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
1066
1067 nv50->dirty =
1068 NV50_NEW_FRAMEBUFFER | NV50_NEW_MIN_SAMPLES |
1069 NV50_NEW_VERTPROG | NV50_NEW_FRAGPROG | NV50_NEW_GMTYPROG |
1070 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS;
1071 }
1072
1073 static void
1074 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
1075 {
1076 struct nv50_context *nv50 = blit->nv50;
1077 int s;
1078
1079 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
1080
1081 nv50->framebuffer.width = blit->saved.fb.width;
1082 nv50->framebuffer.height = blit->saved.fb.height;
1083 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1084 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1085 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1086
1087 nv50->rast = blit->saved.rast;
1088
1089 nv50->vertprog = blit->saved.vp;
1090 nv50->gmtyprog = blit->saved.gp;
1091 nv50->fragprog = blit->saved.fp;
1092
1093 nv50->min_samples = blit->saved.min_samples;
1094
1095 pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
1096 pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
1097
1098 for (s = 0; s < 3; ++s) {
1099 nv50->num_textures[s] = blit->saved.num_textures[s];
1100 nv50->num_samplers[s] = blit->saved.num_samplers[s];
1101 }
1102 nv50->textures[2][0] = blit->saved.texture[0];
1103 nv50->textures[2][1] = blit->saved.texture[1];
1104 nv50->samplers[2][0] = blit->saved.sampler[0];
1105 nv50->samplers[2][1] = blit->saved.sampler[1];
1106
1107 if (nv50->cond_query && !blit->render_condition_enable)
1108 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
1109 nv50->cond_cond, nv50->cond_mode);
1110
1111 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
1112 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
1113
1114 nv50->dirty = blit->saved.dirty |
1115 (NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR | NV50_NEW_SAMPLE_MASK |
1116 NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
1117 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
1118 NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
1119 nv50->scissors_dirty |= 1;
1120
1121 nv50->base.pipe.set_min_samples(&nv50->base.pipe, blit->saved.min_samples);
1122 }
1123
1124
1125 static void
1126 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1127 {
1128 struct nv50_blitctx *blit = nv50->blit;
1129 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1130 struct pipe_resource *src = info->src.resource;
1131 struct pipe_resource *dst = info->dst.resource;
1132 int32_t minx, maxx, miny, maxy;
1133 int32_t i;
1134 float x0, x1, y0, y1, z;
1135 float dz;
1136 float x_range, y_range;
1137 float tri_x, tri_y;
1138
1139 blit->mode = nv50_blit_select_mode(info);
1140 blit->color_mask = nv50_blit_derive_color_mask(info);
1141 blit->filter = nv50_blit_get_filter(info);
1142 blit->render_condition_enable = info->render_condition_enable;
1143
1144 nv50_blit_select_fp(blit, info);
1145 nv50_blitctx_pre_blit(blit);
1146
1147 nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1148 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1149 blit->filter);
1150
1151 nv50_blitctx_prepare_state(blit);
1152
1153 nv50_state_validate(nv50, ~0, 36);
1154
1155 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1156 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1157
1158 tri_x = 16384 << nv50_miptree(dst)->ms_x;
1159 tri_y = 16384 << nv50_miptree(dst)->ms_y;
1160
1161 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1162 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1163
1164 x1 = x0 + tri_x * x_range;
1165 y1 = y0 + tri_y * y_range;
1166
1167 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1168 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1169 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1170 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1171
1172 /* XXX: multiply by 6 for cube arrays ? */
1173 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1174 z = (float)info->src.box.z;
1175 if (nv50_miptree(src)->layout_3d)
1176 z += 0.5f * dz;
1177
1178 if (src->last_level > 0) {
1179 /* If there are mip maps, GPU always assumes normalized coordinates. */
1180 const unsigned l = info->src.level;
1181 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1182 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1183 x0 /= fh;
1184 x1 /= fh;
1185 y0 /= fv;
1186 y1 /= fv;
1187 if (nv50_miptree(src)->layout_3d) {
1188 z /= u_minify(src->depth0, l);
1189 dz /= u_minify(src->depth0, l);
1190 }
1191 }
1192
1193 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1194 PUSH_DATA (push, 0);
1195 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1196 PUSH_DATA (push, 0x1);
1197
1198 /* Draw a large triangle in screen coordinates covering the whole
1199 * render target, with scissors defining the destination region.
1200 * The vertex is supplied with non-normalized texture coordinates
1201 * arranged in a way to yield the desired offset and scale.
1202 */
1203
1204 minx = info->dst.box.x;
1205 maxx = info->dst.box.x + info->dst.box.width;
1206 miny = info->dst.box.y;
1207 maxy = info->dst.box.y + info->dst.box.height;
1208 if (info->scissor_enable) {
1209 minx = MAX2(minx, info->scissor.minx);
1210 maxx = MIN2(maxx, info->scissor.maxx);
1211 miny = MAX2(miny, info->scissor.miny);
1212 maxy = MIN2(maxy, info->scissor.maxy);
1213 }
1214 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
1215 PUSH_DATA (push, (maxx << 16) | minx);
1216 PUSH_DATA (push, (maxy << 16) | miny);
1217
1218 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1219 if (info->dst.box.z + i) {
1220 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1221 PUSH_DATA (push, info->dst.box.z + i);
1222 }
1223 PUSH_SPACE(push, 32);
1224 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1225 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1226 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1227 PUSH_DATAf(push, x0);
1228 PUSH_DATAf(push, y0);
1229 PUSH_DATAf(push, z);
1230 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1231 PUSH_DATAf(push, 0.0f);
1232 PUSH_DATAf(push, 0.0f);
1233 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1234 PUSH_DATAf(push, x1);
1235 PUSH_DATAf(push, y0);
1236 PUSH_DATAf(push, z);
1237 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1238 PUSH_DATAf(push, tri_x);
1239 PUSH_DATAf(push, 0.0f);
1240 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1241 PUSH_DATAf(push, x0);
1242 PUSH_DATAf(push, y1);
1243 PUSH_DATAf(push, z);
1244 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1245 PUSH_DATAf(push, 0.0f);
1246 PUSH_DATAf(push, tri_y);
1247 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1248 PUSH_DATA (push, 0);
1249 }
1250 if (info->dst.box.z + info->dst.box.depth - 1) {
1251 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1252 PUSH_DATA (push, 0);
1253 }
1254
1255 /* re-enable normally constant state */
1256
1257 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1258 PUSH_DATA (push, 1);
1259
1260 nv50_blitctx_post_blit(blit);
1261 }
1262
1263 static void
1264 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1265 {
1266 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1267 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1268 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1269 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1270 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1271 const int32_t dz = info->dst.box.z;
1272 const int32_t sz = info->src.box.z;
1273 uint32_t dstw, dsth;
1274 int32_t dstx, dsty;
1275 int64_t srcx, srcy;
1276 int64_t du_dx, dv_dy;
1277 int i;
1278 uint32_t mode;
1279 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1280 bool b;
1281
1282 mode = nv50_blit_get_filter(info) ?
1283 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1284 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1285 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1286 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1287
1288 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1289 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1290
1291 b = info->dst.format == info->src.format;
1292 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1293 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1294
1295 if (info->scissor_enable) {
1296 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1297 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1298 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1299 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1300 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1301 PUSH_DATA (push, 1); /* enable */
1302 }
1303
1304 if (nv50->cond_query && info->render_condition_enable) {
1305 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1306 PUSH_DATA (push, nv50->cond_condmode);
1307 }
1308
1309 if (mask != 0xffffffff) {
1310 BEGIN_NV04(push, NV50_2D(ROP), 1);
1311 PUSH_DATA (push, 0xca); /* DPSDxax */
1312 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1313 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1314 BEGIN_NV04(push, NV50_2D(PATTERN_BITMAP_COLOR(0)), 4);
1315 PUSH_DATA (push, 0x00000000);
1316 PUSH_DATA (push, mask);
1317 PUSH_DATA (push, 0xffffffff);
1318 PUSH_DATA (push, 0xffffffff);
1319 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1320 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1321 } else
1322 if (info->src.format != info->dst.format) {
1323 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1324 info->src.format == PIPE_FORMAT_R16_UNORM ||
1325 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1326 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1327 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1328 BEGIN_NV04(push, NV50_2D(BETA4), 2);
1329 PUSH_DATA (push, mask);
1330 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1331 }
1332 }
1333
1334 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1335 /* ms_x is always >= ms_y */
1336 du_dx <<= src->ms_x - dst->ms_x;
1337 dv_dy <<= src->ms_y - dst->ms_y;
1338 } else {
1339 du_dx >>= dst->ms_x - src->ms_x;
1340 dv_dy >>= dst->ms_y - src->ms_y;
1341 }
1342
1343 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1344 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1345
1346 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1347 /* center src coorinates for proper MS resolve filtering */
1348 srcx += (int64_t)1 << (src->ms_x + 31);
1349 srcy += (int64_t)1 << (src->ms_y + 31);
1350 }
1351
1352 dstx = info->dst.box.x << dst->ms_x;
1353 dsty = info->dst.box.y << dst->ms_y;
1354
1355 dstw = info->dst.box.width << dst->ms_x;
1356 dsth = info->dst.box.height << dst->ms_y;
1357
1358 if (dstx < 0) {
1359 dstw += dstx;
1360 srcx -= du_dx * dstx;
1361 dstx = 0;
1362 }
1363 if (dsty < 0) {
1364 dsth += dsty;
1365 srcy -= dv_dy * dsty;
1366 dsty = 0;
1367 }
1368
1369 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1370 PUSH_DATA (push, mode);
1371 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1372 PUSH_DATA (push, dstx);
1373 PUSH_DATA (push, dsty);
1374 PUSH_DATA (push, dstw);
1375 PUSH_DATA (push, dsth);
1376 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1377 PUSH_DATA (push, du_dx);
1378 PUSH_DATA (push, du_dx >> 32);
1379 PUSH_DATA (push, dv_dy);
1380 PUSH_DATA (push, dv_dy >> 32);
1381
1382 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1383 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1384 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1385 if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1386 return;
1387
1388 for (i = 0; i < info->dst.box.depth; ++i) {
1389 if (i > 0) {
1390 /* no scaling in z-direction possible for eng2d blits */
1391 if (dst->layout_3d) {
1392 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1393 PUSH_DATA (push, info->dst.box.z + i);
1394 } else {
1395 const unsigned z = info->dst.box.z + i;
1396 const uint64_t address = dst->base.address +
1397 dst->level[info->dst.level].offset +
1398 z * dst->layer_stride;
1399 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1400 PUSH_DATAh(push, address);
1401 PUSH_DATA (push, address);
1402 }
1403 if (src->layout_3d) {
1404 /* not possible because of depth tiling */
1405 assert(0);
1406 } else {
1407 const unsigned z = info->src.box.z + i;
1408 const uint64_t address = src->base.address +
1409 src->level[info->src.level].offset +
1410 z * src->layer_stride;
1411 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1412 PUSH_DATAh(push, address);
1413 PUSH_DATA (push, address);
1414 }
1415 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1416 PUSH_DATA (push, srcy >> 32);
1417 } else {
1418 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1419 PUSH_DATA (push, srcx);
1420 PUSH_DATA (push, srcx >> 32);
1421 PUSH_DATA (push, srcy);
1422 PUSH_DATA (push, srcy >> 32);
1423 }
1424 }
1425 nv50_bufctx_fence(nv50->bufctx, false);
1426
1427 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1428
1429 if (info->scissor_enable) {
1430 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1431 PUSH_DATA (push, 0);
1432 }
1433 if (mask != 0xffffffff) {
1434 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1435 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1436 }
1437 if (nv50->cond_query && info->render_condition_enable) {
1438 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
1439 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1440 }
1441 }
1442
1443 static void
1444 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1445 {
1446 struct nv50_context *nv50 = nv50_context(pipe);
1447 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1448 bool eng3d = FALSE;
1449
1450 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1451 if (!(info->mask & PIPE_MASK_ZS))
1452 return;
1453 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1454 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1455 eng3d = true;
1456 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1457 eng3d = true;
1458 } else {
1459 if (!(info->mask & PIPE_MASK_RGBA))
1460 return;
1461 if (info->mask != PIPE_MASK_RGBA)
1462 eng3d = true;
1463 }
1464
1465 if (nv50_miptree(info->src.resource)->layout_3d) {
1466 eng3d = true;
1467 } else
1468 if (info->src.box.depth != info->dst.box.depth) {
1469 eng3d = true;
1470 debug_printf("blit: cannot filter array or cube textures in z direction");
1471 }
1472
1473 if (!eng3d && info->dst.format != info->src.format) {
1474 if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1475 !nv50_2d_src_format_faithful(info->src.format)) {
1476 eng3d = true;
1477 } else
1478 if (!nv50_2d_src_format_faithful(info->src.format)) {
1479 if (!util_format_is_luminance(info->src.format)) {
1480 if (util_format_is_intensity(info->src.format))
1481 eng3d = true;
1482 else
1483 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1484 eng3d = true;
1485 else
1486 eng3d = !nv50_2d_format_supported(info->src.format);
1487 }
1488 } else
1489 if (util_format_is_luminance_alpha(info->src.format))
1490 eng3d = true;
1491 }
1492
1493 if (info->src.resource->nr_samples == 8 &&
1494 info->dst.resource->nr_samples <= 1)
1495 eng3d = true;
1496
1497 /* FIXME: can't make this work with eng2d anymore */
1498 if ((info->src.resource->nr_samples | 1) !=
1499 (info->dst.resource->nr_samples | 1))
1500 eng3d = true;
1501
1502 /* FIXME: find correct src coordinate adjustments */
1503 if ((info->src.box.width != info->dst.box.width &&
1504 info->src.box.width != -info->dst.box.width) ||
1505 (info->src.box.height != info->dst.box.height &&
1506 info->src.box.height != -info->dst.box.height))
1507 eng3d = true;
1508
1509 if (nv50->screen->num_occlusion_queries_active) {
1510 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1511 PUSH_DATA (push, 0);
1512 }
1513
1514 if (!eng3d)
1515 nv50_blit_eng2d(nv50, info);
1516 else
1517 nv50_blit_3d(nv50, info);
1518
1519 if (nv50->screen->num_occlusion_queries_active) {
1520 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
1521 PUSH_DATA (push, 1);
1522 }
1523 }
1524
1525 static void
1526 nv50_flush_resource(struct pipe_context *ctx,
1527 struct pipe_resource *resource)
1528 {
1529 }
1530
1531 bool
1532 nv50_blitter_create(struct nv50_screen *screen)
1533 {
1534 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1535 if (!screen->blitter) {
1536 NOUVEAU_ERR("failed to allocate blitter struct\n");
1537 return false;
1538 }
1539
1540 pipe_mutex_init(screen->blitter->mutex);
1541
1542 nv50_blitter_make_vp(screen->blitter);
1543 nv50_blitter_make_sampler(screen->blitter);
1544
1545 return true;
1546 }
1547
1548 void
1549 nv50_blitter_destroy(struct nv50_screen *screen)
1550 {
1551 struct nv50_blitter *blitter = screen->blitter;
1552 unsigned i, m;
1553
1554 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1555 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1556 struct nv50_program *prog = blitter->fp[i][m];
1557 if (prog) {
1558 nv50_program_destroy(NULL, prog);
1559 FREE((void *)prog->pipe.tokens);
1560 FREE(prog);
1561 }
1562 }
1563 }
1564
1565 FREE(blitter);
1566 }
1567
1568 bool
1569 nv50_blitctx_create(struct nv50_context *nv50)
1570 {
1571 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1572 if (!nv50->blit) {
1573 NOUVEAU_ERR("failed to allocate blit context\n");
1574 return false;
1575 }
1576
1577 nv50->blit->nv50 = nv50;
1578
1579 nv50->blit->rast.pipe.half_pixel_center = 1;
1580
1581 return true;
1582 }
1583
1584 void
1585 nv50_init_surface_functions(struct nv50_context *nv50)
1586 {
1587 struct pipe_context *pipe = &nv50->base.pipe;
1588
1589 pipe->resource_copy_region = nv50_resource_copy_region;
1590 pipe->blit = nv50_blit;
1591 pipe->flush_resource = nv50_flush_resource;
1592 pipe->clear_render_target = nv50_clear_render_target;
1593 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1594 pipe->clear_buffer = nv50_clear_buffer;
1595 }