src/gallium/drivers/nouveau/nv50/nv50_tex.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "nv50/nv50_context.h"
  24 #include "nv50/nv50_resource.h"
  25 #include "nv50/nv50_texture.xml.h"
  26 #include "nv50/nv50_defs.xml.h"
  27
  28 #include "util/u_format.h"
  29
  30 #define NV50_TIC_0_SWIZZLE__MASK                      \
  31    (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK |   \
  32     NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK)
  33
  34 static inline uint32_t
  35 nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int)
  36 {
  37    switch (swz) {
  38    case PIPE_SWIZZLE_RED:
  39       return (tc & NV50_TIC_0_MAPR__MASK) >> NV50_TIC_0_MAPR__SHIFT;
  40    case PIPE_SWIZZLE_GREEN:
  41       return (tc & NV50_TIC_0_MAPG__MASK) >> NV50_TIC_0_MAPG__SHIFT;
  42    case PIPE_SWIZZLE_BLUE:
  43       return (tc & NV50_TIC_0_MAPB__MASK) >> NV50_TIC_0_MAPB__SHIFT;
  44    case PIPE_SWIZZLE_ALPHA:
  45       return (tc & NV50_TIC_0_MAPA__MASK) >> NV50_TIC_0_MAPA__SHIFT;
  46    case PIPE_SWIZZLE_ONE:
  47       return tex_int ? NV50_TIC_MAP_ONE_INT : NV50_TIC_MAP_ONE_FLOAT;
  48    case PIPE_SWIZZLE_ZERO:
  49    default:
  50       return NV50_TIC_MAP_ZERO;
  51    }
  52 }
  53
  54 struct pipe_sampler_view *
  55 nv50_create_sampler_view(struct pipe_context *pipe,
  56                          struct pipe_resource *res,
  57                          const struct pipe_sampler_view *templ)
  58 {
  59    uint32_t flags = 0;
  60
  61    if (templ->target == PIPE_TEXTURE_RECT || templ->target == PIPE_BUFFER)
  62       flags |= NV50_TEXVIEW_SCALED_COORDS;
  63
  64    return nv50_create_texture_view(pipe, res, templ, flags, templ->target);
  65 }
  66
  67 struct pipe_sampler_view *
  68 nv50_create_texture_view(struct pipe_context *pipe,
  69                          struct pipe_resource *texture,
  70                          const struct pipe_sampler_view *templ,
  71                          uint32_t flags,
  72                          enum pipe_texture_target target)
  73 {
  74    const uint32_t class_3d = nouveau_context(pipe)->screen->class_3d;
  75    const struct util_format_description *desc;
  76    uint64_t addr;
  77    uint32_t *tic;
  78    uint32_t swz[4];
  79    uint32_t depth;
  80    struct nv50_tic_entry *view;
  81    struct nv50_miptree *mt = nv50_miptree(texture);
  82    bool tex_int;
  83
  84    view = MALLOC_STRUCT(nv50_tic_entry);
  85    if (!view)
  86       return NULL;
  87
  88    view->pipe = *templ;
  89    view->pipe.reference.count = 1;
  90    view->pipe.texture = NULL;
  91    view->pipe.context = pipe;
  92
  93    view->id = -1;
  94
  95    pipe_resource_reference(&view->pipe.texture, texture);
  96
  97    tic = &view->tic[0];
  98
  99    desc = util_format_description(view->pipe.format);
 100
 101    /* TIC[0] */
 102
 103    tic[0] = nv50_format_table[view->pipe.format].tic;
 104
 105    tex_int = util_format_is_pure_integer(view->pipe.format);
 106
 107    swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int);
 108    swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
 109    swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
 110    swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
 111    tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) |
 112       (swz[0] << NV50_TIC_0_MAPR__SHIFT) |
 113       (swz[1] << NV50_TIC_0_MAPG__SHIFT) |
 114       (swz[2] << NV50_TIC_0_MAPB__SHIFT) |
 115       (swz[3] << NV50_TIC_0_MAPA__SHIFT);
 116
 117    addr = mt->base.address;
 118
 119    depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
 120
 121    if (mt->base.base.array_size > 1) {
 122       /* there doesn't seem to be a base layer field in TIC */
 123       addr += view->pipe.u.tex.first_layer * mt->layer_stride;
 124       depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
 125    }
 126
 127    tic[2] = 0x10001000 | NV50_TIC_2_NO_BORDER;
 128
 129    if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 130       tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
 131
 132    if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
 133       tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
 134
 135    if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
 136       if (target == PIPE_BUFFER) {
 137          addr += view->pipe.u.buf.first_element * desc->block.bits / 8;
 138          tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_BUFFER;
 139          tic[3] = 0;
 140          tic[4] = /* width */
 141             view->pipe.u.buf.last_element - view->pipe.u.buf.first_element + 1;
 142          tic[5] = 0;
 143       } else {
 144          tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
 145          tic[3] = mt->level[0].pitch;
 146          tic[4] = mt->base.base.width0;
 147          tic[5] = (1 << 16) | (mt->base.base.height0);
 148       }
 149       tic[6] =
 150       tic[7] = 0;
 151       tic[1] = addr;
 152       tic[2] |= addr >> 32;
 153       return &view->pipe;
 154    }
 155
 156    tic[1] = addr;
 157    tic[2] |= (addr >> 32) & 0xff;
 158
 159    tic[2] |=
 160       ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) |
 161       ((mt->level[0].tile_mode & 0xf00) << (25 - 8));
 162
 163    switch (target) {
 164    case PIPE_TEXTURE_1D:
 165       tic[2] |= NV50_TIC_2_TARGET_1D;
 166       break;
 167    case PIPE_TEXTURE_2D:
 168       tic[2] |= NV50_TIC_2_TARGET_2D;
 169       break;
 170    case PIPE_TEXTURE_RECT:
 171       tic[2] |= NV50_TIC_2_TARGET_RECT;
 172       break;
 173    case PIPE_TEXTURE_3D:
 174       tic[2] |= NV50_TIC_2_TARGET_3D;
 175       break;
 176    case PIPE_TEXTURE_CUBE:
 177       depth /= 6;
 178       tic[2] |= NV50_TIC_2_TARGET_CUBE;
 179       break;
 180    case PIPE_TEXTURE_1D_ARRAY:
 181       tic[2] |= NV50_TIC_2_TARGET_1D_ARRAY;
 182       break;
 183    case PIPE_TEXTURE_2D_ARRAY:
 184       tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY;
 185       break;
 186    case PIPE_TEXTURE_CUBE_ARRAY:
 187       depth /= 6;
 188       tic[2] |= NV50_TIC_2_TARGET_CUBE_ARRAY;
 189       break;
 190    case PIPE_BUFFER:
 191       assert(0); /* should be linear and handled above ! */
 192       tic[2] |= NV50_TIC_2_TARGET_BUFFER | NV50_TIC_2_LINEAR;
 193       break;
 194    default:
 195       unreachable("unexpected/invalid texture target");
 196    }
 197
 198    tic[3] = (flags & NV50_TEXVIEW_FILTER_MSAA8) ? 0x20000000 : 0x00300000;
 199
 200    tic[4] = (1 << 31) | (mt->base.base.width0 << mt->ms_x);
 201
 202    tic[5] = (mt->base.base.height0 << mt->ms_y) & 0xffff;
 203    tic[5] |= depth << 16;
 204    if (class_3d > NV50_3D_CLASS)
 205       tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
 206    else
 207       tic[5] |= view->pipe.u.tex.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
 208
 209    tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000; /* sampling points */
 210
 211    if (class_3d > NV50_3D_CLASS)
 212       tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
 213    else
 214       tic[7] = 0;
 215
 216    if (unlikely(!(tic[2] & NV50_TIC_2_NORMALIZED_COORDS)))
 217       if (mt->base.base.last_level)
 218          tic[5] &= ~NV50_TIC_5_LAST_LEVEL__MASK;
 219
 220    return &view->pipe;
 221 }
 222
 223 static void
 224 nv50_update_tic(struct nv50_context *nv50, struct nv50_tic_entry *tic,
 225                 struct nv04_resource *res)
 226 {
 227    uint64_t address = res->address;
 228    if (res->base.target != PIPE_BUFFER)
 229       return;
 230    address += tic->pipe.u.buf.first_element *
 231       util_format_get_blocksize(tic->pipe.format);
 232    if (tic->tic[1] == (uint32_t)address &&
 233        (tic->tic[2] & 0xff) == address >> 32)
 234       return;
 235
 236    nv50_screen_tic_unlock(nv50->screen, tic);
 237    tic->id = -1;
 238    tic->tic[1] = address;
 239    tic->tic[2] &= 0xffffff00;
 240    tic->tic[2] |= address >> 32;
 241 }
 242
 243 static bool
 244 nv50_validate_tic(struct nv50_context *nv50, int s)
 245 {
 246    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 247    struct nouveau_bo *txc = nv50->screen->txc;
 248    unsigned i;
 249    bool need_flush = false;
 250
 251    assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
 252    for (i = 0; i < nv50->num_textures[s]; ++i) {
 253       struct nv50_tic_entry *tic = nv50_tic_entry(nv50->textures[s][i]);
 254       struct nv04_resource *res;
 255
 256       if (!tic) {
 257          BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
 258          PUSH_DATA (push, (i << 1) | 0);
 259          continue;
 260       }
 261       res = &nv50_miptree(tic->pipe.texture)->base;
 262       nv50_update_tic(nv50, tic, res);
 263
 264       if (tic->id < 0) {
 265          tic->id = nv50_screen_tic_alloc(nv50->screen, tic);
 266
 267          BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
 268          PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
 269          PUSH_DATA (push, 1);
 270          BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
 271          PUSH_DATA (push, 262144);
 272          PUSH_DATA (push, 65536);
 273          PUSH_DATA (push, 1);
 274          PUSH_DATAh(push, txc->offset);
 275          PUSH_DATA (push, txc->offset);
 276          BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
 277          PUSH_DATA (push, 0);
 278          PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
 279          BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
 280          PUSH_DATA (push, 32);
 281          PUSH_DATA (push, 1);
 282          PUSH_DATA (push, 0);
 283          PUSH_DATA (push, 1);
 284          PUSH_DATA (push, 0);
 285          PUSH_DATA (push, 1);
 286          PUSH_DATA (push, 0);
 287          PUSH_DATA (push, tic->id * 32);
 288          PUSH_DATA (push, 0);
 289          PUSH_DATA (push, 0);
 290          BEGIN_NI04(push, NV50_2D(SIFC_DATA), 8);
 291          PUSH_DATAp(push, &tic->tic[0], 8);
 292
 293          need_flush = true;
 294       } else
 295       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 296          BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
 297          PUSH_DATA (push, 0x20);
 298       }
 299
 300       nv50->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
 301
 302       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 303       res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
 304
 305       BCTX_REFN(nv50->bufctx_3d, TEXTURES, res, RD);
 306
 307       BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
 308       PUSH_DATA (push, (tic->id << 9) | (i << 1) | 1);
 309    }
 310    for (; i < nv50->state.num_textures[s]; ++i) {
 311       BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
 312       PUSH_DATA (push, (i << 1) | 0);
 313    }
 314    if (nv50->num_textures[s]) {
 315       BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 316       PUSH_DATA (push, ((NV50_CB_AUX_TEX_MS_OFFSET + 16 * s * 2 * 4) << (8 - 2)) | NV50_CB_AUX);
 317       BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nv50->num_textures[s] * 2);
 318       for (i = 0; i < nv50->num_textures[s]; i++) {
 319          struct nv50_tic_entry *tic = nv50_tic_entry(nv50->textures[s][i]);
 320          struct nv50_miptree *res;
 321
 322          if (!tic) {
 323             PUSH_DATA (push, 0);
 324             PUSH_DATA (push, 0);
 325             continue;
 326          }
 327          res = nv50_miptree(tic->pipe.texture);
 328          PUSH_DATA (push, res->ms_x);
 329          PUSH_DATA (push, res->ms_y);
 330       }
 331    }
 332    nv50->state.num_textures[s] = nv50->num_textures[s];
 333
 334    return need_flush;
 335 }
 336
 337 void nv50_validate_textures(struct nv50_context *nv50)
 338 {
 339    bool need_flush;
 340
 341    need_flush  = nv50_validate_tic(nv50, 0);
 342    need_flush |= nv50_validate_tic(nv50, 1);
 343    need_flush |= nv50_validate_tic(nv50, 2);
 344
 345    if (need_flush) {
 346       BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TIC_FLUSH), 1);
 347       PUSH_DATA (nv50->base.pushbuf, 0);
 348    }
 349 }
 350
 351 static bool
 352 nv50_validate_tsc(struct nv50_context *nv50, int s)
 353 {
 354    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 355    unsigned i;
 356    bool need_flush = false;
 357
 358    assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
 359    for (i = 0; i < nv50->num_samplers[s]; ++i) {
 360       struct nv50_tsc_entry *tsc = nv50_tsc_entry(nv50->samplers[s][i]);
 361
 362       if (!tsc) {
 363          BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
 364          PUSH_DATA (push, (i << 4) | 0);
 365          continue;
 366       }
 367       if (tsc->id < 0) {
 368          tsc->id = nv50_screen_tsc_alloc(nv50->screen, tsc);
 369
 370          nv50_sifc_linear_u8(&nv50->base, nv50->screen->txc,
 371                              65536 + tsc->id * 32,
 372                              NOUVEAU_BO_VRAM, 32, tsc->tsc);
 373          need_flush = true;
 374       }
 375       nv50->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
 376
 377       BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
 378       PUSH_DATA (push, (tsc->id << 12) | (i << 4) | 1);
 379    }
 380    for (; i < nv50->state.num_samplers[s]; ++i) {
 381       BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
 382       PUSH_DATA (push, (i << 4) | 0);
 383    }
 384    nv50->state.num_samplers[s] = nv50->num_samplers[s];
 385
 386    return need_flush;
 387 }
 388
 389 void nv50_validate_samplers(struct nv50_context *nv50)
 390 {
 391    bool need_flush;
 392
 393    need_flush  = nv50_validate_tsc(nv50, 0);
 394    need_flush |= nv50_validate_tsc(nv50, 1);
 395    need_flush |= nv50_validate_tsc(nv50, 2);
 396
 397    if (need_flush) {
 398       BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TSC_FLUSH), 1);
 399       PUSH_DATA (nv50->base.pushbuf, 0);
 400    }
 401 }
 402
 403 /* There can be up to 4 different MS levels (1, 2, 4, 8). To simplify the
 404  * shader logic, allow each one to take up 8 offsets.
 405  */
 406 #define COMBINE(x, y) x, y
 407 #define DUMMY 0, 0
 408 static const uint32_t msaa_sample_xy_offsets[] = {
 409    /* MS1 */
 410    COMBINE(0, 0),
 411    DUMMY,
 412    DUMMY,
 413    DUMMY,
 414    DUMMY,
 415    DUMMY,
 416    DUMMY,
 417    DUMMY,
 418
 419    /* MS2 */
 420    COMBINE(0, 0),
 421    COMBINE(1, 0),
 422    DUMMY,
 423    DUMMY,
 424    DUMMY,
 425    DUMMY,
 426    DUMMY,
 427    DUMMY,
 428
 429    /* MS4 */
 430    COMBINE(0, 0),
 431    COMBINE(1, 0),
 432    COMBINE(0, 1),
 433    COMBINE(1, 1),
 434    DUMMY,
 435    DUMMY,
 436    DUMMY,
 437    DUMMY,
 438
 439    /* MS8 */
 440    COMBINE(0, 0),
 441    COMBINE(1, 0),
 442    COMBINE(0, 1),
 443    COMBINE(1, 1),
 444    COMBINE(2, 0),
 445    COMBINE(3, 0),
 446    COMBINE(2, 1),
 447    COMBINE(3, 1),
 448 };
 449
 450 void nv50_upload_ms_info(struct nouveau_pushbuf *push)
 451 {
 452    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 453    PUSH_DATA (push, (NV50_CB_AUX_MS_OFFSET << (8 - 2)) | NV50_CB_AUX);
 454    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), Elements(msaa_sample_xy_offsets));
 455    PUSH_DATAp(push, msaa_sample_xy_offsets, Elements(msaa_sample_xy_offsets));
 456 }