projects / mesa.git / blob
? search:


600b973c5f63b95fb6b9ea702778efcb3b94eca7
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nv50/nv50_context.h"
30 #include "nv50/nv50_resource.h"
31
32 #include "nv50/nv50_3d.xml.h"
33
34 void
35 nv50_vertex_state_delete(struct pipe_context *pipe,
36 void *hwcso)
37 {
38 struct nv50_vertex_stateobj *so = hwcso;
39
40 if (so->translate)
41 so->translate->release(so->translate);
42 FREE(hwcso);
43 }
44
45 void *
46 nv50_vertex_state_create(struct pipe_context *pipe,
47 unsigned num_elements,
48 const struct pipe_vertex_element *elements)
49 {
50 struct nv50_vertex_stateobj *so;
51 struct translate_key transkey;
52 unsigned i;
53
54 so = MALLOC(sizeof(*so) +
55 num_elements * sizeof(struct nv50_vertex_element));
56 if (!so)
57 return NULL;
58 so->num_elements = num_elements;
59 so->instance_elts = 0;
60 so->instance_bufs = 0;
61 so->need_conversion = false;
62
63 memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
64
65 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
66 so->min_instance_div[i] = 0xffffffff;
67
68 transkey.nr_elements = 0;
69 transkey.output_stride = 0;
70
71 for (i = 0; i < num_elements; ++i) {
72 const struct pipe_vertex_element *ve = &elements[i];
73 const unsigned vbi = ve->vertex_buffer_index;
74 unsigned size;
75 enum pipe_format fmt = ve->src_format;
76
77 so->element[i].pipe = elements[i];
78 so->element[i].state = nv50_format_table[fmt].vtx;
79
80 if (!so->element[i].state) {
81 switch (util_format_get_nr_components(fmt)) {
82 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
83 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
84 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
85 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
86 default:
87 assert(0);
88 FREE(so);
89 return NULL;
90 }
91 so->element[i].state = nv50_format_table[fmt].vtx;
92 so->need_conversion = true;
93 }
94 so->element[i].state |= i;
95
96 size = util_format_get_blocksize(fmt);
97 if (so->vb_access_size[vbi] < (ve->src_offset + size))
98 so->vb_access_size[vbi] = ve->src_offset + size;
99
100 if (1) {
101 unsigned j = transkey.nr_elements++;
102
103 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
104 transkey.element[j].input_format = ve->src_format;
105 transkey.element[j].input_buffer = vbi;
106 transkey.element[j].input_offset = ve->src_offset;
107 transkey.element[j].instance_divisor = ve->instance_divisor;
108
109 transkey.element[j].output_format = fmt;
110 transkey.element[j].output_offset = transkey.output_stride;
111 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
112
113 if (unlikely(ve->instance_divisor)) {
114 so->instance_elts |= 1 << i;
115 so->instance_bufs |= 1 << vbi;
116 if (ve->instance_divisor < so->min_instance_div[vbi])
117 so->min_instance_div[vbi] = ve->instance_divisor;
118 }
119 }
120 }
121
122 so->translate = translate_create(&transkey);
123 so->vertex_size = transkey.output_stride / 4;
124 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
125 MAX2(so->vertex_size, 1);
126
127 return so;
128 }
129
130 #define NV50_3D_VERTEX_ATTRIB_INACTIVE \
131 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \
132 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
133 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
134
135 static void
136 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
137 struct pipe_vertex_element *ve, unsigned attr)
138 {
139 struct nouveau_pushbuf *push = nv50->base.pushbuf;
140 const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
141 float v[4];
142 const unsigned nc = util_format_get_nr_components(ve->src_format);
143 const struct util_format_description *desc =
144 util_format_description(ve->src_format);
145
146 assert(vb->user_buffer);
147
148 if (desc->channel[0].pure_integer) {
149 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
150 desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
151 } else {
152 desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
153 }
154 } else {
155 desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
156 }
157
158 switch (nc) {
159 case 4:
160 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
161 PUSH_DATAf(push, v[0]);
162 PUSH_DATAf(push, v[1]);
163 PUSH_DATAf(push, v[2]);
164 PUSH_DATAf(push, v[3]);
165 break;
166 case 3:
167 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
168 PUSH_DATAf(push, v[0]);
169 PUSH_DATAf(push, v[1]);
170 PUSH_DATAf(push, v[2]);
171 break;
172 case 2:
173 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
174 PUSH_DATAf(push, v[0]);
175 PUSH_DATAf(push, v[1]);
176 break;
177 case 1:
178 if (attr == nv50->vertprog->vp.edgeflag) {
179 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
180 PUSH_DATA (push, v[0] ? 1 : 0);
181 }
182 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
183 PUSH_DATAf(push, v[0]);
184 break;
185 default:
186 assert(0);
187 break;
188 }
189 }
190
191 static inline void
192 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
193 uint32_t *base, uint32_t *size)
194 {
195 assert(vbi < PIPE_MAX_ATTRIBS);
196 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
197 /* TODO: use min and max instance divisor to get a proper range */
198 *base = 0;
199 *size = nv50->vtxbuf[vbi].buffer->width0;
200 } else {
201 /* NOTE: if there are user buffers, we *must* have index bounds */
202 assert(nv50->vb_elt_limit != ~0);
203 *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
204 *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
205 nv50->vertex->vb_access_size[vbi];
206 }
207 }
208
209 static void
210 nv50_upload_user_buffers(struct nv50_context *nv50,
211 uint64_t addrs[], uint32_t limits[])
212 {
213 unsigned b;
214
215 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
216 for (b = 0; b < nv50->num_vtxbufs; ++b) {
217 struct nouveau_bo *bo;
218 const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
219 uint32_t base, size;
220
221 if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
222 continue;
223 nv50_user_vbuf_range(nv50, b, &base, &size);
224
225 limits[b] = base + size - 1;
226 addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size,
227 &bo);
228 if (addrs[b])
229 BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART |
230 NOUVEAU_BO_RD, bo);
231 }
232 nv50->base.vbo_dirty = true;
233 }
234
235 static void
236 nv50_update_user_vbufs(struct nv50_context *nv50)
237 {
238 uint64_t address[PIPE_MAX_ATTRIBS];
239 struct nouveau_pushbuf *push = nv50->base.pushbuf;
240 unsigned i;
241 uint32_t written = 0;
242
243 for (i = 0; i < nv50->vertex->num_elements; ++i) {
244 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
245 const unsigned b = ve->vertex_buffer_index;
246 struct pipe_vertex_buffer *vb;
247 uint32_t base, size;
248
249 assert(b < PIPE_MAX_ATTRIBS);
250 vb = &nv50->vtxbuf[b];
251
252 if (!(nv50->vbo_user & (1 << b)))
253 continue;
254
255 if (!vb->stride) {
256 nv50_emit_vtxattr(nv50, vb, ve, i);
257 continue;
258 }
259 nv50_user_vbuf_range(nv50, b, &base, &size);
260
261 if (!(written & (1 << b))) {
262 struct nouveau_bo *bo;
263 const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
264 written |= 1 << b;
265 address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer,
266 base, size, &bo);
267 if (address[b])
268 BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo);
269 }
270
271 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
272 PUSH_DATAh(push, address[b] + base + size - 1);
273 PUSH_DATA (push, address[b] + base + size - 1);
274 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
275 PUSH_DATAh(push, address[b] + ve->src_offset);
276 PUSH_DATA (push, address[b] + ve->src_offset);
277 }
278 nv50->base.vbo_dirty = true;
279 }
280
281 static inline void
282 nv50_release_user_vbufs(struct nv50_context *nv50)
283 {
284 if (nv50->vbo_user) {
285 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP);
286 nouveau_scratch_done(&nv50->base);
287 }
288 }
289
290 void
291 nv50_vertex_arrays_validate(struct nv50_context *nv50)
292 {
293 uint64_t addrs[PIPE_MAX_ATTRIBS];
294 uint32_t limits[PIPE_MAX_ATTRIBS];
295 struct nouveau_pushbuf *push = nv50->base.pushbuf;
296 struct nv50_vertex_stateobj *vertex = nv50->vertex;
297 struct pipe_vertex_buffer *vb;
298 struct nv50_vertex_element *ve;
299 uint32_t mask;
300 uint32_t refd = 0;
301 unsigned i;
302 const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
303
304 if (unlikely(vertex->need_conversion))
305 nv50->vbo_fifo = ~0;
306 else
307 if (nv50->vbo_user & ~nv50->vbo_constant)
308 nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
309 else
310 nv50->vbo_fifo = 0;
311
312 if (!nv50->vbo_fifo) {
313 /* if vertex buffer was written by GPU - flush VBO cache */
314 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
315 for (i = 0; i < nv50->num_vtxbufs; ++i) {
316 struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer);
317 if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
318 buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
319 nv50->base.vbo_dirty = true;
320 }
321 }
322 }
323
324 /* update vertex format state */
325 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
326 if (nv50->vbo_fifo) {
327 nv50->state.num_vtxelts = vertex->num_elements;
328 for (i = 0; i < vertex->num_elements; ++i)
329 PUSH_DATA (push, vertex->element[i].state);
330 for (; i < n; ++i)
331 PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
332 for (i = 0; i < n; ++i) {
333 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
334 PUSH_DATA (push, 0);
335 }
336 return;
337 }
338 for (i = 0; i < vertex->num_elements; ++i) {
339 const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
340
341 assert(b < PIPE_MAX_ATTRIBS);
342 ve = &vertex->element[i];
343 vb = &nv50->vtxbuf[b];
344
345 if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
346 PUSH_DATA(push, ve->state);
347 else
348 PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
349 }
350 for (; i < n; ++i)
351 PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
352
353 /* update per-instance enables */
354 mask = vertex->instance_elts ^ nv50->state.instance_elts;
355 while (mask) {
356 const int i = ffs(mask) - 1;
357 mask &= ~(1 << i);
358 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
359 PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
360 }
361 nv50->state.instance_elts = vertex->instance_elts;
362
363 if (nv50->vbo_user & ~nv50->vbo_constant)
364 nv50_upload_user_buffers(nv50, addrs, limits);
365
366 /* update buffers and set constant attributes */
367 for (i = 0; i < vertex->num_elements; ++i) {
368 uint64_t address, limit;
369 const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
370
371 assert(b < PIPE_MAX_ATTRIBS);
372 ve = &vertex->element[i];
373 vb = &nv50->vtxbuf[b];
374
375 if (unlikely(nv50->vbo_constant & (1 << b))) {
376 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
377 PUSH_DATA (push, 0);
378 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
379 continue;
380 } else
381 if (nv50->vbo_user & (1 << b)) {
382 address = addrs[b] + ve->pipe.src_offset;
383 limit = addrs[b] + limits[b];
384 } else
385 if (!vb->buffer) {
386 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
387 PUSH_DATA (push, 0);
388 continue;
389 } else {
390 struct nv04_resource *buf = nv04_resource(vb->buffer);
391 if (!(refd & (1 << b))) {
392 refd |= 1 << b;
393 BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
394 }
395 address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
396 limit = buf->address + buf->base.width0 - 1;
397 }
398
399 if (unlikely(ve->pipe.instance_divisor)) {
400 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
401 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
402 PUSH_DATAh(push, address);
403 PUSH_DATA (push, address);
404 PUSH_DATA (push, ve->pipe.instance_divisor);
405 } else {
406 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
407 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
408 PUSH_DATAh(push, address);
409 PUSH_DATA (push, address);
410 }
411 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
412 PUSH_DATAh(push, limit);
413 PUSH_DATA (push, limit);
414 }
415 for (; i < nv50->state.num_vtxelts; ++i) {
416 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
417 PUSH_DATA (push, 0);
418 }
419 nv50->state.num_vtxelts = vertex->num_elements;
420 }
421
422 #define NV50_PRIM_GL_CASE(n) \
423 case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
424
425 static inline unsigned
426 nv50_prim_gl(unsigned prim)
427 {
428 switch (prim) {
429 NV50_PRIM_GL_CASE(POINTS);
430 NV50_PRIM_GL_CASE(LINES);
431 NV50_PRIM_GL_CASE(LINE_LOOP);
432 NV50_PRIM_GL_CASE(LINE_STRIP);
433 NV50_PRIM_GL_CASE(TRIANGLES);
434 NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
435 NV50_PRIM_GL_CASE(TRIANGLE_FAN);
436 NV50_PRIM_GL_CASE(QUADS);
437 NV50_PRIM_GL_CASE(QUAD_STRIP);
438 NV50_PRIM_GL_CASE(POLYGON);
439 NV50_PRIM_GL_CASE(LINES_ADJACENCY);
440 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
441 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
442 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
443 default:
444 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
445 break;
446 }
447 }
448
449 /* For pre-nva0 transform feedback. */
450 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
451 {
452 [PIPE_PRIM_POINTS] = 1,
453 [PIPE_PRIM_LINES] = 2,
454 [PIPE_PRIM_LINE_LOOP] = 2,
455 [PIPE_PRIM_LINE_STRIP] = 2,
456 [PIPE_PRIM_TRIANGLES] = 3,
457 [PIPE_PRIM_TRIANGLE_STRIP] = 3,
458 [PIPE_PRIM_TRIANGLE_FAN] = 3,
459 [PIPE_PRIM_QUADS] = 3,
460 [PIPE_PRIM_QUAD_STRIP] = 3,
461 [PIPE_PRIM_POLYGON] = 3,
462 [PIPE_PRIM_LINES_ADJACENCY] = 2,
463 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
464 [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
465 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
466 };
467
468 static void
469 nv50_draw_arrays(struct nv50_context *nv50,
470 unsigned mode, unsigned start, unsigned count,
471 unsigned instance_count)
472 {
473 struct nouveau_pushbuf *push = nv50->base.pushbuf;
474 unsigned prim;
475
476 if (nv50->state.index_bias) {
477 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
478 PUSH_DATA (push, 0);
479 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
480 BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
481 PUSH_DATA (push, 0);
482 }
483 nv50->state.index_bias = 0;
484 }
485
486 prim = nv50_prim_gl(mode);
487
488 while (instance_count--) {
489 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
490 PUSH_DATA (push, prim);
491 BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
492 PUSH_DATA (push, start);
493 PUSH_DATA (push, count);
494 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
495 PUSH_DATA (push, 0);
496
497 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
498 }
499 }
500
501 static void
502 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
503 unsigned start, unsigned count)
504 {
505 map += start;
506
507 if (count & 3) {
508 unsigned i;
509 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
510 for (i = 0; i < (count & 3); ++i)
511 PUSH_DATA(push, *map++);
512 count &= ~3;
513 }
514 while (count) {
515 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
516
517 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
518 for (i = 0; i < nr; ++i) {
519 PUSH_DATA(push,
520 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
521 map += 4;
522 }
523 count -= nr * 4;
524 }
525 }
526
527 static void
528 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
529 unsigned start, unsigned count)
530 {
531 map += start;
532
533 if (count & 1) {
534 count &= ~1;
535 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
536 PUSH_DATA (push, *map++);
537 }
538 while (count) {
539 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
540
541 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
542 for (i = 0; i < nr; ++i) {
543 PUSH_DATA(push, (map[1] << 16) | map[0]);
544 map += 2;
545 }
546 count -= nr * 2;
547 }
548 }
549
550 static void
551 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
552 unsigned start, unsigned count)
553 {
554 map += start;
555
556 while (count) {
557 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
558
559 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
560 PUSH_DATAp(push, map, nr);
561
562 map += nr;
563 count -= nr;
564 }
565 }
566
567 static void
568 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
569 const uint32_t *map,
570 unsigned start, unsigned count)
571 {
572 map += start;
573
574 if (count & 1) {
575 count--;
576 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
577 PUSH_DATA (push, *map++);
578 }
579 while (count) {
580 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
581
582 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
583 for (i = 0; i < nr; ++i) {
584 PUSH_DATA(push, (map[1] << 16) | map[0]);
585 map += 2;
586 }
587 count -= nr * 2;
588 }
589 }
590
591 static void
592 nv50_draw_elements(struct nv50_context *nv50, bool shorten,
593 unsigned mode, unsigned start, unsigned count,
594 unsigned instance_count, int32_t index_bias)
595 {
596 struct nouveau_pushbuf *push = nv50->base.pushbuf;
597 unsigned prim;
598 const unsigned index_size = nv50->idxbuf.index_size;
599
600 prim = nv50_prim_gl(mode);
601
602 if (index_bias != nv50->state.index_bias) {
603 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
604 PUSH_DATA (push, index_bias);
605 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
606 BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
607 PUSH_DATA (push, index_bias);
608 }
609 nv50->state.index_bias = index_bias;
610 }
611
612 if (nv50->idxbuf.buffer) {
613 struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
614 unsigned pb_start;
615 unsigned pb_bytes;
616 const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
617
618 start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
619
620 assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
621
622 /* This shouldn't have to be here. The going theory is that the buffer
623 * is being filled in by PGRAPH, and it's not done yet by the time it
624 * gets submitted to PFIFO, which in turn starts immediately prefetching
625 * the not-yet-written data. Ideally this wait would only happen on
626 * pushbuf submit, but it's probably not a big performance difference.
627 */
628 if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
629 nouveau_fence_wait(buf->fence_wr);
630
631 while (instance_count--) {
632 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
633 PUSH_DATA (push, prim);
634
635 PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
636 nouveau_pushbuf_space(push, 8, 0, 1);
637
638 switch (index_size) {
639 case 4:
640 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
641 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
642 break;
643 case 2:
644 pb_start = (start & ~1) * 2;
645 pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
646
647 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
648 PUSH_DATA (push, (start << 31) | count);
649 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
650 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
651 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
652 PUSH_DATA (push, 0);
653 break;
654 default:
655 assert(index_size == 1);
656 pb_start = start & ~3;
657 pb_bytes = ((start + count + 3) & ~3) - pb_start;
658
659 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
660 PUSH_DATA (push, (start << 30) | count);
661 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
662 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
663 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
664 PUSH_DATA (push, 0);
665 break;
666 }
667 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
668 PUSH_DATA (push, 0);
669
670 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
671 }
672 } else {
673 const void *data = nv50->idxbuf.user_buffer;
674
675 while (instance_count--) {
676 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
677 PUSH_DATA (push, prim);
678 switch (index_size) {
679 case 1:
680 nv50_draw_elements_inline_u08(push, data, start, count);
681 break;
682 case 2:
683 nv50_draw_elements_inline_u16(push, data, start, count);
684 break;
685 case 4:
686 if (shorten)
687 nv50_draw_elements_inline_u32_short(push, data, start, count);
688 else
689 nv50_draw_elements_inline_u32(push, data, start, count);
690 break;
691 default:
692 assert(0);
693 return;
694 }
695 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
696 PUSH_DATA (push, 0);
697
698 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
699 }
700 }
701 }
702
703 static void
704 nva0_draw_stream_output(struct nv50_context *nv50,
705 const struct pipe_draw_info *info)
706 {
707 struct nouveau_pushbuf *push = nv50->base.pushbuf;
708 struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
709 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
710 unsigned num_instances = info->instance_count;
711 unsigned mode = nv50_prim_gl(info->mode);
712
713 if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
714 /* A proper implementation without waiting doesn't seem possible,
715 * so don't bother.
716 */
717 NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
718 return;
719 }
720
721 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
722 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
723 PUSH_SPACE(push, 4);
724 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
725 PUSH_DATA (push, 0);
726 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
727 PUSH_DATA (push, 0);
728 }
729
730 assert(num_instances);
731 do {
732 PUSH_SPACE(push, 8);
733 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
734 PUSH_DATA (push, mode);
735 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
736 PUSH_DATA (push, 0);
737 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
738 PUSH_DATA (push, so->stride);
739 nv50_query_pushbuf_submit(push, NVA0_3D_DRAW_TFB_BYTES, so->pq, 0x4);
740 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
741 PUSH_DATA (push, 0);
742
743 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
744 } while (--num_instances);
745 }
746
747 static void
748 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
749 {
750 struct nv50_screen *screen = chan->user_priv;
751
752 nouveau_fence_update(&screen->base, true);
753
754 nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true);
755 }
756
757 void
758 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
759 {
760 struct nv50_context *nv50 = nv50_context(pipe);
761 struct nouveau_pushbuf *push = nv50->base.pushbuf;
762 int i, s;
763
764 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
765 nv50->vb_elt_first = info->min_index + info->index_bias;
766 nv50->vb_elt_limit = info->max_index - info->min_index;
767 nv50->instance_off = info->start_instance;
768 nv50->instance_max = info->instance_count - 1;
769
770 /* For picking only a few vertices from a large user buffer, push is better,
771 * if index count is larger and we expect repeated vertices, suggest upload.
772 */
773 nv50->vbo_push_hint = /* the 64 is heuristic */
774 !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
775
776 if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) {
777 if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
778 nv50->dirty |= NV50_NEW_ARRAYS;
779 else
780 if (!nv50->vbo_fifo)
781 nv50_update_user_vbufs(nv50);
782 }
783
784 if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
785 nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
786
787 nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
788
789 push->kick_notify = nv50_draw_vbo_kick_notify;
790
791 for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
792 uint32_t valid = nv50->constbuf_valid[s];
793
794 while (valid && !nv50->cb_dirty) {
795 const unsigned i = ffs(valid) - 1;
796 struct pipe_resource *res;
797
798 valid &= ~(1 << i);
799 if (nv50->constbuf[s][i].user)
800 continue;
801
802 res = nv50->constbuf[s][i].u.buf;
803 if (!res)
804 continue;
805
806 if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
807 nv50->cb_dirty = true;
808 }
809 }
810
811 /* If there are any coherent constbufs, flush the cache */
812 if (nv50->cb_dirty) {
813 BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
814 PUSH_DATA (push, 0);
815 nv50->cb_dirty = false;
816 }
817
818 if (nv50->vbo_fifo) {
819 nv50_push_vbo(nv50, info);
820 push->kick_notify = nv50_default_kick_notify;
821 nouveau_pushbuf_bufctx(push, NULL);
822 return;
823 }
824
825 if (nv50->state.instance_base != info->start_instance) {
826 nv50->state.instance_base = info->start_instance;
827 /* NOTE: this does not affect the shader input, should it ? */
828 BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
829 PUSH_DATA (push, info->start_instance);
830 }
831
832 for (i = 0; i < nv50->num_vtxbufs && !nv50->base.vbo_dirty; ++i) {
833 if (!nv50->vtxbuf[i].buffer)
834 continue;
835 if (nv50->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
836 nv50->base.vbo_dirty = true;
837 }
838
839 if (nv50->base.vbo_dirty) {
840 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
841 PUSH_DATA (push, 0);
842 nv50->base.vbo_dirty = false;
843 }
844
845 if (info->indexed) {
846 bool shorten = info->max_index <= 65535;
847
848 if (info->primitive_restart != nv50->state.prim_restart) {
849 if (info->primitive_restart) {
850 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
851 PUSH_DATA (push, 1);
852 PUSH_DATA (push, info->restart_index);
853
854 if (info->restart_index > 65535)
855 shorten = false;
856 } else {
857 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
858 PUSH_DATA (push, 0);
859 }
860 nv50->state.prim_restart = info->primitive_restart;
861 } else
862 if (info->primitive_restart) {
863 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
864 PUSH_DATA (push, info->restart_index);
865
866 if (info->restart_index > 65535)
867 shorten = false;
868 }
869
870 nv50_draw_elements(nv50, shorten,
871 info->mode, info->start, info->count,
872 info->instance_count, info->index_bias);
873 } else
874 if (unlikely(info->count_from_stream_output)) {
875 nva0_draw_stream_output(nv50, info);
876 } else {
877 nv50_draw_arrays(nv50,
878 info->mode, info->start, info->count,
879 info->instance_count);
880 }
881 push->kick_notify = nv50_default_kick_notify;
882
883 nv50_release_user_vbufs(nv50);
884
885 nouveau_pushbuf_bufctx(push, NULL);
886 }