src/gallium/drivers/nouveau/nv50/nv50_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nv50/nv50_context.h"
  30 #include "nv50/nv50_query_hw.h"
  31 #include "nv50/nv50_resource.h"
  32
  33 #include "nv50/nv50_3d.xml.h"
  34
  35 void
  36 nv50_vertex_state_delete(struct pipe_context *pipe,
  37                          void *hwcso)
  38 {
  39    struct nv50_vertex_stateobj *so = hwcso;
  40
  41    if (so->translate)
  42       so->translate->release(so->translate);
  43    FREE(hwcso);
  44 }
  45
  46 void *
  47 nv50_vertex_state_create(struct pipe_context *pipe,
  48                          unsigned num_elements,
  49                          const struct pipe_vertex_element *elements)
  50 {
  51     struct nv50_vertex_stateobj *so;
  52     struct translate_key transkey;
  53     unsigned i;
  54
  55     so = MALLOC(sizeof(*so) +
  56                 num_elements * sizeof(struct nv50_vertex_element));
  57     if (!so)
  58         return NULL;
  59     so->num_elements = num_elements;
  60     so->instance_elts = 0;
  61     so->instance_bufs = 0;
  62     so->need_conversion = false;
  63
  64     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  65
  66     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  67        so->min_instance_div[i] = 0xffffffff;
  68
  69     transkey.nr_elements = 0;
  70     transkey.output_stride = 0;
  71
  72     for (i = 0; i < num_elements; ++i) {
  73         const struct pipe_vertex_element *ve = &elements[i];
  74         const unsigned vbi = ve->vertex_buffer_index;
  75         unsigned size;
  76         enum pipe_format fmt = ve->src_format;
  77
  78         so->element[i].pipe = elements[i];
  79         so->element[i].state = nv50_vertex_format[fmt].vtx;
  80
  81         if (!so->element[i].state) {
  82             switch (util_format_get_nr_components(fmt)) {
  83             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  84             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  85             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  86             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  87             default:
  88                 assert(0);
  89                 FREE(so);
  90                 return NULL;
  91             }
  92             so->element[i].state = nv50_vertex_format[fmt].vtx;
  93             so->need_conversion = true;
  94             pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
  95                                "Converting vertex element %d, no hw format %s",
  96                                i, util_format_name(ve->src_format));
  97         }
  98         so->element[i].state |= i;
  99
 100         size = util_format_get_blocksize(fmt);
 101         if (so->vb_access_size[vbi] < (ve->src_offset + size))
 102            so->vb_access_size[vbi] = ve->src_offset + size;
 103
 104         if (1) {
 105             unsigned j = transkey.nr_elements++;
 106
 107             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
 108             transkey.element[j].input_format = ve->src_format;
 109             transkey.element[j].input_buffer = vbi;
 110             transkey.element[j].input_offset = ve->src_offset;
 111             transkey.element[j].instance_divisor = ve->instance_divisor;
 112
 113             transkey.element[j].output_format = fmt;
 114             transkey.element[j].output_offset = transkey.output_stride;
 115             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 116
 117             if (unlikely(ve->instance_divisor)) {
 118                so->instance_elts |= 1 << i;
 119                so->instance_bufs |= 1 << vbi;
 120                if (ve->instance_divisor < so->min_instance_div[vbi])
 121                   so->min_instance_div[vbi] = ve->instance_divisor;
 122             }
 123         }
 124     }
 125
 126     so->translate = translate_create(&transkey);
 127     so->vertex_size = transkey.output_stride / 4;
 128     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
 129        MAX2(so->vertex_size, 1);
 130
 131     return so;
 132 }
 133
 134 #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
 135    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
 136    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
 137    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
 138
 139 static void
 140 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
 141                   struct pipe_vertex_element *ve, unsigned attr)
 142 {
 143    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 144    const void *data = (const uint8_t *)vb->buffer.user + ve->src_offset;
 145    float v[4];
 146    const unsigned nc = util_format_get_nr_components(ve->src_format);
 147    const struct util_format_description *desc =
 148       util_format_description(ve->src_format);
 149
 150    assert(vb->is_user_buffer);
 151
 152    if (desc->channel[0].pure_integer) {
 153       if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
 154          desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
 155       } else {
 156          desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
 157       }
 158    } else {
 159       desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
 160    }
 161
 162    switch (nc) {
 163    case 4:
 164       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
 165       PUSH_DATAf(push, v[0]);
 166       PUSH_DATAf(push, v[1]);
 167       PUSH_DATAf(push, v[2]);
 168       PUSH_DATAf(push, v[3]);
 169       break;
 170    case 3:
 171       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
 172       PUSH_DATAf(push, v[0]);
 173       PUSH_DATAf(push, v[1]);
 174       PUSH_DATAf(push, v[2]);
 175       break;
 176    case 2:
 177       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
 178       PUSH_DATAf(push, v[0]);
 179       PUSH_DATAf(push, v[1]);
 180       break;
 181    case 1:
 182       if (attr == nv50->vertprog->vp.edgeflag) {
 183          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 184          PUSH_DATA (push, v[0] ? 1 : 0);
 185       }
 186       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
 187       PUSH_DATAf(push, v[0]);
 188       break;
 189    default:
 190       assert(0);
 191       break;
 192    }
 193 }
 194
 195 static inline void
 196 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
 197                      uint32_t *base, uint32_t *size)
 198 {
 199    assert(vbi < PIPE_MAX_ATTRIBS);
 200    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
 201       /* TODO: use min and max instance divisor to get a proper range */
 202       *base = 0;
 203       *size = nv50->vtxbuf[vbi].buffer.resource->width0;
 204    } else {
 205       /* NOTE: if there are user buffers, we *must* have index bounds */
 206       assert(nv50->vb_elt_limit != ~0);
 207       *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
 208       *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
 209          nv50->vertex->vb_access_size[vbi];
 210    }
 211 }
 212
 213 static void
 214 nv50_upload_user_buffers(struct nv50_context *nv50,
 215                          uint64_t addrs[], uint32_t limits[])
 216 {
 217    unsigned b;
 218
 219    assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
 220    for (b = 0; b < nv50->num_vtxbufs; ++b) {
 221       struct nouveau_bo *bo;
 222       const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 223       uint32_t base, size;
 224
 225       if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
 226          continue;
 227       nv50_user_vbuf_range(nv50, b, &base, &size);
 228
 229       limits[b] = base + size - 1;
 230       addrs[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user, base, size,
 231                                       &bo);
 232       if (addrs[b])
 233          BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, NOUVEAU_BO_GART |
 234                       NOUVEAU_BO_RD, bo);
 235    }
 236    nv50->base.vbo_dirty = true;
 237 }
 238
 239 static void
 240 nv50_update_user_vbufs(struct nv50_context *nv50)
 241 {
 242    uint64_t address[PIPE_MAX_ATTRIBS];
 243    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 244    unsigned i;
 245    uint32_t written = 0;
 246
 247    for (i = 0; i < nv50->vertex->num_elements; ++i) {
 248       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
 249       const unsigned b = ve->vertex_buffer_index;
 250       struct pipe_vertex_buffer *vb;
 251       uint32_t base, size;
 252
 253       assert(b < PIPE_MAX_ATTRIBS);
 254       vb = &nv50->vtxbuf[b];
 255
 256       if (!(nv50->vbo_user & (1 << b)))
 257          continue;
 258
 259       if (!vb->stride) {
 260          nv50_emit_vtxattr(nv50, vb, ve, i);
 261          continue;
 262       }
 263       nv50_user_vbuf_range(nv50, b, &base, &size);
 264
 265       if (!(written & (1 << b))) {
 266          struct nouveau_bo *bo;
 267          const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 268          written |= 1 << b;
 269          address[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user,
 270                                            base, size, &bo);
 271          if (address[b])
 272             BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, bo_flags, bo);
 273       }
 274
 275       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 276       PUSH_DATAh(push, address[b] + base + size - 1);
 277       PUSH_DATA (push, address[b] + base + size - 1);
 278       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 279       PUSH_DATAh(push, address[b] + ve->src_offset);
 280       PUSH_DATA (push, address[b] + ve->src_offset);
 281    }
 282    nv50->base.vbo_dirty = true;
 283 }
 284
 285 static inline void
 286 nv50_release_user_vbufs(struct nv50_context *nv50)
 287 {
 288    if (nv50->vbo_user) {
 289       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX_TMP);
 290       nouveau_scratch_done(&nv50->base);
 291    }
 292 }
 293
 294 void
 295 nv50_vertex_arrays_validate(struct nv50_context *nv50)
 296 {
 297    uint64_t addrs[PIPE_MAX_ATTRIBS];
 298    uint32_t limits[PIPE_MAX_ATTRIBS];
 299    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 300    struct nv50_vertex_stateobj *vertex = nv50->vertex;
 301    struct pipe_vertex_buffer *vb;
 302    struct nv50_vertex_element *ve;
 303    uint32_t mask;
 304    uint32_t refd = 0;
 305    unsigned i;
 306    const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
 307
 308    if (unlikely(vertex->need_conversion))
 309       nv50->vbo_fifo = ~0;
 310    else
 311    if (nv50->vbo_user & ~nv50->vbo_constant)
 312       nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
 313    else
 314       nv50->vbo_fifo = 0;
 315
 316    if (!nv50->vbo_fifo) {
 317       /* if vertex buffer was written by GPU - flush VBO cache */
 318       assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
 319       for (i = 0; i < nv50->num_vtxbufs; ++i) {
 320          struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer.resource);
 321          if (!nv50->vtxbuf[i].is_user_buffer &&
 322              buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 323             buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 324             nv50->base.vbo_dirty = true;
 325          }
 326       }
 327    }
 328
 329    /* update vertex format state */
 330    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
 331    if (nv50->vbo_fifo) {
 332       nv50->state.num_vtxelts = vertex->num_elements;
 333       for (i = 0; i < vertex->num_elements; ++i)
 334          PUSH_DATA (push, vertex->element[i].state);
 335       for (; i < n; ++i)
 336          PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 337       for (i = 0; i < n; ++i) {
 338          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 339          PUSH_DATA (push, 0);
 340       }
 341       return;
 342    }
 343    for (i = 0; i < vertex->num_elements; ++i) {
 344       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 345
 346       assert(b < PIPE_MAX_ATTRIBS);
 347       ve = &vertex->element[i];
 348       vb = &nv50->vtxbuf[b];
 349
 350       if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
 351          PUSH_DATA(push, ve->state);
 352       else
 353          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
 354    }
 355    for (; i < n; ++i)
 356       PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 357
 358    /* update per-instance enables */
 359    mask = vertex->instance_elts ^ nv50->state.instance_elts;
 360    while (mask) {
 361       const int i = ffs(mask) - 1;
 362       mask &= ~(1 << i);
 363       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 364       PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
 365    }
 366    nv50->state.instance_elts = vertex->instance_elts;
 367
 368    if (nv50->vbo_user & ~nv50->vbo_constant)
 369       nv50_upload_user_buffers(nv50, addrs, limits);
 370
 371    /* update buffers and set constant attributes */
 372    for (i = 0; i < vertex->num_elements; ++i) {
 373       uint64_t address, limit;
 374       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 375
 376       assert(b < PIPE_MAX_ATTRIBS);
 377       ve = &vertex->element[i];
 378       vb = &nv50->vtxbuf[b];
 379
 380       if (unlikely(nv50->vbo_constant & (1 << b))) {
 381          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 382          PUSH_DATA (push, 0);
 383          nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
 384          continue;
 385       } else
 386       if (nv50->vbo_user & (1 << b)) {
 387          address = addrs[b] + ve->pipe.src_offset;
 388          limit = addrs[b] + limits[b];
 389       } else
 390       if (!vb->buffer.resource) {
 391          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 392          PUSH_DATA (push, 0);
 393          continue;
 394       } else {
 395          struct nv04_resource *buf = nv04_resource(vb->buffer.resource);
 396          if (!(refd & (1 << b))) {
 397             refd |= 1 << b;
 398             BCTX_REFN(nv50->bufctx_3d, 3D_VERTEX, buf, RD);
 399          }
 400          address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
 401          limit = buf->address + buf->base.width0 - 1;
 402       }
 403
 404       if (unlikely(ve->pipe.instance_divisor)) {
 405          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
 406          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 407          PUSH_DATAh(push, address);
 408          PUSH_DATA (push, address);
 409          PUSH_DATA (push, ve->pipe.instance_divisor);
 410       } else {
 411          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
 412          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 413          PUSH_DATAh(push, address);
 414          PUSH_DATA (push, address);
 415       }
 416       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 417       PUSH_DATAh(push, limit);
 418       PUSH_DATA (push, limit);
 419    }
 420    for (; i < nv50->state.num_vtxelts; ++i) {
 421       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 422       PUSH_DATA (push, 0);
 423    }
 424    nv50->state.num_vtxelts = vertex->num_elements;
 425 }
 426
 427 #define NV50_PRIM_GL_CASE(n) \
 428    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 429
 430 static inline unsigned
 431 nv50_prim_gl(unsigned prim)
 432 {
 433    switch (prim) {
 434    NV50_PRIM_GL_CASE(POINTS);
 435    NV50_PRIM_GL_CASE(LINES);
 436    NV50_PRIM_GL_CASE(LINE_LOOP);
 437    NV50_PRIM_GL_CASE(LINE_STRIP);
 438    NV50_PRIM_GL_CASE(TRIANGLES);
 439    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
 440    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
 441    NV50_PRIM_GL_CASE(QUADS);
 442    NV50_PRIM_GL_CASE(QUAD_STRIP);
 443    NV50_PRIM_GL_CASE(POLYGON);
 444    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
 445    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 446    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 447    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 448    default:
 449       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 450       break;
 451    }
 452 }
 453
 454 /* For pre-nva0 transform feedback. */
 455 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
 456 {
 457    [PIPE_PRIM_POINTS] = 1,
 458    [PIPE_PRIM_LINES] = 2,
 459    [PIPE_PRIM_LINE_LOOP] = 2,
 460    [PIPE_PRIM_LINE_STRIP] = 2,
 461    [PIPE_PRIM_TRIANGLES] = 3,
 462    [PIPE_PRIM_TRIANGLE_STRIP] = 3,
 463    [PIPE_PRIM_TRIANGLE_FAN] = 3,
 464    [PIPE_PRIM_QUADS] = 3,
 465    [PIPE_PRIM_QUAD_STRIP] = 3,
 466    [PIPE_PRIM_POLYGON] = 3,
 467    [PIPE_PRIM_LINES_ADJACENCY] = 2,
 468    [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
 469    [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
 470    [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
 471 };
 472
 473 static void
 474 nv50_draw_arrays(struct nv50_context *nv50,
 475                  unsigned mode, unsigned start, unsigned count,
 476                  unsigned instance_count)
 477 {
 478    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 479    unsigned prim;
 480
 481    if (nv50->state.index_bias) {
 482       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 483       PUSH_DATA (push, 0);
 484       if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
 485          BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 486          PUSH_DATA (push, 0);
 487       }
 488       nv50->state.index_bias = 0;
 489    }
 490
 491    prim = nv50_prim_gl(mode);
 492
 493    while (instance_count--) {
 494       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 495       PUSH_DATA (push, prim);
 496       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
 497       PUSH_DATA (push, start);
 498       PUSH_DATA (push, count);
 499       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 500       PUSH_DATA (push, 0);
 501
 502       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 503    }
 504 }
 505
 506 static void
 507 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
 508                               unsigned start, unsigned count)
 509 {
 510    map += start;
 511
 512    if (count & 3) {
 513       unsigned i;
 514       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
 515       for (i = 0; i < (count & 3); ++i)
 516          PUSH_DATA(push, *map++);
 517       count &= ~3;
 518    }
 519    while (count) {
 520       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 521
 522       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
 523       for (i = 0; i < nr; ++i) {
 524          PUSH_DATA(push,
 525                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 526          map += 4;
 527       }
 528       count -= nr * 4;
 529    }
 530 }
 531
 532 static void
 533 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
 534                               unsigned start, unsigned count)
 535 {
 536    map += start;
 537
 538    if (count & 1) {
 539       count &= ~1;
 540       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 541       PUSH_DATA (push, *map++);
 542    }
 543    while (count) {
 544       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 545
 546       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 547       for (i = 0; i < nr; ++i) {
 548          PUSH_DATA(push, (map[1] << 16) | map[0]);
 549          map += 2;
 550       }
 551       count -= nr * 2;
 552    }
 553 }
 554
 555 static void
 556 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
 557                               unsigned start, unsigned count)
 558 {
 559    map += start;
 560
 561    while (count) {
 562       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 563
 564       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
 565       PUSH_DATAp(push, map, nr);
 566
 567       map += nr;
 568       count -= nr;
 569    }
 570 }
 571
 572 static void
 573 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 574                                     const uint32_t *map,
 575                                     unsigned start, unsigned count)
 576 {
 577    map += start;
 578
 579    if (count & 1) {
 580       count--;
 581       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 582       PUSH_DATA (push, *map++);
 583    }
 584    while (count) {
 585       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 586
 587       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 588       for (i = 0; i < nr; ++i) {
 589          PUSH_DATA(push, (map[1] << 16) | map[0]);
 590          map += 2;
 591       }
 592       count -= nr * 2;
 593    }
 594 }
 595
 596 static void
 597 nv50_draw_elements(struct nv50_context *nv50, bool shorten,
 598                    unsigned mode, unsigned start, unsigned count,
 599                    unsigned instance_count, int32_t index_bias)
 600 {
 601    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 602    unsigned prim;
 603    const unsigned index_size = nv50->idxbuf.index_size;
 604
 605    prim = nv50_prim_gl(mode);
 606
 607    if (index_bias != nv50->state.index_bias) {
 608       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 609       PUSH_DATA (push, index_bias);
 610       if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
 611          BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 612          PUSH_DATA (push, index_bias);
 613       }
 614       nv50->state.index_bias = index_bias;
 615    }
 616
 617    if (nv50->idxbuf.buffer) {
 618       struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
 619       unsigned pb_start;
 620       unsigned pb_bytes;
 621       const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
 622
 623       start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
 624
 625       assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
 626
 627       /* This shouldn't have to be here. The going theory is that the buffer
 628        * is being filled in by PGRAPH, and it's not done yet by the time it
 629        * gets submitted to PFIFO, which in turn starts immediately prefetching
 630        * the not-yet-written data. Ideally this wait would only happen on
 631        * pushbuf submit, but it's probably not a big performance difference.
 632        */
 633       if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
 634          nouveau_fence_wait(buf->fence_wr, &nv50->base.debug);
 635
 636       while (instance_count--) {
 637          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 638          PUSH_DATA (push, prim);
 639
 640          nouveau_pushbuf_space(push, 16, 0, 1);
 641          PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
 642
 643          switch (index_size) {
 644          case 4:
 645             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
 646             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
 647             break;
 648          case 2:
 649             pb_start = (start & ~1) * 2;
 650             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
 651
 652             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 653             PUSH_DATA (push, (start << 31) | count);
 654             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
 655             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 656             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 657             PUSH_DATA (push, 0);
 658             break;
 659          default:
 660             assert(index_size == 1);
 661             pb_start = start & ~3;
 662             pb_bytes = ((start + count + 3) & ~3) - pb_start;
 663
 664             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 665             PUSH_DATA (push, (start << 30) | count);
 666             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
 667             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 668             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 669             PUSH_DATA (push, 0);
 670             break;
 671          }
 672          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 673          PUSH_DATA (push, 0);
 674
 675          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 676       }
 677    } else {
 678       const void *data = nv50->idxbuf.user_buffer;
 679
 680       while (instance_count--) {
 681          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 682          PUSH_DATA (push, prim);
 683          switch (index_size) {
 684          case 1:
 685             nv50_draw_elements_inline_u08(push, data, start, count);
 686             break;
 687          case 2:
 688             nv50_draw_elements_inline_u16(push, data, start, count);
 689             break;
 690          case 4:
 691             if (shorten)
 692                nv50_draw_elements_inline_u32_short(push, data, start, count);
 693             else
 694                nv50_draw_elements_inline_u32(push, data, start, count);
 695             break;
 696          default:
 697             assert(0);
 698             return;
 699          }
 700          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 701          PUSH_DATA (push, 0);
 702
 703          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 704       }
 705    }
 706    NOUVEAU_DRV_STAT(&nv50->screen->base, draw_calls_indexed, 1);
 707 }
 708
 709 static void
 710 nva0_draw_stream_output(struct nv50_context *nv50,
 711                         const struct pipe_draw_info *info)
 712 {
 713    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 714    struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
 715    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
 716    unsigned num_instances = info->instance_count;
 717    unsigned mode = nv50_prim_gl(info->mode);
 718
 719    if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
 720       /* A proper implementation without waiting doesn't seem possible,
 721        * so don't bother.
 722        */
 723       NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
 724       return;
 725    }
 726
 727    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 728       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 729       PUSH_SPACE(push, 4);
 730       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 731       PUSH_DATA (push, 0);
 732       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 733       PUSH_DATA (push, 0);
 734    }
 735
 736    assert(num_instances);
 737    do {
 738       PUSH_SPACE(push, 8);
 739       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 740       PUSH_DATA (push, mode);
 741       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
 742       PUSH_DATA (push, 0);
 743       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
 744       PUSH_DATA (push, so->stride);
 745       nv50_hw_query_pushbuf_submit(push, NVA0_3D_DRAW_TFB_BYTES,
 746                                    nv50_query(so->pq), 0x4);
 747       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 748       PUSH_DATA (push, 0);
 749
 750       mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 751    } while (--num_instances);
 752 }
 753
 754 static void
 755 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
 756 {
 757    struct nv50_screen *screen = chan->user_priv;
 758
 759    nouveau_fence_update(&screen->base, true);
 760
 761    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true);
 762 }
 763
 764 void
 765 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 766 {
 767    struct nv50_context *nv50 = nv50_context(pipe);
 768    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 769    bool tex_dirty = false;
 770    int s;
 771
 772    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
 773    nv50->vb_elt_first = info->min_index + info->index_bias;
 774    nv50->vb_elt_limit = info->max_index - info->min_index;
 775    nv50->instance_off = info->start_instance;
 776    nv50->instance_max = info->instance_count - 1;
 777
 778    /* For picking only a few vertices from a large user buffer, push is better,
 779     * if index count is larger and we expect repeated vertices, suggest upload.
 780     */
 781    nv50->vbo_push_hint = /* the 64 is heuristic */
 782       !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
 783
 784    if (nv50->vbo_user && !(nv50->dirty_3d & (NV50_NEW_3D_ARRAYS | NV50_NEW_3D_VERTEX))) {
 785       if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
 786          nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
 787       else
 788       if (!nv50->vbo_fifo)
 789          nv50_update_user_vbufs(nv50);
 790    }
 791
 792    if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
 793       nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
 794
 795    nv50_state_validate_3d(nv50, ~0);
 796
 797    push->kick_notify = nv50_draw_vbo_kick_notify;
 798
 799    for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
 800       if (nv50->constbuf_coherent[s])
 801          nv50->cb_dirty = true;
 802    }
 803
 804    /* If there are any coherent constbufs, flush the cache */
 805    if (nv50->cb_dirty) {
 806       BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
 807       PUSH_DATA (push, 0);
 808       nv50->cb_dirty = false;
 809    }
 810
 811    for (s = 0; s < 3 && !tex_dirty; ++s) {
 812       if (nv50->textures_coherent[s])
 813          tex_dirty = true;
 814    }
 815
 816    if (tex_dirty) {
 817       BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
 818       PUSH_DATA (push, 0x20);
 819    }
 820
 821    if (nv50->screen->base.class_3d >= NVA0_3D_CLASS &&
 822        nv50->seamless_cube_map != nv50->state.seamless_cube_map) {
 823       nv50->state.seamless_cube_map = nv50->seamless_cube_map;
 824       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 825       PUSH_DATA (push, nv50->seamless_cube_map ? NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
 826    }
 827
 828    if (nv50->vertprog->mul_zero_wins != nv50->state.mul_zero_wins) {
 829       nv50->state.mul_zero_wins = nv50->vertprog->mul_zero_wins;
 830       BEGIN_NV04(push, NV50_3D(UNK1690), 1);
 831       PUSH_DATA (push, 0x00010000 * !!nv50->state.mul_zero_wins);
 832    }
 833
 834    if (nv50->vbo_fifo) {
 835       nv50_push_vbo(nv50, info);
 836       push->kick_notify = nv50_default_kick_notify;
 837       nouveau_pushbuf_bufctx(push, NULL);
 838       return;
 839    }
 840
 841    if (nv50->state.instance_base != info->start_instance) {
 842       nv50->state.instance_base = info->start_instance;
 843       /* NOTE: this does not affect the shader input, should it ? */
 844       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
 845       PUSH_DATA (push, info->start_instance);
 846    }
 847
 848    nv50->base.vbo_dirty |= !!nv50->vtxbufs_coherent;
 849
 850    if (nv50->base.vbo_dirty) {
 851       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 852       PUSH_DATA (push, 0);
 853       nv50->base.vbo_dirty = false;
 854    }
 855
 856    if (info->indexed) {
 857       bool shorten = info->max_index <= 65535;
 858
 859       if (info->primitive_restart != nv50->state.prim_restart) {
 860          if (info->primitive_restart) {
 861             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
 862             PUSH_DATA (push, 1);
 863             PUSH_DATA (push, info->restart_index);
 864
 865             if (info->restart_index > 65535)
 866                shorten = false;
 867          } else {
 868             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
 869             PUSH_DATA (push, 0);
 870          }
 871          nv50->state.prim_restart = info->primitive_restart;
 872       } else
 873       if (info->primitive_restart) {
 874          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
 875          PUSH_DATA (push, info->restart_index);
 876
 877          if (info->restart_index > 65535)
 878             shorten = false;
 879       }
 880
 881       nv50_draw_elements(nv50, shorten,
 882                          info->mode, info->start, info->count,
 883                          info->instance_count, info->index_bias);
 884    } else
 885    if (unlikely(info->count_from_stream_output)) {
 886       nva0_draw_stream_output(nv50, info);
 887    } else {
 888       nv50_draw_arrays(nv50,
 889                        info->mode, info->start, info->count,
 890                        info->instance_count);
 891    }
 892    push->kick_notify = nv50_default_kick_notify;
 893
 894    nv50_release_user_vbufs(nv50);
 895
 896    nouveau_pushbuf_bufctx(push, NULL);
 897 }