projects / mesa.git / blob
? search:


9fa6fceeefa4271e2b9c76657ac796b46f15426a
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nv50/nv50_context.h"
30 #include "nv50/nv50_query_hw.h"
31 #include "nv50/nv50_resource.h"
32
33 #include "nv50/nv50_3d.xml.h"
34
35 void
36 nv50_vertex_state_delete(struct pipe_context *pipe,
37 void *hwcso)
38 {
39 struct nv50_vertex_stateobj *so = hwcso;
40
41 if (so->translate)
42 so->translate->release(so->translate);
43 FREE(hwcso);
44 }
45
46 void *
47 nv50_vertex_state_create(struct pipe_context *pipe,
48 unsigned num_elements,
49 const struct pipe_vertex_element *elements)
50 {
51 struct nv50_vertex_stateobj *so;
52 struct translate_key transkey;
53 unsigned i;
54
55 so = MALLOC(sizeof(*so) +
56 num_elements * sizeof(struct nv50_vertex_element));
57 if (!so)
58 return NULL;
59 so->num_elements = num_elements;
60 so->instance_elts = 0;
61 so->instance_bufs = 0;
62 so->need_conversion = false;
63
64 memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
65
66 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
67 so->min_instance_div[i] = 0xffffffff;
68
69 transkey.nr_elements = 0;
70 transkey.output_stride = 0;
71
72 for (i = 0; i < num_elements; ++i) {
73 const struct pipe_vertex_element *ve = &elements[i];
74 const unsigned vbi = ve->vertex_buffer_index;
75 unsigned size;
76 enum pipe_format fmt = ve->src_format;
77
78 so->element[i].pipe = elements[i];
79 so->element[i].state = nv50_format_table[fmt].vtx;
80
81 if (!so->element[i].state) {
82 switch (util_format_get_nr_components(fmt)) {
83 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
84 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
85 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
86 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
87 default:
88 assert(0);
89 FREE(so);
90 return NULL;
91 }
92 so->element[i].state = nv50_format_table[fmt].vtx;
93 so->need_conversion = true;
94 }
95 so->element[i].state |= i;
96
97 size = util_format_get_blocksize(fmt);
98 if (so->vb_access_size[vbi] < (ve->src_offset + size))
99 so->vb_access_size[vbi] = ve->src_offset + size;
100
101 if (1) {
102 unsigned j = transkey.nr_elements++;
103
104 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
105 transkey.element[j].input_format = ve->src_format;
106 transkey.element[j].input_buffer = vbi;
107 transkey.element[j].input_offset = ve->src_offset;
108 transkey.element[j].instance_divisor = ve->instance_divisor;
109
110 transkey.element[j].output_format = fmt;
111 transkey.element[j].output_offset = transkey.output_stride;
112 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
113
114 if (unlikely(ve->instance_divisor)) {
115 so->instance_elts |= 1 << i;
116 so->instance_bufs |= 1 << vbi;
117 if (ve->instance_divisor < so->min_instance_div[vbi])
118 so->min_instance_div[vbi] = ve->instance_divisor;
119 }
120 }
121 }
122
123 so->translate = translate_create(&transkey);
124 so->vertex_size = transkey.output_stride / 4;
125 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
126 MAX2(so->vertex_size, 1);
127
128 return so;
129 }
130
131 #define NV50_3D_VERTEX_ATTRIB_INACTIVE \
132 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \
133 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
134 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
135
136 static void
137 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
138 struct pipe_vertex_element *ve, unsigned attr)
139 {
140 struct nouveau_pushbuf *push = nv50->base.pushbuf;
141 const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
142 float v[4];
143 const unsigned nc = util_format_get_nr_components(ve->src_format);
144 const struct util_format_description *desc =
145 util_format_description(ve->src_format);
146
147 assert(vb->user_buffer);
148
149 if (desc->channel[0].pure_integer) {
150 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
151 desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
152 } else {
153 desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
154 }
155 } else {
156 desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
157 }
158
159 switch (nc) {
160 case 4:
161 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
162 PUSH_DATAf(push, v[0]);
163 PUSH_DATAf(push, v[1]);
164 PUSH_DATAf(push, v[2]);
165 PUSH_DATAf(push, v[3]);
166 break;
167 case 3:
168 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
169 PUSH_DATAf(push, v[0]);
170 PUSH_DATAf(push, v[1]);
171 PUSH_DATAf(push, v[2]);
172 break;
173 case 2:
174 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
175 PUSH_DATAf(push, v[0]);
176 PUSH_DATAf(push, v[1]);
177 break;
178 case 1:
179 if (attr == nv50->vertprog->vp.edgeflag) {
180 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
181 PUSH_DATA (push, v[0] ? 1 : 0);
182 }
183 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
184 PUSH_DATAf(push, v[0]);
185 break;
186 default:
187 assert(0);
188 break;
189 }
190 }
191
192 static inline void
193 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
194 uint32_t *base, uint32_t *size)
195 {
196 assert(vbi < PIPE_MAX_ATTRIBS);
197 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
198 /* TODO: use min and max instance divisor to get a proper range */
199 *base = 0;
200 *size = nv50->vtxbuf[vbi].buffer->width0;
201 } else {
202 /* NOTE: if there are user buffers, we *must* have index bounds */
203 assert(nv50->vb_elt_limit != ~0);
204 *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
205 *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
206 nv50->vertex->vb_access_size[vbi];
207 }
208 }
209
210 static void
211 nv50_upload_user_buffers(struct nv50_context *nv50,
212 uint64_t addrs[], uint32_t limits[])
213 {
214 unsigned b;
215
216 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
217 for (b = 0; b < nv50->num_vtxbufs; ++b) {
218 struct nouveau_bo *bo;
219 const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
220 uint32_t base, size;
221
222 if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
223 continue;
224 nv50_user_vbuf_range(nv50, b, &base, &size);
225
226 limits[b] = base + size - 1;
227 addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size,
228 &bo);
229 if (addrs[b])
230 BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART |
231 NOUVEAU_BO_RD, bo);
232 }
233 nv50->base.vbo_dirty = true;
234 }
235
236 static void
237 nv50_update_user_vbufs(struct nv50_context *nv50)
238 {
239 uint64_t address[PIPE_MAX_ATTRIBS];
240 struct nouveau_pushbuf *push = nv50->base.pushbuf;
241 unsigned i;
242 uint32_t written = 0;
243
244 for (i = 0; i < nv50->vertex->num_elements; ++i) {
245 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
246 const unsigned b = ve->vertex_buffer_index;
247 struct pipe_vertex_buffer *vb;
248 uint32_t base, size;
249
250 assert(b < PIPE_MAX_ATTRIBS);
251 vb = &nv50->vtxbuf[b];
252
253 if (!(nv50->vbo_user & (1 << b)))
254 continue;
255
256 if (!vb->stride) {
257 nv50_emit_vtxattr(nv50, vb, ve, i);
258 continue;
259 }
260 nv50_user_vbuf_range(nv50, b, &base, &size);
261
262 if (!(written & (1 << b))) {
263 struct nouveau_bo *bo;
264 const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
265 written |= 1 << b;
266 address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer,
267 base, size, &bo);
268 if (address[b])
269 BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo);
270 }
271
272 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
273 PUSH_DATAh(push, address[b] + base + size - 1);
274 PUSH_DATA (push, address[b] + base + size - 1);
275 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
276 PUSH_DATAh(push, address[b] + ve->src_offset);
277 PUSH_DATA (push, address[b] + ve->src_offset);
278 }
279 nv50->base.vbo_dirty = true;
280 }
281
282 static inline void
283 nv50_release_user_vbufs(struct nv50_context *nv50)
284 {
285 if (nv50->vbo_user) {
286 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP);
287 nouveau_scratch_done(&nv50->base);
288 }
289 }
290
291 void
292 nv50_vertex_arrays_validate(struct nv50_context *nv50)
293 {
294 uint64_t addrs[PIPE_MAX_ATTRIBS];
295 uint32_t limits[PIPE_MAX_ATTRIBS];
296 struct nouveau_pushbuf *push = nv50->base.pushbuf;
297 struct nv50_vertex_stateobj dummy = {};
298 struct nv50_vertex_stateobj *vertex = nv50->vertex ? nv50->vertex : &dummy;
299 struct pipe_vertex_buffer *vb;
300 struct nv50_vertex_element *ve;
301 uint32_t mask;
302 uint32_t refd = 0;
303 unsigned i;
304 const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
305
306 /* A vertexid is not generated for inline data uploads. Have to use a
307 * VBO. This check must come after the vertprog has been validated,
308 * otherwise vertexid may be unset.
309 */
310 assert(nv50->vertprog->translated);
311 if (nv50->vertprog->vp.vertexid)
312 nv50->vbo_push_hint = 0;
313
314 if (unlikely(vertex->need_conversion))
315 nv50->vbo_fifo = ~0;
316 else
317 if (nv50->vbo_user & ~nv50->vbo_constant)
318 nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
319 else
320 nv50->vbo_fifo = 0;
321
322 if (!nv50->vbo_fifo) {
323 /* if vertex buffer was written by GPU - flush VBO cache */
324 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
325 for (i = 0; i < nv50->num_vtxbufs; ++i) {
326 struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer);
327 if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
328 buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
329 nv50->base.vbo_dirty = true;
330 }
331 }
332 }
333
334 /* update vertex format state */
335 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
336 if (nv50->vbo_fifo) {
337 nv50->state.num_vtxelts = vertex->num_elements;
338 for (i = 0; i < vertex->num_elements; ++i)
339 PUSH_DATA (push, vertex->element[i].state);
340 for (; i < n; ++i)
341 PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
342 for (i = 0; i < n; ++i) {
343 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
344 PUSH_DATA (push, 0);
345 }
346 return;
347 }
348 for (i = 0; i < vertex->num_elements; ++i) {
349 const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
350
351 assert(b < PIPE_MAX_ATTRIBS);
352 ve = &vertex->element[i];
353 vb = &nv50->vtxbuf[b];
354
355 if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
356 PUSH_DATA(push, ve->state);
357 else
358 PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
359 }
360 for (; i < n; ++i)
361 PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
362
363 /* update per-instance enables */
364 mask = vertex->instance_elts ^ nv50->state.instance_elts;
365 while (mask) {
366 const int i = ffs(mask) - 1;
367 mask &= ~(1 << i);
368 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
369 PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
370 }
371 nv50->state.instance_elts = vertex->instance_elts;
372
373 if (nv50->vbo_user & ~nv50->vbo_constant)
374 nv50_upload_user_buffers(nv50, addrs, limits);
375
376 /* update buffers and set constant attributes */
377 for (i = 0; i < vertex->num_elements; ++i) {
378 uint64_t address, limit;
379 const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
380
381 assert(b < PIPE_MAX_ATTRIBS);
382 ve = &vertex->element[i];
383 vb = &nv50->vtxbuf[b];
384
385 if (unlikely(nv50->vbo_constant & (1 << b))) {
386 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
387 PUSH_DATA (push, 0);
388 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
389 continue;
390 } else
391 if (nv50->vbo_user & (1 << b)) {
392 address = addrs[b] + ve->pipe.src_offset;
393 limit = addrs[b] + limits[b];
394 } else
395 if (!vb->buffer) {
396 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
397 PUSH_DATA (push, 0);
398 continue;
399 } else {
400 struct nv04_resource *buf = nv04_resource(vb->buffer);
401 if (!(refd & (1 << b))) {
402 refd |= 1 << b;
403 BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
404 }
405 address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
406 limit = buf->address + buf->base.width0 - 1;
407 }
408
409 if (unlikely(ve->pipe.instance_divisor)) {
410 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
411 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
412 PUSH_DATAh(push, address);
413 PUSH_DATA (push, address);
414 PUSH_DATA (push, ve->pipe.instance_divisor);
415 } else {
416 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
417 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
418 PUSH_DATAh(push, address);
419 PUSH_DATA (push, address);
420 }
421 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
422 PUSH_DATAh(push, limit);
423 PUSH_DATA (push, limit);
424 }
425 for (; i < nv50->state.num_vtxelts; ++i) {
426 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
427 PUSH_DATA (push, 0);
428 }
429 nv50->state.num_vtxelts = vertex->num_elements;
430 }
431
432 #define NV50_PRIM_GL_CASE(n) \
433 case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
434
435 static inline unsigned
436 nv50_prim_gl(unsigned prim)
437 {
438 switch (prim) {
439 NV50_PRIM_GL_CASE(POINTS);
440 NV50_PRIM_GL_CASE(LINES);
441 NV50_PRIM_GL_CASE(LINE_LOOP);
442 NV50_PRIM_GL_CASE(LINE_STRIP);
443 NV50_PRIM_GL_CASE(TRIANGLES);
444 NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
445 NV50_PRIM_GL_CASE(TRIANGLE_FAN);
446 NV50_PRIM_GL_CASE(QUADS);
447 NV50_PRIM_GL_CASE(QUAD_STRIP);
448 NV50_PRIM_GL_CASE(POLYGON);
449 NV50_PRIM_GL_CASE(LINES_ADJACENCY);
450 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
451 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
452 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
453 default:
454 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
455 break;
456 }
457 }
458
459 /* For pre-nva0 transform feedback. */
460 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
461 {
462 [PIPE_PRIM_POINTS] = 1,
463 [PIPE_PRIM_LINES] = 2,
464 [PIPE_PRIM_LINE_LOOP] = 2,
465 [PIPE_PRIM_LINE_STRIP] = 2,
466 [PIPE_PRIM_TRIANGLES] = 3,
467 [PIPE_PRIM_TRIANGLE_STRIP] = 3,
468 [PIPE_PRIM_TRIANGLE_FAN] = 3,
469 [PIPE_PRIM_QUADS] = 3,
470 [PIPE_PRIM_QUAD_STRIP] = 3,
471 [PIPE_PRIM_POLYGON] = 3,
472 [PIPE_PRIM_LINES_ADJACENCY] = 2,
473 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
474 [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
475 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
476 };
477
478 static void
479 nv50_draw_arrays(struct nv50_context *nv50,
480 unsigned mode, unsigned start, unsigned count,
481 unsigned instance_count)
482 {
483 struct nouveau_pushbuf *push = nv50->base.pushbuf;
484 unsigned prim;
485
486 if (nv50->state.index_bias) {
487 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
488 PUSH_DATA (push, 0);
489 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
490 BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
491 PUSH_DATA (push, 0);
492 }
493 nv50->state.index_bias = 0;
494 }
495
496 prim = nv50_prim_gl(mode);
497
498 while (instance_count--) {
499 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
500 PUSH_DATA (push, prim);
501 BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
502 PUSH_DATA (push, start);
503 PUSH_DATA (push, count);
504 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
505 PUSH_DATA (push, 0);
506
507 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
508 }
509 }
510
511 static void
512 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
513 unsigned start, unsigned count)
514 {
515 map += start;
516
517 if (count & 3) {
518 unsigned i;
519 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
520 for (i = 0; i < (count & 3); ++i)
521 PUSH_DATA(push, *map++);
522 count &= ~3;
523 }
524 while (count) {
525 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
526
527 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
528 for (i = 0; i < nr; ++i) {
529 PUSH_DATA(push,
530 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
531 map += 4;
532 }
533 count -= nr * 4;
534 }
535 }
536
537 static void
538 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
539 unsigned start, unsigned count)
540 {
541 map += start;
542
543 if (count & 1) {
544 count &= ~1;
545 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
546 PUSH_DATA (push, *map++);
547 }
548 while (count) {
549 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
550
551 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
552 for (i = 0; i < nr; ++i) {
553 PUSH_DATA(push, (map[1] << 16) | map[0]);
554 map += 2;
555 }
556 count -= nr * 2;
557 }
558 }
559
560 static void
561 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
562 unsigned start, unsigned count)
563 {
564 map += start;
565
566 while (count) {
567 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
568
569 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
570 PUSH_DATAp(push, map, nr);
571
572 map += nr;
573 count -= nr;
574 }
575 }
576
577 static void
578 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
579 const uint32_t *map,
580 unsigned start, unsigned count)
581 {
582 map += start;
583
584 if (count & 1) {
585 count--;
586 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
587 PUSH_DATA (push, *map++);
588 }
589 while (count) {
590 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
591
592 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
593 for (i = 0; i < nr; ++i) {
594 PUSH_DATA(push, (map[1] << 16) | map[0]);
595 map += 2;
596 }
597 count -= nr * 2;
598 }
599 }
600
601 static void
602 nv50_draw_elements(struct nv50_context *nv50, bool shorten,
603 unsigned mode, unsigned start, unsigned count,
604 unsigned instance_count, int32_t index_bias)
605 {
606 struct nouveau_pushbuf *push = nv50->base.pushbuf;
607 unsigned prim;
608 const unsigned index_size = nv50->idxbuf.index_size;
609
610 prim = nv50_prim_gl(mode);
611
612 if (index_bias != nv50->state.index_bias) {
613 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
614 PUSH_DATA (push, index_bias);
615 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
616 BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
617 PUSH_DATA (push, index_bias);
618 }
619 nv50->state.index_bias = index_bias;
620 }
621
622 if (nv50->idxbuf.buffer) {
623 struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
624 unsigned pb_start;
625 unsigned pb_bytes;
626 const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
627
628 start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
629
630 assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
631
632 /* This shouldn't have to be here. The going theory is that the buffer
633 * is being filled in by PGRAPH, and it's not done yet by the time it
634 * gets submitted to PFIFO, which in turn starts immediately prefetching
635 * the not-yet-written data. Ideally this wait would only happen on
636 * pushbuf submit, but it's probably not a big performance difference.
637 */
638 if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
639 nouveau_fence_wait(buf->fence_wr);
640
641 while (instance_count--) {
642 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
643 PUSH_DATA (push, prim);
644
645 PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
646 nouveau_pushbuf_space(push, 8, 0, 1);
647
648 switch (index_size) {
649 case 4:
650 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
651 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
652 break;
653 case 2:
654 pb_start = (start & ~1) * 2;
655 pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
656
657 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
658 PUSH_DATA (push, (start << 31) | count);
659 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
660 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
661 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
662 PUSH_DATA (push, 0);
663 break;
664 default:
665 assert(index_size == 1);
666 pb_start = start & ~3;
667 pb_bytes = ((start + count + 3) & ~3) - pb_start;
668
669 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
670 PUSH_DATA (push, (start << 30) | count);
671 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
672 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
673 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
674 PUSH_DATA (push, 0);
675 break;
676 }
677 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
678 PUSH_DATA (push, 0);
679
680 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
681 }
682 } else {
683 const void *data = nv50->idxbuf.user_buffer;
684
685 while (instance_count--) {
686 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
687 PUSH_DATA (push, prim);
688 switch (index_size) {
689 case 1:
690 nv50_draw_elements_inline_u08(push, data, start, count);
691 break;
692 case 2:
693 nv50_draw_elements_inline_u16(push, data, start, count);
694 break;
695 case 4:
696 if (shorten)
697 nv50_draw_elements_inline_u32_short(push, data, start, count);
698 else
699 nv50_draw_elements_inline_u32(push, data, start, count);
700 break;
701 default:
702 assert(0);
703 return;
704 }
705 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
706 PUSH_DATA (push, 0);
707
708 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
709 }
710 }
711 }
712
713 static void
714 nva0_draw_stream_output(struct nv50_context *nv50,
715 const struct pipe_draw_info *info)
716 {
717 struct nouveau_pushbuf *push = nv50->base.pushbuf;
718 struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
719 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
720 unsigned num_instances = info->instance_count;
721 unsigned mode = nv50_prim_gl(info->mode);
722
723 if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
724 /* A proper implementation without waiting doesn't seem possible,
725 * so don't bother.
726 */
727 NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
728 return;
729 }
730
731 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
732 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
733 PUSH_SPACE(push, 4);
734 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
735 PUSH_DATA (push, 0);
736 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
737 PUSH_DATA (push, 0);
738 }
739
740 assert(num_instances);
741 do {
742 PUSH_SPACE(push, 8);
743 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
744 PUSH_DATA (push, mode);
745 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
746 PUSH_DATA (push, 0);
747 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
748 PUSH_DATA (push, so->stride);
749 nv50_hw_query_pushbuf_submit(push, NVA0_3D_DRAW_TFB_BYTES,
750 nv50_query(so->pq), 0x4);
751 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
752 PUSH_DATA (push, 0);
753
754 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
755 } while (--num_instances);
756 }
757
758 static void
759 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
760 {
761 struct nv50_screen *screen = chan->user_priv;
762
763 nouveau_fence_update(&screen->base, true);
764
765 nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true);
766 }
767
768 void
769 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
770 {
771 struct nv50_context *nv50 = nv50_context(pipe);
772 struct nouveau_pushbuf *push = nv50->base.pushbuf;
773 bool tex_dirty = false;
774 int i, s;
775
776 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
777 nv50->vb_elt_first = info->min_index + info->index_bias;
778 nv50->vb_elt_limit = info->max_index - info->min_index;
779 nv50->instance_off = info->start_instance;
780 nv50->instance_max = info->instance_count - 1;
781
782 /* For picking only a few vertices from a large user buffer, push is better,
783 * if index count is larger and we expect repeated vertices, suggest upload.
784 */
785 nv50->vbo_push_hint = /* the 64 is heuristic */
786 !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
787
788 if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) {
789 if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
790 nv50->dirty |= NV50_NEW_ARRAYS;
791 else
792 if (!nv50->vbo_fifo)
793 nv50_update_user_vbufs(nv50);
794 }
795
796 if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
797 nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
798
799 nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
800
801 push->kick_notify = nv50_draw_vbo_kick_notify;
802
803 /* TODO: Instead of iterating over all the buffer resources looking for
804 * coherent buffers, keep track of a context-wide count.
805 */
806 for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
807 uint32_t valid = nv50->constbuf_valid[s];
808
809 while (valid && !nv50->cb_dirty) {
810 const unsigned i = ffs(valid) - 1;
811 struct pipe_resource *res;
812
813 valid &= ~(1 << i);
814 if (nv50->constbuf[s][i].user)
815 continue;
816
817 res = nv50->constbuf[s][i].u.buf;
818 if (!res)
819 continue;
820
821 if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
822 nv50->cb_dirty = true;
823 }
824 }
825
826 /* If there are any coherent constbufs, flush the cache */
827 if (nv50->cb_dirty) {
828 BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
829 PUSH_DATA (push, 0);
830 nv50->cb_dirty = false;
831 }
832
833 for (s = 0; s < 3 && !tex_dirty; ++s) {
834 for (i = 0; i < nv50->num_textures[s] && !tex_dirty; ++i) {
835 if (!nv50->textures[s][i] ||
836 nv50->textures[s][i]->texture->target != PIPE_BUFFER)
837 continue;
838 if (nv50->textures[s][i]->texture->flags &
839 PIPE_RESOURCE_FLAG_MAP_COHERENT)
840 tex_dirty = true;
841 }
842 }
843 if (tex_dirty) {
844 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
845 PUSH_DATA (push, 0x20);
846 }
847
848 if (nv50->vbo_fifo) {
849 nv50_push_vbo(nv50, info);
850 push->kick_notify = nv50_default_kick_notify;
851 nouveau_pushbuf_bufctx(push, NULL);
852 return;
853 }
854
855 if (nv50->state.instance_base != info->start_instance) {
856 nv50->state.instance_base = info->start_instance;
857 /* NOTE: this does not affect the shader input, should it ? */
858 BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
859 PUSH_DATA (push, info->start_instance);
860 }
861
862 for (i = 0; i < nv50->num_vtxbufs && !nv50->base.vbo_dirty; ++i) {
863 if (!nv50->vtxbuf[i].buffer)
864 continue;
865 if (nv50->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
866 nv50->base.vbo_dirty = true;
867 }
868
869 if (nv50->base.vbo_dirty) {
870 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
871 PUSH_DATA (push, 0);
872 nv50->base.vbo_dirty = false;
873 }
874
875 if (info->indexed) {
876 bool shorten = info->max_index <= 65535;
877
878 if (info->primitive_restart != nv50->state.prim_restart) {
879 if (info->primitive_restart) {
880 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
881 PUSH_DATA (push, 1);
882 PUSH_DATA (push, info->restart_index);
883
884 if (info->restart_index > 65535)
885 shorten = false;
886 } else {
887 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
888 PUSH_DATA (push, 0);
889 }
890 nv50->state.prim_restart = info->primitive_restart;
891 } else
892 if (info->primitive_restart) {
893 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
894 PUSH_DATA (push, info->restart_index);
895
896 if (info->restart_index > 65535)
897 shorten = false;
898 }
899
900 nv50_draw_elements(nv50, shorten,
901 info->mode, info->start, info->count,
902 info->instance_count, info->index_bias);
903 } else
904 if (unlikely(info->count_from_stream_output)) {
905 nva0_draw_stream_output(nv50, info);
906 } else {
907 nv50_draw_arrays(nv50,
908 info->mode, info->start, info->count,
909 info->instance_count);
910 }
911 push->kick_notify = nv50_default_kick_notify;
912
913 nv50_release_user_vbufs(nv50);
914
915 nouveau_pushbuf_bufctx(push, NULL);
916 }