src/gallium/drivers/nouveau/nv50/nv50_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nv50/nv50_context.h"
  30 #include "nv50/nv50_resource.h"
  31
  32 #include "nv50/nv50_3d.xml.h"
  33
  34 void
  35 nv50_vertex_state_delete(struct pipe_context *pipe,
  36                          void *hwcso)
  37 {
  38    struct nv50_vertex_stateobj *so = hwcso;
  39
  40    if (so->translate)
  41       so->translate->release(so->translate);
  42    FREE(hwcso);
  43 }
  44
  45 void *
  46 nv50_vertex_state_create(struct pipe_context *pipe,
  47                          unsigned num_elements,
  48                          const struct pipe_vertex_element *elements)
  49 {
  50     struct nv50_vertex_stateobj *so;
  51     struct translate_key transkey;
  52     unsigned i;
  53
  54     so = MALLOC(sizeof(*so) +
  55                 num_elements * sizeof(struct nv50_vertex_element));
  56     if (!so)
  57         return NULL;
  58     so->num_elements = num_elements;
  59     so->instance_elts = 0;
  60     so->instance_bufs = 0;
  61     so->need_conversion = FALSE;
  62
  63     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  64
  65     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  66        so->min_instance_div[i] = 0xffffffff;
  67
  68     transkey.nr_elements = 0;
  69     transkey.output_stride = 0;
  70
  71     for (i = 0; i < num_elements; ++i) {
  72         const struct pipe_vertex_element *ve = &elements[i];
  73         const unsigned vbi = ve->vertex_buffer_index;
  74         unsigned size;
  75         enum pipe_format fmt = ve->src_format;
  76
  77         so->element[i].pipe = elements[i];
  78         so->element[i].state = nv50_format_table[fmt].vtx;
  79
  80         if (!so->element[i].state) {
  81             switch (util_format_get_nr_components(fmt)) {
  82             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  83             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  84             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  85             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  86             default:
  87                 assert(0);
  88                 FREE(so);
  89                 return NULL;
  90             }
  91             so->element[i].state = nv50_format_table[fmt].vtx;
  92             so->need_conversion = TRUE;
  93         }
  94         so->element[i].state |= i;
  95
  96         size = util_format_get_blocksize(fmt);
  97         if (so->vb_access_size[vbi] < (ve->src_offset + size))
  98            so->vb_access_size[vbi] = ve->src_offset + size;
  99
 100         if (1) {
 101             unsigned j = transkey.nr_elements++;
 102
 103             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
 104             transkey.element[j].input_format = ve->src_format;
 105             transkey.element[j].input_buffer = vbi;
 106             transkey.element[j].input_offset = ve->src_offset;
 107             transkey.element[j].instance_divisor = ve->instance_divisor;
 108
 109             transkey.element[j].output_format = fmt;
 110             transkey.element[j].output_offset = transkey.output_stride;
 111             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 112
 113             if (unlikely(ve->instance_divisor)) {
 114                so->instance_elts |= 1 << i;
 115                so->instance_bufs |= 1 << vbi;
 116                if (ve->instance_divisor < so->min_instance_div[vbi])
 117                   so->min_instance_div[vbi] = ve->instance_divisor;
 118             }
 119         }
 120     }
 121
 122     so->translate = translate_create(&transkey);
 123     so->vertex_size = transkey.output_stride / 4;
 124     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
 125        MAX2(so->vertex_size, 1);
 126
 127     return so;
 128 }
 129
 130 #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
 131    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
 132    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
 133    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
 134
 135 static void
 136 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
 137                   struct pipe_vertex_element *ve, unsigned attr)
 138 {
 139    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 140    const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
 141    float v[4];
 142    const unsigned nc = util_format_get_nr_components(ve->src_format);
 143    const struct util_format_description *desc =
 144       util_format_description(ve->src_format);
 145
 146    assert(vb->user_buffer);
 147
 148    if (desc->channel[0].pure_integer) {
 149       if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
 150          desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
 151       } else {
 152          desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
 153       }
 154    } else {
 155       desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
 156    }
 157
 158    switch (nc) {
 159    case 4:
 160       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
 161       PUSH_DATAf(push, v[0]);
 162       PUSH_DATAf(push, v[1]);
 163       PUSH_DATAf(push, v[2]);
 164       PUSH_DATAf(push, v[3]);
 165       break;
 166    case 3:
 167       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
 168       PUSH_DATAf(push, v[0]);
 169       PUSH_DATAf(push, v[1]);
 170       PUSH_DATAf(push, v[2]);
 171       break;
 172    case 2:
 173       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
 174       PUSH_DATAf(push, v[0]);
 175       PUSH_DATAf(push, v[1]);
 176       break;
 177    case 1:
 178       if (attr == nv50->vertprog->vp.edgeflag) {
 179          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 180          PUSH_DATA (push, v[0] ? 1 : 0);
 181       }
 182       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
 183       PUSH_DATAf(push, v[0]);
 184       break;
 185    default:
 186       assert(0);
 187       break;
 188    }
 189 }
 190
 191 static INLINE void
 192 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
 193                      uint32_t *base, uint32_t *size)
 194 {
 195    assert(vbi < PIPE_MAX_ATTRIBS);
 196    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
 197       /* TODO: use min and max instance divisor to get a proper range */
 198       *base = 0;
 199       *size = nv50->vtxbuf[vbi].buffer->width0;
 200    } else {
 201       /* NOTE: if there are user buffers, we *must* have index bounds */
 202       assert(nv50->vb_elt_limit != ~0);
 203       *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
 204       *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
 205          nv50->vertex->vb_access_size[vbi];
 206    }
 207 }
 208
 209 static void
 210 nv50_upload_user_buffers(struct nv50_context *nv50,
 211                          uint64_t addrs[], uint32_t limits[])
 212 {
 213    unsigned b;
 214
 215    assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
 216    for (b = 0; b < nv50->num_vtxbufs; ++b) {
 217       struct nouveau_bo *bo;
 218       const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 219       uint32_t base, size;
 220
 221       if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
 222          continue;
 223       nv50_user_vbuf_range(nv50, b, &base, &size);
 224
 225       limits[b] = base + size - 1;
 226       addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size,
 227                                       &bo);
 228       if (addrs[b])
 229          BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART |
 230                       NOUVEAU_BO_RD, bo);
 231    }
 232    nv50->base.vbo_dirty = TRUE;
 233 }
 234
 235 static void
 236 nv50_update_user_vbufs(struct nv50_context *nv50)
 237 {
 238    uint64_t address[PIPE_MAX_ATTRIBS];
 239    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 240    unsigned i;
 241    uint32_t written = 0;
 242
 243    for (i = 0; i < nv50->vertex->num_elements; ++i) {
 244       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
 245       const unsigned b = ve->vertex_buffer_index;
 246       struct pipe_vertex_buffer *vb;
 247       uint32_t base, size;
 248
 249       assert(b < PIPE_MAX_ATTRIBS);
 250       vb = &nv50->vtxbuf[b];
 251
 252       if (!(nv50->vbo_user & (1 << b)))
 253          continue;
 254
 255       if (!vb->stride) {
 256          nv50_emit_vtxattr(nv50, vb, ve, i);
 257          continue;
 258       }
 259       nv50_user_vbuf_range(nv50, b, &base, &size);
 260
 261       if (!(written & (1 << b))) {
 262          struct nouveau_bo *bo;
 263          const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 264          written |= 1 << b;
 265          address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer,
 266                                            base, size, &bo);
 267          if (address[b])
 268             BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo);
 269       }
 270
 271       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 272       PUSH_DATAh(push, address[b] + base + size - 1);
 273       PUSH_DATA (push, address[b] + base + size - 1);
 274       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 275       PUSH_DATAh(push, address[b] + ve->src_offset);
 276       PUSH_DATA (push, address[b] + ve->src_offset);
 277    }
 278    nv50->base.vbo_dirty = TRUE;
 279 }
 280
 281 static INLINE void
 282 nv50_release_user_vbufs(struct nv50_context *nv50)
 283 {
 284    if (nv50->vbo_user) {
 285       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP);
 286       nouveau_scratch_done(&nv50->base);
 287    }
 288 }
 289
 290 void
 291 nv50_vertex_arrays_validate(struct nv50_context *nv50)
 292 {
 293    uint64_t addrs[PIPE_MAX_ATTRIBS];
 294    uint32_t limits[PIPE_MAX_ATTRIBS];
 295    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 296    struct nv50_vertex_stateobj *vertex = nv50->vertex;
 297    struct pipe_vertex_buffer *vb;
 298    struct nv50_vertex_element *ve;
 299    uint32_t mask;
 300    uint32_t refd = 0;
 301    unsigned i;
 302    const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
 303
 304    if (unlikely(vertex->need_conversion))
 305       nv50->vbo_fifo = ~0;
 306    else
 307    if (nv50->vbo_user & ~nv50->vbo_constant)
 308       nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
 309    else
 310       nv50->vbo_fifo = 0;
 311
 312    if (!nv50->vbo_fifo) {
 313       /* if vertex buffer was written by GPU - flush VBO cache */
 314       assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
 315       for (i = 0; i < nv50->num_vtxbufs; ++i) {
 316          struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer);
 317          if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 318             buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 319             nv50->base.vbo_dirty = TRUE;
 320             break;
 321          }
 322       }
 323    }
 324
 325    /* update vertex format state */
 326    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
 327    if (nv50->vbo_fifo) {
 328       nv50->state.num_vtxelts = vertex->num_elements;
 329       for (i = 0; i < vertex->num_elements; ++i)
 330          PUSH_DATA (push, vertex->element[i].state);
 331       for (; i < n; ++i)
 332          PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 333       for (i = 0; i < n; ++i) {
 334          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 335          PUSH_DATA (push, 0);
 336       }
 337       return;
 338    }
 339    for (i = 0; i < vertex->num_elements; ++i) {
 340       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 341
 342       assert(b < PIPE_MAX_ATTRIBS);
 343       ve = &vertex->element[i];
 344       vb = &nv50->vtxbuf[b];
 345
 346       if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
 347          PUSH_DATA(push, ve->state);
 348       else
 349          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
 350    }
 351    for (; i < n; ++i)
 352       PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 353
 354    /* update per-instance enables */
 355    mask = vertex->instance_elts ^ nv50->state.instance_elts;
 356    while (mask) {
 357       const int i = ffs(mask) - 1;
 358       mask &= ~(1 << i);
 359       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 360       PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
 361    }
 362    nv50->state.instance_elts = vertex->instance_elts;
 363
 364    if (nv50->vbo_user & ~nv50->vbo_constant)
 365       nv50_upload_user_buffers(nv50, addrs, limits);
 366
 367    /* update buffers and set constant attributes */
 368    for (i = 0; i < vertex->num_elements; ++i) {
 369       uint64_t address, limit;
 370       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 371
 372       assert(b < PIPE_MAX_ATTRIBS);
 373       ve = &vertex->element[i];
 374       vb = &nv50->vtxbuf[b];
 375
 376       if (unlikely(nv50->vbo_constant & (1 << b))) {
 377          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 378          PUSH_DATA (push, 0);
 379          nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
 380          continue;
 381       } else
 382       if (nv50->vbo_user & (1 << b)) {
 383          address = addrs[b] + ve->pipe.src_offset;
 384          limit = addrs[b] + limits[b];
 385       } else {
 386          struct nv04_resource *buf = nv04_resource(vb->buffer);
 387          if (!(refd & (1 << b))) {
 388             refd |= 1 << b;
 389             BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
 390          }
 391          address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
 392          limit = buf->address + buf->base.width0 - 1;
 393       }
 394
 395       if (unlikely(ve->pipe.instance_divisor)) {
 396          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
 397          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 398          PUSH_DATAh(push, address);
 399          PUSH_DATA (push, address);
 400          PUSH_DATA (push, ve->pipe.instance_divisor);
 401       } else {
 402          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
 403          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 404          PUSH_DATAh(push, address);
 405          PUSH_DATA (push, address);
 406       }
 407       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 408       PUSH_DATAh(push, limit);
 409       PUSH_DATA (push, limit);
 410    }
 411    for (; i < nv50->state.num_vtxelts; ++i) {
 412       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 413       PUSH_DATA (push, 0);
 414    }
 415    nv50->state.num_vtxelts = vertex->num_elements;
 416 }
 417
 418 #define NV50_PRIM_GL_CASE(n) \
 419    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 420
 421 static INLINE unsigned
 422 nv50_prim_gl(unsigned prim)
 423 {
 424    switch (prim) {
 425    NV50_PRIM_GL_CASE(POINTS);
 426    NV50_PRIM_GL_CASE(LINES);
 427    NV50_PRIM_GL_CASE(LINE_LOOP);
 428    NV50_PRIM_GL_CASE(LINE_STRIP);
 429    NV50_PRIM_GL_CASE(TRIANGLES);
 430    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
 431    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
 432    NV50_PRIM_GL_CASE(QUADS);
 433    NV50_PRIM_GL_CASE(QUAD_STRIP);
 434    NV50_PRIM_GL_CASE(POLYGON);
 435    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
 436    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 437    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 438    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 439    default:
 440       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 441       break;
 442    }
 443 }
 444
 445 /* For pre-nva0 transform feedback. */
 446 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
 447 {
 448    [PIPE_PRIM_POINTS] = 1,
 449    [PIPE_PRIM_LINES] = 2,
 450    [PIPE_PRIM_LINE_LOOP] = 2,
 451    [PIPE_PRIM_LINE_STRIP] = 2,
 452    [PIPE_PRIM_TRIANGLES] = 3,
 453    [PIPE_PRIM_TRIANGLE_STRIP] = 3,
 454    [PIPE_PRIM_TRIANGLE_FAN] = 3,
 455    [PIPE_PRIM_QUADS] = 3,
 456    [PIPE_PRIM_QUAD_STRIP] = 3,
 457    [PIPE_PRIM_POLYGON] = 3,
 458    [PIPE_PRIM_LINES_ADJACENCY] = 2,
 459    [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
 460    [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
 461    [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
 462 };
 463
 464 static void
 465 nv50_draw_arrays(struct nv50_context *nv50,
 466                  unsigned mode, unsigned start, unsigned count,
 467                  unsigned instance_count)
 468 {
 469    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 470    unsigned prim;
 471
 472    if (nv50->state.index_bias) {
 473       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 474       PUSH_DATA (push, 0);
 475       nv50->state.index_bias = 0;
 476    }
 477
 478    prim = nv50_prim_gl(mode);
 479
 480    while (instance_count--) {
 481       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 482       PUSH_DATA (push, prim);
 483       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
 484       PUSH_DATA (push, start);
 485       PUSH_DATA (push, count);
 486       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 487       PUSH_DATA (push, 0);
 488
 489       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 490    }
 491 }
 492
 493 static void
 494 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
 495                               unsigned start, unsigned count)
 496 {
 497    map += start;
 498
 499    if (count & 3) {
 500       unsigned i;
 501       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
 502       for (i = 0; i < (count & 3); ++i)
 503          PUSH_DATA(push, *map++);
 504       count &= ~3;
 505    }
 506    while (count) {
 507       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 508
 509       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
 510       for (i = 0; i < nr; ++i) {
 511          PUSH_DATA(push,
 512                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 513          map += 4;
 514       }
 515       count -= nr * 4;
 516    }
 517 }
 518
 519 static void
 520 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
 521                               unsigned start, unsigned count)
 522 {
 523    map += start;
 524
 525    if (count & 1) {
 526       count &= ~1;
 527       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 528       PUSH_DATA (push, *map++);
 529    }
 530    while (count) {
 531       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 532
 533       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 534       for (i = 0; i < nr; ++i) {
 535          PUSH_DATA(push, (map[1] << 16) | map[0]);
 536          map += 2;
 537       }
 538       count -= nr * 2;
 539    }
 540 }
 541
 542 static void
 543 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
 544                               unsigned start, unsigned count)
 545 {
 546    map += start;
 547
 548    while (count) {
 549       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 550
 551       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
 552       PUSH_DATAp(push, map, nr);
 553
 554       map += nr;
 555       count -= nr;
 556    }
 557 }
 558
 559 static void
 560 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 561                                     const uint32_t *map,
 562                                     unsigned start, unsigned count)
 563 {
 564    map += start;
 565
 566    if (count & 1) {
 567       count--;
 568       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 569       PUSH_DATA (push, *map++);
 570    }
 571    while (count) {
 572       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 573
 574       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 575       for (i = 0; i < nr; ++i) {
 576          PUSH_DATA(push, (map[1] << 16) | map[0]);
 577          map += 2;
 578       }
 579       count -= nr * 2;
 580    }
 581 }
 582
 583 static void
 584 nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
 585                    unsigned mode, unsigned start, unsigned count,
 586                    unsigned instance_count, int32_t index_bias)
 587 {
 588    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 589    unsigned prim;
 590    const unsigned index_size = nv50->idxbuf.index_size;
 591
 592    prim = nv50_prim_gl(mode);
 593
 594    if (index_bias != nv50->state.index_bias) {
 595       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 596       PUSH_DATA (push, index_bias);
 597       nv50->state.index_bias = index_bias;
 598    }
 599
 600    if (nv50->idxbuf.buffer) {
 601       struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
 602       unsigned pb_start;
 603       unsigned pb_bytes;
 604       const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
 605
 606       start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
 607
 608       assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
 609
 610       /* This shouldn't have to be here. The going theory is that the buffer
 611        * is being filled in by PGRAPH, and it's not done yet by the time it
 612        * gets submitted to PFIFO, which in turn starts immediately prefetching
 613        * the not-yet-written data. Ideally this wait would only happen on
 614        * pushbuf submit, but it's probably not a big performance difference.
 615        */
 616       if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
 617          nouveau_fence_wait(buf->fence_wr);
 618
 619       while (instance_count--) {
 620          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 621          PUSH_DATA (push, prim);
 622
 623          nouveau_pushbuf_space(push, 8, 0, 1);
 624
 625          switch (index_size) {
 626          case 4:
 627             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
 628             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
 629             break;
 630          case 2:
 631             pb_start = (start & ~1) * 2;
 632             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
 633
 634             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 635             PUSH_DATA (push, (start << 31) | count);
 636             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
 637             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 638             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 639             PUSH_DATA (push, 0);
 640             break;
 641          default:
 642             assert(index_size == 1);
 643             pb_start = start & ~3;
 644             pb_bytes = ((start + count + 3) & ~3) - pb_start;
 645
 646             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 647             PUSH_DATA (push, (start << 30) | count);
 648             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
 649             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 650             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 651             PUSH_DATA (push, 0);
 652             break;
 653          }
 654          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 655          PUSH_DATA (push, 0);
 656
 657          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 658       }
 659    } else {
 660       const void *data = nv50->idxbuf.user_buffer;
 661
 662       while (instance_count--) {
 663          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 664          PUSH_DATA (push, prim);
 665          switch (index_size) {
 666          case 1:
 667             nv50_draw_elements_inline_u08(push, data, start, count);
 668             break;
 669          case 2:
 670             nv50_draw_elements_inline_u16(push, data, start, count);
 671             break;
 672          case 4:
 673             if (shorten)
 674                nv50_draw_elements_inline_u32_short(push, data, start, count);
 675             else
 676                nv50_draw_elements_inline_u32(push, data, start, count);
 677             break;
 678          default:
 679             assert(0);
 680             return;
 681          }
 682          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 683          PUSH_DATA (push, 0);
 684
 685          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 686       }
 687    }
 688 }
 689
 690 static void
 691 nva0_draw_stream_output(struct nv50_context *nv50,
 692                         const struct pipe_draw_info *info)
 693 {
 694    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 695    struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
 696    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
 697    unsigned num_instances = info->instance_count;
 698    unsigned mode = nv50_prim_gl(info->mode);
 699
 700    if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
 701       /* A proper implementation without waiting doesn't seem possible,
 702        * so don't bother.
 703        */
 704       NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
 705       return;
 706    }
 707
 708    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 709       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 710       PUSH_SPACE(push, 4);
 711       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 712       PUSH_DATA (push, 0);
 713       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 714       PUSH_DATA (push, 0);
 715    }
 716
 717    assert(num_instances);
 718    do {
 719       PUSH_SPACE(push, 8);
 720       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 721       PUSH_DATA (push, mode);
 722       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
 723       PUSH_DATA (push, 0);
 724       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
 725       PUSH_DATA (push, 0);
 726       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BYTES), 1);
 727       nv50_query_pushbuf_submit(push, so->pq, 0x4);
 728       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 729       PUSH_DATA (push, 0);
 730
 731       mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 732    } while (--num_instances);
 733 }
 734
 735 static void
 736 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
 737 {
 738    struct nv50_screen *screen = chan->user_priv;
 739
 740    nouveau_fence_update(&screen->base, TRUE);
 741
 742    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, TRUE);
 743 }
 744
 745 void
 746 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 747 {
 748    struct nv50_context *nv50 = nv50_context(pipe);
 749    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 750
 751    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
 752    nv50->vb_elt_first = info->min_index + info->index_bias;
 753    nv50->vb_elt_limit = info->max_index - info->min_index;
 754    nv50->instance_off = info->start_instance;
 755    nv50->instance_max = info->instance_count - 1;
 756
 757    /* For picking only a few vertices from a large user buffer, push is better,
 758     * if index count is larger and we expect repeated vertices, suggest upload.
 759     */
 760    nv50->vbo_push_hint = /* the 64 is heuristic */
 761       !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
 762
 763    if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) {
 764       if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
 765          nv50->dirty |= NV50_NEW_ARRAYS;
 766       else
 767       if (!nv50->vbo_fifo)
 768          nv50_update_user_vbufs(nv50);
 769    }
 770
 771    if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
 772       nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
 773
 774    nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
 775
 776    push->kick_notify = nv50_draw_vbo_kick_notify;
 777
 778    if (nv50->vbo_fifo) {
 779       nv50_push_vbo(nv50, info);
 780       push->kick_notify = nv50_default_kick_notify;
 781       nouveau_pushbuf_bufctx(push, NULL);
 782       return;
 783    }
 784
 785    if (nv50->state.instance_base != info->start_instance) {
 786       nv50->state.instance_base = info->start_instance;
 787       /* NOTE: this does not affect the shader input, should it ? */
 788       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
 789       PUSH_DATA (push, info->start_instance);
 790    }
 791
 792    if (nv50->base.vbo_dirty) {
 793       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 794       PUSH_DATA (push, 0);
 795       nv50->base.vbo_dirty = FALSE;
 796    }
 797
 798    if (info->indexed) {
 799       boolean shorten = info->max_index <= 65535;
 800
 801       if (info->primitive_restart != nv50->state.prim_restart) {
 802          if (info->primitive_restart) {
 803             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
 804             PUSH_DATA (push, 1);
 805             PUSH_DATA (push, info->restart_index);
 806
 807             if (info->restart_index > 65535)
 808                shorten = FALSE;
 809          } else {
 810             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
 811             PUSH_DATA (push, 0);
 812          }
 813          nv50->state.prim_restart = info->primitive_restart;
 814       } else
 815       if (info->primitive_restart) {
 816          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
 817          PUSH_DATA (push, info->restart_index);
 818
 819          if (info->restart_index > 65535)
 820             shorten = FALSE;
 821       }
 822
 823       nv50_draw_elements(nv50, shorten,
 824                          info->mode, info->start, info->count,
 825                          info->instance_count, info->index_bias);
 826    } else
 827    if (unlikely(info->count_from_stream_output)) {
 828       nva0_draw_stream_output(nv50, info);
 829    } else {
 830       nv50_draw_arrays(nv50,
 831                        info->mode, info->start, info->count,
 832                        info->instance_count);
 833    }
 834    push->kick_notify = nv50_default_kick_notify;
 835
 836    nv50_release_user_vbufs(nv50);
 837
 838    nouveau_pushbuf_bufctx(push, NULL);
 839 }