src/gallium/drivers/nouveau/nv50/nv50_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nv50/nv50_context.h"
  30 #include "nv50/nv50_resource.h"
  31
  32 #include "nv50/nv50_3d.xml.h"
  33
  34 void
  35 nv50_vertex_state_delete(struct pipe_context *pipe,
  36                          void *hwcso)
  37 {
  38    struct nv50_vertex_stateobj *so = hwcso;
  39
  40    if (so->translate)
  41       so->translate->release(so->translate);
  42    FREE(hwcso);
  43 }
  44
  45 void *
  46 nv50_vertex_state_create(struct pipe_context *pipe,
  47                          unsigned num_elements,
  48                          const struct pipe_vertex_element *elements)
  49 {
  50     struct nv50_vertex_stateobj *so;
  51     struct translate_key transkey;
  52     unsigned i;
  53
  54     so = MALLOC(sizeof(*so) +
  55                 num_elements * sizeof(struct nv50_vertex_element));
  56     if (!so)
  57         return NULL;
  58     so->num_elements = num_elements;
  59     so->instance_elts = 0;
  60     so->instance_bufs = 0;
  61     so->need_conversion = false;
  62
  63     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  64
  65     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  66        so->min_instance_div[i] = 0xffffffff;
  67
  68     transkey.nr_elements = 0;
  69     transkey.output_stride = 0;
  70
  71     for (i = 0; i < num_elements; ++i) {
  72         const struct pipe_vertex_element *ve = &elements[i];
  73         const unsigned vbi = ve->vertex_buffer_index;
  74         unsigned size;
  75         enum pipe_format fmt = ve->src_format;
  76
  77         so->element[i].pipe = elements[i];
  78         so->element[i].state = nv50_format_table[fmt].vtx;
  79
  80         if (!so->element[i].state) {
  81             switch (util_format_get_nr_components(fmt)) {
  82             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  83             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  84             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  85             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  86             default:
  87                 assert(0);
  88                 FREE(so);
  89                 return NULL;
  90             }
  91             so->element[i].state = nv50_format_table[fmt].vtx;
  92             so->need_conversion = true;
  93         }
  94         so->element[i].state |= i;
  95
  96         size = util_format_get_blocksize(fmt);
  97         if (so->vb_access_size[vbi] < (ve->src_offset + size))
  98            so->vb_access_size[vbi] = ve->src_offset + size;
  99
 100         if (1) {
 101             unsigned j = transkey.nr_elements++;
 102
 103             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
 104             transkey.element[j].input_format = ve->src_format;
 105             transkey.element[j].input_buffer = vbi;
 106             transkey.element[j].input_offset = ve->src_offset;
 107             transkey.element[j].instance_divisor = ve->instance_divisor;
 108
 109             transkey.element[j].output_format = fmt;
 110             transkey.element[j].output_offset = transkey.output_stride;
 111             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 112
 113             if (unlikely(ve->instance_divisor)) {
 114                so->instance_elts |= 1 << i;
 115                so->instance_bufs |= 1 << vbi;
 116                if (ve->instance_divisor < so->min_instance_div[vbi])
 117                   so->min_instance_div[vbi] = ve->instance_divisor;
 118             }
 119         }
 120     }
 121
 122     so->translate = translate_create(&transkey);
 123     so->vertex_size = transkey.output_stride / 4;
 124     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
 125        MAX2(so->vertex_size, 1);
 126
 127     return so;
 128 }
 129
 130 #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
 131    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
 132    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
 133    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
 134
 135 static void
 136 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
 137                   struct pipe_vertex_element *ve, unsigned attr)
 138 {
 139    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 140    const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
 141    float v[4];
 142    const unsigned nc = util_format_get_nr_components(ve->src_format);
 143    const struct util_format_description *desc =
 144       util_format_description(ve->src_format);
 145
 146    assert(vb->user_buffer);
 147
 148    if (desc->channel[0].pure_integer) {
 149       if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
 150          desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
 151       } else {
 152          desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
 153       }
 154    } else {
 155       desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
 156    }
 157
 158    switch (nc) {
 159    case 4:
 160       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
 161       PUSH_DATAf(push, v[0]);
 162       PUSH_DATAf(push, v[1]);
 163       PUSH_DATAf(push, v[2]);
 164       PUSH_DATAf(push, v[3]);
 165       break;
 166    case 3:
 167       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
 168       PUSH_DATAf(push, v[0]);
 169       PUSH_DATAf(push, v[1]);
 170       PUSH_DATAf(push, v[2]);
 171       break;
 172    case 2:
 173       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
 174       PUSH_DATAf(push, v[0]);
 175       PUSH_DATAf(push, v[1]);
 176       break;
 177    case 1:
 178       if (attr == nv50->vertprog->vp.edgeflag) {
 179          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 180          PUSH_DATA (push, v[0] ? 1 : 0);
 181       }
 182       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
 183       PUSH_DATAf(push, v[0]);
 184       break;
 185    default:
 186       assert(0);
 187       break;
 188    }
 189 }
 190
 191 static inline void
 192 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
 193                      uint32_t *base, uint32_t *size)
 194 {
 195    assert(vbi < PIPE_MAX_ATTRIBS);
 196    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
 197       /* TODO: use min and max instance divisor to get a proper range */
 198       *base = 0;
 199       *size = nv50->vtxbuf[vbi].buffer->width0;
 200    } else {
 201       /* NOTE: if there are user buffers, we *must* have index bounds */
 202       assert(nv50->vb_elt_limit != ~0);
 203       *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
 204       *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
 205          nv50->vertex->vb_access_size[vbi];
 206    }
 207 }
 208
 209 static void
 210 nv50_upload_user_buffers(struct nv50_context *nv50,
 211                          uint64_t addrs[], uint32_t limits[])
 212 {
 213    unsigned b;
 214
 215    assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
 216    for (b = 0; b < nv50->num_vtxbufs; ++b) {
 217       struct nouveau_bo *bo;
 218       const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 219       uint32_t base, size;
 220
 221       if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
 222          continue;
 223       nv50_user_vbuf_range(nv50, b, &base, &size);
 224
 225       limits[b] = base + size - 1;
 226       addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size,
 227                                       &bo);
 228       if (addrs[b])
 229          BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART |
 230                       NOUVEAU_BO_RD, bo);
 231    }
 232    nv50->base.vbo_dirty = true;
 233 }
 234
 235 static void
 236 nv50_update_user_vbufs(struct nv50_context *nv50)
 237 {
 238    uint64_t address[PIPE_MAX_ATTRIBS];
 239    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 240    unsigned i;
 241    uint32_t written = 0;
 242
 243    for (i = 0; i < nv50->vertex->num_elements; ++i) {
 244       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
 245       const unsigned b = ve->vertex_buffer_index;
 246       struct pipe_vertex_buffer *vb;
 247       uint32_t base, size;
 248
 249       assert(b < PIPE_MAX_ATTRIBS);
 250       vb = &nv50->vtxbuf[b];
 251
 252       if (!(nv50->vbo_user & (1 << b)))
 253          continue;
 254
 255       if (!vb->stride) {
 256          nv50_emit_vtxattr(nv50, vb, ve, i);
 257          continue;
 258       }
 259       nv50_user_vbuf_range(nv50, b, &base, &size);
 260
 261       if (!(written & (1 << b))) {
 262          struct nouveau_bo *bo;
 263          const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 264          written |= 1 << b;
 265          address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer,
 266                                            base, size, &bo);
 267          if (address[b])
 268             BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo);
 269       }
 270
 271       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 272       PUSH_DATAh(push, address[b] + base + size - 1);
 273       PUSH_DATA (push, address[b] + base + size - 1);
 274       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 275       PUSH_DATAh(push, address[b] + ve->src_offset);
 276       PUSH_DATA (push, address[b] + ve->src_offset);
 277    }
 278    nv50->base.vbo_dirty = true;
 279 }
 280
 281 static inline void
 282 nv50_release_user_vbufs(struct nv50_context *nv50)
 283 {
 284    if (nv50->vbo_user) {
 285       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP);
 286       nouveau_scratch_done(&nv50->base);
 287    }
 288 }
 289
 290 void
 291 nv50_vertex_arrays_validate(struct nv50_context *nv50)
 292 {
 293    uint64_t addrs[PIPE_MAX_ATTRIBS];
 294    uint32_t limits[PIPE_MAX_ATTRIBS];
 295    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 296    struct nv50_vertex_stateobj *vertex = nv50->vertex;
 297    struct pipe_vertex_buffer *vb;
 298    struct nv50_vertex_element *ve;
 299    uint32_t mask;
 300    uint32_t refd = 0;
 301    unsigned i;
 302    const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
 303
 304    if (unlikely(vertex->need_conversion))
 305       nv50->vbo_fifo = ~0;
 306    else
 307    if (nv50->vbo_user & ~nv50->vbo_constant)
 308       nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
 309    else
 310       nv50->vbo_fifo = 0;
 311
 312    if (!nv50->vbo_fifo) {
 313       /* if vertex buffer was written by GPU - flush VBO cache */
 314       assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
 315       for (i = 0; i < nv50->num_vtxbufs; ++i) {
 316          struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer);
 317          if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 318             buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 319             nv50->base.vbo_dirty = true;
 320             break;
 321          }
 322       }
 323    }
 324
 325    /* update vertex format state */
 326    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
 327    if (nv50->vbo_fifo) {
 328       nv50->state.num_vtxelts = vertex->num_elements;
 329       for (i = 0; i < vertex->num_elements; ++i)
 330          PUSH_DATA (push, vertex->element[i].state);
 331       for (; i < n; ++i)
 332          PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 333       for (i = 0; i < n; ++i) {
 334          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 335          PUSH_DATA (push, 0);
 336       }
 337       return;
 338    }
 339    for (i = 0; i < vertex->num_elements; ++i) {
 340       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 341
 342       assert(b < PIPE_MAX_ATTRIBS);
 343       ve = &vertex->element[i];
 344       vb = &nv50->vtxbuf[b];
 345
 346       if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
 347          PUSH_DATA(push, ve->state);
 348       else
 349          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
 350    }
 351    for (; i < n; ++i)
 352       PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 353
 354    /* update per-instance enables */
 355    mask = vertex->instance_elts ^ nv50->state.instance_elts;
 356    while (mask) {
 357       const int i = ffs(mask) - 1;
 358       mask &= ~(1 << i);
 359       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 360       PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
 361    }
 362    nv50->state.instance_elts = vertex->instance_elts;
 363
 364    if (nv50->vbo_user & ~nv50->vbo_constant)
 365       nv50_upload_user_buffers(nv50, addrs, limits);
 366
 367    /* update buffers and set constant attributes */
 368    for (i = 0; i < vertex->num_elements; ++i) {
 369       uint64_t address, limit;
 370       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 371
 372       assert(b < PIPE_MAX_ATTRIBS);
 373       ve = &vertex->element[i];
 374       vb = &nv50->vtxbuf[b];
 375
 376       if (unlikely(nv50->vbo_constant & (1 << b))) {
 377          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 378          PUSH_DATA (push, 0);
 379          nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
 380          continue;
 381       } else
 382       if (nv50->vbo_user & (1 << b)) {
 383          address = addrs[b] + ve->pipe.src_offset;
 384          limit = addrs[b] + limits[b];
 385       } else
 386       if (!vb->buffer) {
 387          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 388          PUSH_DATA (push, 0);
 389          continue;
 390       } else {
 391          struct nv04_resource *buf = nv04_resource(vb->buffer);
 392          if (!(refd & (1 << b))) {
 393             refd |= 1 << b;
 394             BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
 395          }
 396          address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
 397          limit = buf->address + buf->base.width0 - 1;
 398       }
 399
 400       if (unlikely(ve->pipe.instance_divisor)) {
 401          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
 402          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 403          PUSH_DATAh(push, address);
 404          PUSH_DATA (push, address);
 405          PUSH_DATA (push, ve->pipe.instance_divisor);
 406       } else {
 407          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
 408          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 409          PUSH_DATAh(push, address);
 410          PUSH_DATA (push, address);
 411       }
 412       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 413       PUSH_DATAh(push, limit);
 414       PUSH_DATA (push, limit);
 415    }
 416    for (; i < nv50->state.num_vtxelts; ++i) {
 417       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 418       PUSH_DATA (push, 0);
 419    }
 420    nv50->state.num_vtxelts = vertex->num_elements;
 421 }
 422
 423 #define NV50_PRIM_GL_CASE(n) \
 424    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 425
 426 static inline unsigned
 427 nv50_prim_gl(unsigned prim)
 428 {
 429    switch (prim) {
 430    NV50_PRIM_GL_CASE(POINTS);
 431    NV50_PRIM_GL_CASE(LINES);
 432    NV50_PRIM_GL_CASE(LINE_LOOP);
 433    NV50_PRIM_GL_CASE(LINE_STRIP);
 434    NV50_PRIM_GL_CASE(TRIANGLES);
 435    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
 436    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
 437    NV50_PRIM_GL_CASE(QUADS);
 438    NV50_PRIM_GL_CASE(QUAD_STRIP);
 439    NV50_PRIM_GL_CASE(POLYGON);
 440    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
 441    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 442    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 443    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 444    default:
 445       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 446       break;
 447    }
 448 }
 449
 450 /* For pre-nva0 transform feedback. */
 451 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
 452 {
 453    [PIPE_PRIM_POINTS] = 1,
 454    [PIPE_PRIM_LINES] = 2,
 455    [PIPE_PRIM_LINE_LOOP] = 2,
 456    [PIPE_PRIM_LINE_STRIP] = 2,
 457    [PIPE_PRIM_TRIANGLES] = 3,
 458    [PIPE_PRIM_TRIANGLE_STRIP] = 3,
 459    [PIPE_PRIM_TRIANGLE_FAN] = 3,
 460    [PIPE_PRIM_QUADS] = 3,
 461    [PIPE_PRIM_QUAD_STRIP] = 3,
 462    [PIPE_PRIM_POLYGON] = 3,
 463    [PIPE_PRIM_LINES_ADJACENCY] = 2,
 464    [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
 465    [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
 466    [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
 467 };
 468
 469 static void
 470 nv50_draw_arrays(struct nv50_context *nv50,
 471                  unsigned mode, unsigned start, unsigned count,
 472                  unsigned instance_count)
 473 {
 474    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 475    unsigned prim;
 476
 477    if (nv50->state.index_bias) {
 478       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 479       PUSH_DATA (push, 0);
 480       if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
 481          BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
 482          PUSH_DATA (push, 0);
 483       }
 484       nv50->state.index_bias = 0;
 485    }
 486
 487    prim = nv50_prim_gl(mode);
 488
 489    while (instance_count--) {
 490       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 491       PUSH_DATA (push, prim);
 492       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
 493       PUSH_DATA (push, start);
 494       PUSH_DATA (push, count);
 495       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 496       PUSH_DATA (push, 0);
 497
 498       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 499    }
 500 }
 501
 502 static void
 503 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
 504                               unsigned start, unsigned count)
 505 {
 506    map += start;
 507
 508    if (count & 3) {
 509       unsigned i;
 510       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
 511       for (i = 0; i < (count & 3); ++i)
 512          PUSH_DATA(push, *map++);
 513       count &= ~3;
 514    }
 515    while (count) {
 516       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 517
 518       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
 519       for (i = 0; i < nr; ++i) {
 520          PUSH_DATA(push,
 521                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 522          map += 4;
 523       }
 524       count -= nr * 4;
 525    }
 526 }
 527
 528 static void
 529 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
 530                               unsigned start, unsigned count)
 531 {
 532    map += start;
 533
 534    if (count & 1) {
 535       count &= ~1;
 536       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 537       PUSH_DATA (push, *map++);
 538    }
 539    while (count) {
 540       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 541
 542       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 543       for (i = 0; i < nr; ++i) {
 544          PUSH_DATA(push, (map[1] << 16) | map[0]);
 545          map += 2;
 546       }
 547       count -= nr * 2;
 548    }
 549 }
 550
 551 static void
 552 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
 553                               unsigned start, unsigned count)
 554 {
 555    map += start;
 556
 557    while (count) {
 558       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 559
 560       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
 561       PUSH_DATAp(push, map, nr);
 562
 563       map += nr;
 564       count -= nr;
 565    }
 566 }
 567
 568 static void
 569 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 570                                     const uint32_t *map,
 571                                     unsigned start, unsigned count)
 572 {
 573    map += start;
 574
 575    if (count & 1) {
 576       count--;
 577       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 578       PUSH_DATA (push, *map++);
 579    }
 580    while (count) {
 581       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 582
 583       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 584       for (i = 0; i < nr; ++i) {
 585          PUSH_DATA(push, (map[1] << 16) | map[0]);
 586          map += 2;
 587       }
 588       count -= nr * 2;
 589    }
 590 }
 591
 592 static void
 593 nv50_draw_elements(struct nv50_context *nv50, bool shorten,
 594                    unsigned mode, unsigned start, unsigned count,
 595                    unsigned instance_count, int32_t index_bias)
 596 {
 597    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 598    unsigned prim;
 599    const unsigned index_size = nv50->idxbuf.index_size;
 600
 601    prim = nv50_prim_gl(mode);
 602
 603    if (index_bias != nv50->state.index_bias) {
 604       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 605       PUSH_DATA (push, index_bias);
 606       if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
 607          BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
 608          PUSH_DATA (push, index_bias);
 609       }
 610       nv50->state.index_bias = index_bias;
 611    }
 612
 613    if (nv50->idxbuf.buffer) {
 614       struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
 615       unsigned pb_start;
 616       unsigned pb_bytes;
 617       const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
 618
 619       start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
 620
 621       assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
 622
 623       /* This shouldn't have to be here. The going theory is that the buffer
 624        * is being filled in by PGRAPH, and it's not done yet by the time it
 625        * gets submitted to PFIFO, which in turn starts immediately prefetching
 626        * the not-yet-written data. Ideally this wait would only happen on
 627        * pushbuf submit, but it's probably not a big performance difference.
 628        */
 629       if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
 630          nouveau_fence_wait(buf->fence_wr);
 631
 632       while (instance_count--) {
 633          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 634          PUSH_DATA (push, prim);
 635
 636          PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
 637          nouveau_pushbuf_space(push, 8, 0, 1);
 638
 639          switch (index_size) {
 640          case 4:
 641             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
 642             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
 643             break;
 644          case 2:
 645             pb_start = (start & ~1) * 2;
 646             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
 647
 648             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 649             PUSH_DATA (push, (start << 31) | count);
 650             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
 651             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 652             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 653             PUSH_DATA (push, 0);
 654             break;
 655          default:
 656             assert(index_size == 1);
 657             pb_start = start & ~3;
 658             pb_bytes = ((start + count + 3) & ~3) - pb_start;
 659
 660             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 661             PUSH_DATA (push, (start << 30) | count);
 662             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
 663             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 664             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 665             PUSH_DATA (push, 0);
 666             break;
 667          }
 668          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 669          PUSH_DATA (push, 0);
 670
 671          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 672       }
 673    } else {
 674       const void *data = nv50->idxbuf.user_buffer;
 675
 676       while (instance_count--) {
 677          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 678          PUSH_DATA (push, prim);
 679          switch (index_size) {
 680          case 1:
 681             nv50_draw_elements_inline_u08(push, data, start, count);
 682             break;
 683          case 2:
 684             nv50_draw_elements_inline_u16(push, data, start, count);
 685             break;
 686          case 4:
 687             if (shorten)
 688                nv50_draw_elements_inline_u32_short(push, data, start, count);
 689             else
 690                nv50_draw_elements_inline_u32(push, data, start, count);
 691             break;
 692          default:
 693             assert(0);
 694             return;
 695          }
 696          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 697          PUSH_DATA (push, 0);
 698
 699          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 700       }
 701    }
 702 }
 703
 704 static void
 705 nva0_draw_stream_output(struct nv50_context *nv50,
 706                         const struct pipe_draw_info *info)
 707 {
 708    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 709    struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
 710    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
 711    unsigned num_instances = info->instance_count;
 712    unsigned mode = nv50_prim_gl(info->mode);
 713
 714    if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
 715       /* A proper implementation without waiting doesn't seem possible,
 716        * so don't bother.
 717        */
 718       NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
 719       return;
 720    }
 721
 722    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 723       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 724       PUSH_SPACE(push, 4);
 725       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 726       PUSH_DATA (push, 0);
 727       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 728       PUSH_DATA (push, 0);
 729    }
 730
 731    assert(num_instances);
 732    do {
 733       PUSH_SPACE(push, 8);
 734       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 735       PUSH_DATA (push, mode);
 736       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
 737       PUSH_DATA (push, 0);
 738       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
 739       PUSH_DATA (push, 0);
 740       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BYTES), 1);
 741       nv50_query_pushbuf_submit(push, so->pq, 0x4);
 742       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 743       PUSH_DATA (push, 0);
 744
 745       mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 746    } while (--num_instances);
 747 }
 748
 749 static void
 750 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
 751 {
 752    struct nv50_screen *screen = chan->user_priv;
 753
 754    nouveau_fence_update(&screen->base, true);
 755
 756    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true);
 757 }
 758
 759 void
 760 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 761 {
 762    struct nv50_context *nv50 = nv50_context(pipe);
 763    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 764    int i, s;
 765
 766    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
 767    nv50->vb_elt_first = info->min_index + info->index_bias;
 768    nv50->vb_elt_limit = info->max_index - info->min_index;
 769    nv50->instance_off = info->start_instance;
 770    nv50->instance_max = info->instance_count - 1;
 771
 772    /* For picking only a few vertices from a large user buffer, push is better,
 773     * if index count is larger and we expect repeated vertices, suggest upload.
 774     */
 775    nv50->vbo_push_hint = /* the 64 is heuristic */
 776       !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
 777
 778    if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) {
 779       if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
 780          nv50->dirty |= NV50_NEW_ARRAYS;
 781       else
 782       if (!nv50->vbo_fifo)
 783          nv50_update_user_vbufs(nv50);
 784    }
 785
 786    if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
 787       nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
 788
 789    nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
 790
 791    push->kick_notify = nv50_draw_vbo_kick_notify;
 792
 793    for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
 794       uint32_t valid = nv50->constbuf_valid[s];
 795
 796       while (valid && !nv50->cb_dirty) {
 797          const unsigned i = ffs(valid) - 1;
 798          struct pipe_resource *res;
 799
 800          valid &= ~(1 << i);
 801          if (nv50->constbuf[s][i].user)
 802             continue;
 803
 804          res = nv50->constbuf[s][i].u.buf;
 805          if (!res)
 806             continue;
 807
 808          if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
 809             nv50->cb_dirty = true;
 810       }
 811    }
 812
 813    /* If there are any coherent constbufs, flush the cache */
 814    if (nv50->cb_dirty) {
 815       BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
 816       PUSH_DATA (push, 0);
 817       nv50->cb_dirty = false;
 818    }
 819
 820    if (nv50->vbo_fifo) {
 821       nv50_push_vbo(nv50, info);
 822       push->kick_notify = nv50_default_kick_notify;
 823       nouveau_pushbuf_bufctx(push, NULL);
 824       return;
 825    }
 826
 827    if (nv50->state.instance_base != info->start_instance) {
 828       nv50->state.instance_base = info->start_instance;
 829       /* NOTE: this does not affect the shader input, should it ? */
 830       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
 831       PUSH_DATA (push, info->start_instance);
 832    }
 833
 834    for (i = 0; i < nv50->num_vtxbufs && !nv50->base.vbo_dirty; ++i) {
 835       if (!nv50->vtxbuf[i].buffer)
 836          continue;
 837       if (nv50->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
 838          nv50->base.vbo_dirty = true;
 839    }
 840
 841    if (!nv50->base.vbo_dirty && nv50->idxbuf.buffer &&
 842        nv50->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
 843       nv50->base.vbo_dirty = true;
 844
 845    if (nv50->base.vbo_dirty) {
 846       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 847       PUSH_DATA (push, 0);
 848       nv50->base.vbo_dirty = false;
 849    }
 850
 851    if (info->indexed) {
 852       bool shorten = info->max_index <= 65535;
 853
 854       if (info->primitive_restart != nv50->state.prim_restart) {
 855          if (info->primitive_restart) {
 856             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
 857             PUSH_DATA (push, 1);
 858             PUSH_DATA (push, info->restart_index);
 859
 860             if (info->restart_index > 65535)
 861                shorten = false;
 862          } else {
 863             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
 864             PUSH_DATA (push, 0);
 865          }
 866          nv50->state.prim_restart = info->primitive_restart;
 867       } else
 868       if (info->primitive_restart) {
 869          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
 870          PUSH_DATA (push, info->restart_index);
 871
 872          if (info->restart_index > 65535)
 873             shorten = false;
 874       }
 875
 876       nv50_draw_elements(nv50, shorten,
 877                          info->mode, info->start, info->count,
 878                          info->instance_count, info->index_bias);
 879    } else
 880    if (unlikely(info->count_from_stream_output)) {
 881       nva0_draw_stream_output(nv50, info);
 882    } else {
 883       nv50_draw_arrays(nv50,
 884                        info->mode, info->start, info->count,
 885                        info->instance_count);
 886    }
 887    push->kick_notify = nv50_default_kick_notify;
 888
 889    nv50_release_user_vbufs(nv50);
 890
 891    nouveau_pushbuf_bufctx(push, NULL);
 892 }