1 /*******************************************************************************
2 Copyright (c) 2016 NVIDIA Corporation
4 Permission is hereby granted, free of charge, to any person obtaining a copy
5 of this software and associated documentation files (the "Software"), to
6 deal in the Software without restriction, including without limitation the
7 rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
8 sell copies of the Software, and to permit persons to whom the Software is
9 furnished to do so, subject to the following conditions:
11 The above copyright notice and this permission notice shall be
12 included in all copies or substantial portions of the Software.
14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 DEALINGS IN THE SOFTWARE.
22 *******************************************************************************/
24 /* AUTO GENERATED FILE -- DO NOT EDIT */
26 #ifndef __CLA0C0QMD_H__
27 #define __CLA0C0QMD_H__
30 ** Queue Meta Data, Version 00_06
33 // The below C preprocessor definitions describe "multi-word" structures, where
34 // fields may have bit numbers beyond 32. For example, MW(127:96) means
35 // the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)"
36 // syntax is to distinguish from similar "X:Y" single-word definitions: the
37 // macros historically used for single-word definitions would fail with
38 // multi-word definitions.
40 // See nvmisc.h:DRF_VAL_MW() in the source code of the kernel
41 // interface layer of nvidia.ko for an example of how to manipulate
42 // these MW(X:Y) definitions.
44 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0)
45 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31)
46 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32)
47 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63)
48 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64)
49 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95)
50 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96)
51 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127)
52 #define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128)
53 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160)
54 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192)
55 #define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197)
56 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200)
57 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000
58 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001
59 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201)
60 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000
61 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001
62 #define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
63 #define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
64 #define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
65 #define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
66 #define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
67 #define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
68 #define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204)
69 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208)
70 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223)
71 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000
72 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001
73 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224)
74 #define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249)
75 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
76 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
77 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
78 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
79 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
80 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
81 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
82 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
83 #define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
84 #define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
85 #define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
86 #define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
87 #define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
88 #define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
89 #define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
90 #define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
91 #define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
92 #define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
93 #define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256)
94 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288)
95 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320)
96 #define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328)
97 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336)
98 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352)
99 #define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358)
100 #define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366)
101 #define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
102 #define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
103 #define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368)
104 #define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
105 #define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
106 #define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
107 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370)
108 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000
109 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001
110 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371)
111 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000
112 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001
113 #define NVA0C0_QMDV00_06_THROTTLED MW(372:372)
114 #define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000
115 #define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001
116 #define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376)
117 #define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377)
118 #define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378)
119 #define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000
120 #define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
121 #define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379)
122 #define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
123 #define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
124 #define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382)
125 #define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
126 #define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
127 #define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383)
128 #define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384)
129 #define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416)
130 #define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432)
131 #define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448)
132 #define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480)
133 #define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496)
134 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512)
135 #define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536)
136 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543)
137 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000
138 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001
139 #define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544)
140 #define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562)
141 #define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576)
142 #define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580)
143 #define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584)
144 #define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592)
145 #define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608)
146 #define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624)
147 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
148 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000
149 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001
150 #define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648)
151 #define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669)
152 #define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
153 #define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
154 #define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
155 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672)
156 #define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704)
157 #define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736)
158 #define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768)
159 #define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776)
160 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788)
161 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
162 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
163 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
164 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
165 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
166 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
167 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
168 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
169 #define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791)
170 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792)
171 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
172 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
173 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794)
174 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
175 #define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
176 #define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799)
177 #define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
178 #define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
179 #define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800)
180 #define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832)
181 #define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864)
182 #define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872)
183 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884)
184 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
185 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
186 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
187 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
188 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
189 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
190 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
191 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
192 #define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887)
193 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888)
194 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
195 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
196 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890)
197 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
198 #define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
199 #define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895)
200 #define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
201 #define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
202 #define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896)
203 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
204 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
205 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
206 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
207 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
208 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
209 #define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
210 #define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
211 #define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464)
212 #define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467)
213 #define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
214 #define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496)
215 #define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
216 #define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528)
217 #define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536)
218 #define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568)
219 #define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600)
220 #define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632)
221 #define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664)
222 #define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696)
223 #define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728)
224 #define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760)
225 #define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792)
226 #define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824)
227 #define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856)
228 #define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888)
229 #define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920)
230 #define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952)
231 #define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984)
232 #define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016)
236 ** Queue Meta Data, Version 01_06
239 #define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0)
240 #define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31)
241 #define NVA0C0_QMDV01_06_OUTER_GET MW(62:32)
242 #define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63)
243 #define NVA0C0_QMDV01_06_INNER_GET MW(94:64)
244 #define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95)
245 #define NVA0C0_QMDV01_06_INNER_PUT MW(126:96)
246 #define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127)
247 #define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128)
248 #define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160)
249 #define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192)
250 #define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198)
251 #define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200)
252 #define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000
253 #define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001
254 #define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201)
255 #define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
256 #define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
257 #define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
258 #define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
259 #define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
260 #define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
261 #define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
262 #define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
263 #define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204)
264 #define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
265 #define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
266 #define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205)
267 #define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208)
268 #define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223)
269 #define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000
270 #define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001
271 #define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224)
272 #define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249)
273 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
274 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
275 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
276 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
277 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
278 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
279 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
280 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
281 #define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
282 #define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
283 #define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
284 #define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
285 #define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
286 #define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
287 #define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
288 #define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
289 #define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
290 #define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
291 #define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256)
292 #define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
293 #define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
294 #define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328)
295 #define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
296 #define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352)
297 #define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
298 #define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366)
299 #define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
300 #define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
301 #define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
302 #define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
303 #define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
304 #define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368)
305 #define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
306 #define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
307 #define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
308 #define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370)
309 #define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
310 #define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
311 #define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
312 #define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
313 #define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
314 #define NVA0C0_QMDV01_06_THROTTLED MW(372:372)
315 #define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000
316 #define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001
317 #define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376)
318 #define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000
319 #define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001
320 #define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377)
321 #define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000
322 #define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001
323 #define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378)
324 #define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000
325 #define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
326 #define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379)
327 #define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
328 #define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
329 #define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382)
330 #define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
331 #define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
332 #define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383)
333 #define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000
334 #define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001
335 #define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384)
336 #define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416)
337 #define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432)
338 #define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448)
339 #define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480)
340 #define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496)
341 #define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512)
342 #define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536)
343 #define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543)
344 #define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000
345 #define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001
346 #define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544)
347 #define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562)
348 #define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576)
349 #define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580)
350 #define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584)
351 #define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592)
352 #define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608)
353 #define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624)
354 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
355 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000
356 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001
357 #define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648)
358 #define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669)
359 #define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
360 #define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
361 #define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
362 #define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672)
363 #define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704)
364 #define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736)
365 #define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768)
366 #define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776)
367 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788)
368 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
369 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
370 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
371 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
372 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
373 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
374 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
375 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
376 #define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791)
377 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792)
378 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
379 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
380 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794)
381 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
382 #define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
383 #define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799)
384 #define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
385 #define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
386 #define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800)
387 #define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832)
388 #define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864)
389 #define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872)
390 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884)
391 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
392 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
393 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
394 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
395 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
396 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
397 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
398 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
399 #define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887)
400 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888)
401 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
402 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
403 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890)
404 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
405 #define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
406 #define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895)
407 #define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
408 #define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
409 #define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896)
410 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
411 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
412 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
413 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
414 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
415 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
416 #define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
417 #define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
418 #define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464)
419 #define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467)
420 #define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
421 #define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496)
422 #define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
423 #define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528)
424 #define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536)
425 #define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567)
426 #define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568)
427 #define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599)
428 #define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600)
429 #define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607)
430 #define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610)
431 #define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618)
432 #define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632)
433 #define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664)
434 #define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696)
435 #define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728)
436 #define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760)
437 #define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792)
438 #define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824)
439 #define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856)
440 #define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888)
441 #define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920)
442 #define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952)
443 #define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984)
444 #define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016)
448 ** Queue Meta Data, Version 01_07
451 #define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0)
452 #define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31)
453 #define NVA0C0_QMDV01_07_OUTER_GET MW(62:32)
454 #define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63)
455 #define NVA0C0_QMDV01_07_INNER_GET MW(94:64)
456 #define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95)
457 #define NVA0C0_QMDV01_07_INNER_PUT MW(126:96)
458 #define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127)
459 #define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128)
460 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160)
461 #define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192)
462 #define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198)
463 #define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201)
464 #define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
465 #define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
466 #define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
467 #define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
468 #define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
469 #define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
470 #define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
471 #define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
472 #define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204)
473 #define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
474 #define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
475 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205)
476 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000
477 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001
478 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206)
479 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000
480 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001
481 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207)
482 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000
483 #define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001
484 #define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208)
485 #define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224)
486 #define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249)
487 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
488 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
489 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
490 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
491 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
492 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
493 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
494 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
495 #define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
496 #define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
497 #define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
498 #define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
499 #define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
500 #define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
501 #define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
502 #define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
503 #define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
504 #define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
505 #define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256)
506 #define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
507 #define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
508 #define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328)
509 #define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
510 #define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352)
511 #define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
512 #define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366)
513 #define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
514 #define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
515 #define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
516 #define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
517 #define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
518 #define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368)
519 #define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
520 #define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
521 #define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
522 #define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370)
523 #define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
524 #define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
525 #define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
526 #define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
527 #define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
528 #define NVA0C0_QMDV01_07_THROTTLED MW(372:372)
529 #define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000
530 #define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001
531 #define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376)
532 #define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000
533 #define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001
534 #define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377)
535 #define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000
536 #define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001
537 #define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378)
538 #define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000
539 #define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
540 #define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379)
541 #define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
542 #define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
543 #define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382)
544 #define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
545 #define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
546 #define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383)
547 #define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000
548 #define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001
549 #define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384)
550 #define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416)
551 #define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432)
552 #define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448)
553 #define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480)
554 #define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496)
555 #define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512)
556 #define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522)
557 #define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544)
558 #define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562)
559 #define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576)
560 #define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580)
561 #define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584)
562 #define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592)
563 #define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608)
564 #define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624)
565 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
566 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000
567 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001
568 #define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648)
569 #define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669)
570 #define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
571 #define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
572 #define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
573 #define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672)
574 #define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704)
575 #define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736)
576 #define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768)
577 #define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776)
578 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788)
579 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
580 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
581 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
582 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
583 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
584 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
585 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
586 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
587 #define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791)
588 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792)
589 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
590 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
591 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794)
592 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
593 #define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
594 #define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799)
595 #define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
596 #define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
597 #define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800)
598 #define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832)
599 #define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864)
600 #define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872)
601 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884)
602 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
603 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
604 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
605 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
606 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
607 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
608 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
609 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
610 #define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887)
611 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888)
612 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
613 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
614 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890)
615 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
616 #define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
617 #define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895)
618 #define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
619 #define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
620 #define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896)
621 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
622 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
623 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
624 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
625 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
626 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
627 #define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
628 #define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
629 #define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464)
630 #define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467)
631 #define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
632 #define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496)
633 #define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
634 #define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528)
635 #define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536)
636 #define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567)
637 #define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568)
638 #define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599)
639 #define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600)
640 #define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630)
641 #define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631)
642 #define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
643 #define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
644 #define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632)
645 #define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664)
646 #define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696)
647 #define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728)
648 #define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760)
649 #define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792)
650 #define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824)
651 #define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856)
652 #define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888)
653 #define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920)
654 #define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952)
655 #define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984)
656 #define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016)
660 #endif // #ifndef __CLA0C0QMD_H__
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