src/gallium/drivers/nouveau/nvc0/nvc0_compute.c

   1 /*
   2  * Copyright 2013 Nouveau Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christoph Bumiller, Samuel Pitoiset
  23  */
  24
  25 #include "nvc0/nvc0_context.h"
  26 #include "nvc0/nvc0_compute.h"
  27
  28 int
  29 nvc0_screen_compute_setup(struct nvc0_screen *screen,
  30                           struct nouveau_pushbuf *push)
  31 {
  32    struct nouveau_object *chan = screen->base.channel;
  33    struct nouveau_device *dev = screen->base.device;
  34    uint32_t obj_class;
  35    int ret;
  36    int i;
  37
  38    switch (dev->chipset & ~0xf) {
  39    case 0xc0:
  40    case 0xd0:
  41       /* In theory, GF110+ should also support NVC8_COMPUTE_CLASS but,
  42        * in practice, a ILLEGAL_CLASS dmesg fail appears when using it. */
  43       obj_class = NVC0_COMPUTE_CLASS;
  44       break;
  45    default:
  46       NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
  47       return -1;
  48    }
  49
  50    ret = nouveau_object_new(chan, 0xbeef90c0, obj_class, NULL, 0,
  51                             &screen->compute);
  52    if (ret) {
  53       NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
  54       return ret;
  55    }
  56
  57    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 0, 1 << 12, NULL,
  58                         &screen->parm);
  59    if (ret)
  60       return ret;
  61
  62    BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
  63    PUSH_DATA (push, screen->compute->oclass);
  64
  65    /* hardware limit */
  66    BEGIN_NVC0(push, NVC0_COMPUTE(MP_LIMIT), 1);
  67    PUSH_DATA (push, screen->mp_count);
  68    BEGIN_NVC0(push, NVC0_COMPUTE(CALL_LIMIT_LOG), 1);
  69    PUSH_DATA (push, 0xf);
  70
  71    BEGIN_NVC0(push, SUBC_COMPUTE(0x02a0), 1);
  72    PUSH_DATA (push, 0x8000);
  73
  74    /* global memory setup */
  75    BEGIN_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
  76    PUSH_DATA (push, 0);
  77    BEGIN_NIC0(push, NVC0_COMPUTE(GLOBAL_BASE), 0x100);
  78    for (i = 0; i <= 0xff; i++)
  79       PUSH_DATA (push, (0xc << 28) | (i << 16) | i);
  80    BEGIN_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
  81    PUSH_DATA (push, 1);
  82
  83    /* local memory and cstack setup */
  84    BEGIN_NVC0(push, NVC0_COMPUTE(TEMP_ADDRESS_HIGH), 2);
  85    PUSH_DATAh(push, screen->tls->offset);
  86    PUSH_DATA (push, screen->tls->offset);
  87    BEGIN_NVC0(push, NVC0_COMPUTE(TEMP_SIZE_HIGH), 2);
  88    PUSH_DATAh(push, screen->tls->size);
  89    PUSH_DATA (push, screen->tls->size);
  90    BEGIN_NVC0(push, NVC0_COMPUTE(WARP_TEMP_ALLOC), 1);
  91    PUSH_DATA (push, 0);
  92    BEGIN_NVC0(push, NVC0_COMPUTE(LOCAL_BASE), 1);
  93    PUSH_DATA (push, 1 << 24);
  94
  95    /* shared memory setup */
  96    BEGIN_NVC0(push, NVC0_COMPUTE(CACHE_SPLIT), 1);
  97    PUSH_DATA (push, NVC0_COMPUTE_CACHE_SPLIT_48K_SHARED_16K_L1);
  98    BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_BASE), 1);
  99    PUSH_DATA (push, 2 << 24);
 100    BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_SIZE), 1);
 101    PUSH_DATA (push, 0);
 102
 103    /* code segment setup */
 104    BEGIN_NVC0(push, NVC0_COMPUTE(CODE_ADDRESS_HIGH), 2);
 105    PUSH_DATAh(push, screen->text->offset);
 106    PUSH_DATA (push, screen->text->offset);
 107
 108    /* TODO: textures & samplers */
 109
 110    return 0;
 111 }
 112
 113 bool
 114 nvc0_compute_validate_program(struct nvc0_context *nvc0)
 115 {
 116    struct nvc0_program *prog = nvc0->compprog;
 117
 118    if (prog->mem)
 119       return true;
 120
 121    if (!prog->translated) {
 122       prog->translated = nvc0_program_translate(
 123          prog, nvc0->screen->base.device->chipset, &nvc0->base.debug);
 124       if (!prog->translated)
 125          return false;
 126    }
 127    if (unlikely(!prog->code_size))
 128       return false;
 129
 130    if (likely(prog->code_size)) {
 131       if (nvc0_program_upload_code(nvc0, prog)) {
 132          struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 133          BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1);
 134          PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CODE);
 135          return true;
 136       }
 137    }
 138    return false;
 139 }
 140
 141 static bool
 142 nvc0_compute_state_validate(struct nvc0_context *nvc0)
 143 {
 144    if (!nvc0_compute_validate_program(nvc0))
 145       return false;
 146
 147    /* TODO: textures, samplers, surfaces, global memory buffers */
 148
 149    nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, false);
 150
 151    nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_cp);
 152    if (unlikely(nouveau_pushbuf_validate(nvc0->base.pushbuf)))
 153       return false;
 154    if (unlikely(nvc0->state.flushed))
 155       nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
 156
 157    return true;
 158
 159 }
 160
 161 static void
 162 nvc0_compute_upload_input(struct nvc0_context *nvc0, const void *input)
 163 {
 164    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 165    struct nvc0_screen *screen = nvc0->screen;
 166    struct nvc0_program *cp = nvc0->compprog;
 167
 168    if (cp->parm_size) {
 169       BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3);
 170       PUSH_DATA (push, align(cp->parm_size, 0x100));
 171       PUSH_DATAh(push, screen->parm->offset);
 172       PUSH_DATA (push, screen->parm->offset);
 173       BEGIN_NVC0(push, NVC0_COMPUTE(CB_BIND), 1);
 174       PUSH_DATA (push, (0 << 8) | 1);
 175       /* NOTE: size is limited to 4 KiB, which is < NV04_PFIFO_MAX_PACKET_LEN */
 176       BEGIN_1IC0(push, NVC0_COMPUTE(CB_POS), 1 + cp->parm_size / 4);
 177       PUSH_DATA (push, 0);
 178       PUSH_DATAp(push, input, cp->parm_size / 4);
 179
 180       BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1);
 181       PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CB);
 182    }
 183 }
 184
 185 void
 186 nvc0_launch_grid(struct pipe_context *pipe,
 187                  const uint *block_layout, const uint *grid_layout,
 188                  uint32_t label,
 189                  const void *input)
 190 {
 191    struct nvc0_context *nvc0 = nvc0_context(pipe);
 192    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 193    struct nvc0_program *cp = nvc0->compprog;
 194    unsigned s, i;
 195    int ret;
 196
 197    ret = !nvc0_compute_state_validate(nvc0);
 198    if (ret)
 199       goto out;
 200
 201    nvc0_compute_upload_input(nvc0, input);
 202
 203    BEGIN_NVC0(push, NVC0_COMPUTE(CP_START_ID), 1);
 204    PUSH_DATA (push, nvc0_program_symbol_offset(cp, label));
 205
 206    BEGIN_NVC0(push, NVC0_COMPUTE(LOCAL_POS_ALLOC), 3);
 207    PUSH_DATA (push, align(cp->cp.lmem_size, 0x10));
 208    PUSH_DATA (push, 0);
 209    PUSH_DATA (push, 0x800); /* WARP_CSTACK_SIZE */
 210
 211    BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_SIZE), 3);
 212    PUSH_DATA (push, align(cp->cp.smem_size, 0x100));
 213    PUSH_DATA (push, block_layout[0] * block_layout[1] * block_layout[2]);
 214    PUSH_DATA (push, cp->num_barriers);
 215    BEGIN_NVC0(push, NVC0_COMPUTE(CP_GPR_ALLOC), 1);
 216    PUSH_DATA (push, cp->num_gprs);
 217
 218    /* grid/block setup */
 219    BEGIN_NVC0(push, NVC0_COMPUTE(GRIDDIM_YX), 2);
 220    PUSH_DATA (push, (grid_layout[1] << 16) | grid_layout[0]);
 221    PUSH_DATA (push, grid_layout[2]);
 222    BEGIN_NVC0(push, NVC0_COMPUTE(BLOCKDIM_YX), 2);
 223    PUSH_DATA (push, (block_layout[1] << 16) | block_layout[0]);
 224    PUSH_DATA (push, block_layout[2]);
 225
 226    /* launch preliminary setup */
 227    BEGIN_NVC0(push, NVC0_COMPUTE(GRIDID), 1);
 228    PUSH_DATA (push, 0x1);
 229    BEGIN_NVC0(push, SUBC_COMPUTE(0x036c), 1);
 230    PUSH_DATA (push, 0);
 231    BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1);
 232    PUSH_DATA (push, NVC0_COMPUTE_FLUSH_GLOBAL | NVC0_COMPUTE_FLUSH_UNK8);
 233
 234    /* kernel launching */
 235    BEGIN_NVC0(push, NVC0_COMPUTE(COMPUTE_BEGIN), 1);
 236    PUSH_DATA (push, 0);
 237    BEGIN_NVC0(push, SUBC_COMPUTE(0x0a08), 1);
 238    PUSH_DATA (push, 0);
 239    BEGIN_NVC0(push, NVC0_COMPUTE(LAUNCH), 1);
 240    PUSH_DATA (push, 0x1000);
 241    BEGIN_NVC0(push, NVC0_COMPUTE(COMPUTE_END), 1);
 242    PUSH_DATA (push, 0);
 243    BEGIN_NVC0(push, SUBC_COMPUTE(0x0360), 1);
 244    PUSH_DATA (push, 0x1);
 245
 246    /* rebind all the 3D constant buffers
 247     * (looks like binding a CB on COMPUTE clobbers 3D state) */
 248    nvc0->dirty |= NVC0_NEW_CONSTBUF;
 249    for (s = 0; s < 6; s++) {
 250       for (i = 0; i < NVC0_MAX_PIPE_CONSTBUFS; i++)
 251          if (nvc0->constbuf[s][i].u.buf)
 252             nvc0->constbuf_dirty[s] |= 1 << i;
 253    }
 254    memset(nvc0->state.uniform_buffer_bound, 0,
 255           sizeof(nvc0->state.uniform_buffer_bound));
 256
 257 out:
 258    if (ret)
 259       NOUVEAU_ERR("Failed to launch grid !\n");
 260 }