src/gallium/drivers/nouveau/nvc0/nvc0_compute.c

   1 /*
   2  * Copyright 2013 Nouveau Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christoph Bumiller, Samuel Pitoiset
  23  */
  24
  25 #include "nvc0/nvc0_context.h"
  26
  27 #include "nvc0/nvc0_compute.xml.h"
  28
  29 int
  30 nvc0_screen_compute_setup(struct nvc0_screen *screen,
  31                           struct nouveau_pushbuf *push)
  32 {
  33    struct nouveau_object *chan = screen->base.channel;
  34    struct nouveau_device *dev = screen->base.device;
  35    uint32_t obj_class;
  36    int ret;
  37    int i;
  38
  39    switch (dev->chipset & ~0xf) {
  40    case 0xc0:
  41    case 0xd0:
  42       /* In theory, GF110+ should also support NVC8_COMPUTE_CLASS but,
  43        * in practice, a ILLEGAL_CLASS dmesg fail appears when using it. */
  44       obj_class = NVC0_COMPUTE_CLASS;
  45       break;
  46    default:
  47       NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
  48       return -1;
  49    }
  50
  51    ret = nouveau_object_new(chan, 0xbeef90c0, obj_class, NULL, 0,
  52                             &screen->compute);
  53    if (ret) {
  54       NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
  55       return ret;
  56    }
  57
  58    BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
  59    PUSH_DATA (push, screen->compute->oclass);
  60
  61    /* hardware limit */
  62    BEGIN_NVC0(push, NVC0_CP(MP_LIMIT), 1);
  63    PUSH_DATA (push, screen->mp_count);
  64    BEGIN_NVC0(push, NVC0_CP(CALL_LIMIT_LOG), 1);
  65    PUSH_DATA (push, 0xf);
  66
  67    BEGIN_NVC0(push, SUBC_CP(0x02a0), 1);
  68    PUSH_DATA (push, 0x8000);
  69
  70    /* global memory setup */
  71    BEGIN_NVC0(push, SUBC_CP(0x02c4), 1);
  72    PUSH_DATA (push, 0);
  73    BEGIN_NIC0(push, NVC0_CP(GLOBAL_BASE), 0x100);
  74    for (i = 0; i <= 0xff; i++)
  75       PUSH_DATA (push, (0xc << 28) | (i << 16) | i);
  76    BEGIN_NVC0(push, SUBC_CP(0x02c4), 1);
  77    PUSH_DATA (push, 1);
  78
  79    /* local memory and cstack setup */
  80    BEGIN_NVC0(push, NVC0_CP(TEMP_ADDRESS_HIGH), 2);
  81    PUSH_DATAh(push, screen->tls->offset);
  82    PUSH_DATA (push, screen->tls->offset);
  83    BEGIN_NVC0(push, NVC0_CP(TEMP_SIZE_HIGH), 2);
  84    PUSH_DATAh(push, screen->tls->size);
  85    PUSH_DATA (push, screen->tls->size);
  86    BEGIN_NVC0(push, NVC0_CP(WARP_TEMP_ALLOC), 1);
  87    PUSH_DATA (push, 0);
  88    BEGIN_NVC0(push, NVC0_CP(LOCAL_BASE), 1);
  89    PUSH_DATA (push, 0xff << 24);
  90
  91    /* shared memory setup */
  92    BEGIN_NVC0(push, NVC0_CP(CACHE_SPLIT), 1);
  93    PUSH_DATA (push, NVC0_COMPUTE_CACHE_SPLIT_48K_SHARED_16K_L1);
  94    BEGIN_NVC0(push, NVC0_CP(SHARED_BASE), 1);
  95    PUSH_DATA (push, 0xfe << 24);
  96    BEGIN_NVC0(push, NVC0_CP(SHARED_SIZE), 1);
  97    PUSH_DATA (push, 0);
  98
  99    /* code segment setup */
 100    BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 101    PUSH_DATAh(push, screen->text->offset);
 102    PUSH_DATA (push, screen->text->offset);
 103
 104    /* textures */
 105    BEGIN_NVC0(push, NVC0_CP(TIC_ADDRESS_HIGH), 3);
 106    PUSH_DATAh(push, screen->txc->offset);
 107    PUSH_DATA (push, screen->txc->offset);
 108    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 109
 110    /* samplers */
 111    BEGIN_NVC0(push, NVC0_CP(TSC_ADDRESS_HIGH), 3);
 112    PUSH_DATAh(push, screen->txc->offset + 65536);
 113    PUSH_DATA (push, screen->txc->offset + 65536);
 114    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 115
 116    return 0;
 117 }
 118
 119 static void
 120 nvc0_compute_validate_samplers(struct nvc0_context *nvc0)
 121 {
 122    bool need_flush = nvc0_validate_tsc(nvc0, 5);
 123    if (need_flush) {
 124       BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(TSC_FLUSH), 1);
 125       PUSH_DATA (nvc0->base.pushbuf, 0);
 126    }
 127
 128    /* Invalidate all 3D samplers because they are aliased. */
 129    for (int s = 0; s < 5; s++)
 130       nvc0->samplers_dirty[s] = ~0;
 131    nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
 132 }
 133
 134 static void
 135 nvc0_compute_validate_textures(struct nvc0_context *nvc0)
 136 {
 137    bool need_flush = nvc0_validate_tic(nvc0, 5);
 138    if (need_flush) {
 139       BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(TIC_FLUSH), 1);
 140       PUSH_DATA (nvc0->base.pushbuf, 0);
 141    }
 142
 143    /* Invalidate all 3D textures because they are aliased. */
 144    for (int s = 0; s < 5; s++) {
 145       for (int i = 0; i < nvc0->num_textures[s]; i++)
 146          nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
 147       nvc0->textures_dirty[s] = ~0;
 148    }
 149    nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
 150 }
 151
 152 static inline void
 153 nvc0_compute_invalidate_constbufs(struct nvc0_context *nvc0)
 154 {
 155    int s;
 156
 157    /* Invalidate all 3D constbufs because they are aliased with COMPUTE. */
 158    for (s = 0; s < 5; s++) {
 159       nvc0->constbuf_dirty[s] |= nvc0->constbuf_valid[s];
 160       nvc0->state.uniform_buffer_bound[s] = 0;
 161    }
 162    nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
 163 }
 164
 165 static void
 166 nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
 167 {
 168    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 169    const int s = 5;
 170
 171    while (nvc0->constbuf_dirty[s]) {
 172       int i = ffs(nvc0->constbuf_dirty[s]) - 1;
 173       nvc0->constbuf_dirty[s] &= ~(1 << i);
 174
 175       if (nvc0->constbuf[s][i].user) {
 176          struct nouveau_bo *bo = nvc0->screen->uniform_bo;
 177          const unsigned base = NVC0_CB_USR_INFO(s);
 178          const unsigned size = nvc0->constbuf[s][0].size;
 179          assert(i == 0); /* we really only want OpenGL uniforms here */
 180          assert(nvc0->constbuf[s][0].u.data);
 181
 182          if (nvc0->state.uniform_buffer_bound[s] < size) {
 183             nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
 184
 185             BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
 186             PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
 187             PUSH_DATAh(push, bo->offset + base);
 188             PUSH_DATA (push, bo->offset + base);
 189             BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
 190             PUSH_DATA (push, (0 << 8) | 1);
 191          }
 192          nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
 193                          base, nvc0->state.uniform_buffer_bound[s],
 194                          0, (size + 3) / 4,
 195                          nvc0->constbuf[s][0].u.data);
 196       } else {
 197          struct nv04_resource *res =
 198             nv04_resource(nvc0->constbuf[s][i].u.buf);
 199          if (res) {
 200             BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
 201             PUSH_DATA (push, nvc0->constbuf[s][i].size);
 202             PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
 203             PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
 204             BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
 205             PUSH_DATA (push, (i << 8) | 1);
 206
 207             BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
 208
 209             res->cb_bindings[s] |= 1 << i;
 210          } else {
 211             BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
 212             PUSH_DATA (push, (i << 8) | 0);
 213          }
 214          if (i == 0)
 215             nvc0->state.uniform_buffer_bound[s] = 0;
 216       }
 217    }
 218
 219    nvc0_compute_invalidate_constbufs(nvc0);
 220
 221    BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
 222    PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CB);
 223 }
 224
 225 static void
 226 nvc0_compute_validate_driverconst(struct nvc0_context *nvc0)
 227 {
 228    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 229    struct nvc0_screen *screen = nvc0->screen;
 230
 231    BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
 232    PUSH_DATA (push, 2048);
 233    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
 234    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
 235    BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
 236    PUSH_DATA (push, (15 << 8) | 1);
 237
 238    nvc0->dirty_3d |= NVC0_NEW_3D_DRIVERCONST;
 239 }
 240
 241 static void
 242 nvc0_compute_validate_buffers(struct nvc0_context *nvc0)
 243 {
 244    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 245    struct nvc0_screen *screen = nvc0->screen;
 246    const int s = 5;
 247    int i;
 248
 249    BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
 250    PUSH_DATA (push, 2048);
 251    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
 252    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
 253    BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS);
 254    PUSH_DATA (push, NVC0_CB_AUX_BUF_INFO(0));
 255
 256    for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
 257       if (nvc0->buffers[s][i].buffer) {
 258          struct nv04_resource *res =
 259             nv04_resource(nvc0->buffers[s][i].buffer);
 260          PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
 261          PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
 262          PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
 263          PUSH_DATA (push, 0);
 264          BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR);
 265          util_range_add(&res->valid_buffer_range,
 266                         nvc0->buffers[s][i].buffer_offset,
 267                         nvc0->buffers[s][i].buffer_size);
 268       } else {
 269          PUSH_DATA (push, 0);
 270          PUSH_DATA (push, 0);
 271          PUSH_DATA (push, 0);
 272          PUSH_DATA (push, 0);
 273       }
 274    }
 275 }
 276
 277 void
 278 nvc0_compute_validate_globals(struct nvc0_context *nvc0)
 279 {
 280    unsigned i;
 281
 282    for (i = 0; i < nvc0->global_residents.size / sizeof(struct pipe_resource *);
 283         ++i) {
 284       struct pipe_resource *res = *util_dynarray_element(
 285          &nvc0->global_residents, struct pipe_resource *, i);
 286       if (res)
 287          nvc0_add_resident(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL,
 288                            nv04_resource(res), NOUVEAU_BO_RDWR);
 289    }
 290 }
 291
 292 static inline void
 293 nvc0_compute_invalidate_surfaces(struct nvc0_context *nvc0, const int s)
 294 {
 295    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 296    int i;
 297
 298    for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
 299       if (s == 5)
 300          BEGIN_NVC0(push, NVC0_CP(IMAGE(i)), 6);
 301       else
 302          BEGIN_NVC0(push, NVC0_3D(IMAGE(i)), 6);
 303       PUSH_DATA(push, 0);
 304       PUSH_DATA(push, 0);
 305       PUSH_DATA(push, 0);
 306       PUSH_DATA(push, 0);
 307       PUSH_DATA(push, 0x14000);
 308       PUSH_DATA(push, 0);
 309    }
 310 }
 311
 312 static void
 313 nvc0_compute_validate_surfaces(struct nvc0_context *nvc0)
 314 {
 315    /* TODO: Invalidating both 3D and CP surfaces before validating surfaces for
 316     * compute is probably not really necessary, but we didn't find any better
 317     * solutions for now. This fixes some invalidation issues when compute and
 318     * fragment shaders are used inside the same context. Anyway, we definitely
 319     * have invalidation issues between 3D and CP for other resources like SSBO
 320     * and atomic counters. */
 321    nvc0_compute_invalidate_surfaces(nvc0, 4);
 322    nvc0_compute_invalidate_surfaces(nvc0, 5);
 323
 324    nvc0_validate_suf(nvc0, 5);
 325
 326    /* Invalidate all FRAGMENT images because they are aliased with COMPUTE. */
 327    nvc0->dirty_3d |= NVC0_NEW_3D_SURFACES;
 328    nvc0->images_dirty[4] |= nvc0->images_valid[4];
 329 }
 330
 331 static struct nvc0_state_validate
 332 validate_list_cp[] = {
 333    { nvc0_compprog_validate,              NVC0_NEW_CP_PROGRAM     },
 334    { nvc0_compute_validate_constbufs,     NVC0_NEW_CP_CONSTBUF    },
 335    { nvc0_compute_validate_driverconst,   NVC0_NEW_CP_DRIVERCONST },
 336    { nvc0_compute_validate_buffers,       NVC0_NEW_CP_BUFFERS     },
 337    { nvc0_compute_validate_textures,      NVC0_NEW_CP_TEXTURES    },
 338    { nvc0_compute_validate_samplers,      NVC0_NEW_CP_SAMPLERS    },
 339    { nvc0_compute_validate_globals,       NVC0_NEW_CP_GLOBALS     },
 340    { nvc0_compute_validate_surfaces,      NVC0_NEW_CP_SURFACES    },
 341 };
 342
 343 static bool
 344 nvc0_state_validate_cp(struct nvc0_context *nvc0, uint32_t mask)
 345 {
 346    bool ret;
 347
 348    ret = nvc0_state_validate(nvc0, mask, validate_list_cp,
 349                              ARRAY_SIZE(validate_list_cp), &nvc0->dirty_cp,
 350                              nvc0->bufctx_cp);
 351
 352    if (unlikely(nvc0->state.flushed))
 353       nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, true);
 354    return ret;
 355 }
 356
 357 static void
 358 nvc0_compute_upload_input(struct nvc0_context *nvc0, const void *input)
 359 {
 360    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 361    struct nvc0_screen *screen = nvc0->screen;
 362    struct nvc0_program *cp = nvc0->compprog;
 363
 364    if (cp->parm_size) {
 365       struct nouveau_bo *bo = screen->uniform_bo;
 366       const unsigned base = NVC0_CB_USR_INFO(5);
 367
 368       BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
 369       PUSH_DATA (push, align(cp->parm_size, 0x100));
 370       PUSH_DATAh(push, bo->offset + base);
 371       PUSH_DATA (push, bo->offset + base);
 372       BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
 373       PUSH_DATA (push, (0 << 8) | 1);
 374       /* NOTE: size is limited to 4 KiB, which is < NV04_PFIFO_MAX_PACKET_LEN */
 375       BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + cp->parm_size / 4);
 376       PUSH_DATA (push, 0);
 377       PUSH_DATAp(push, input, cp->parm_size / 4);
 378
 379       nvc0_compute_invalidate_constbufs(nvc0);
 380
 381       BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
 382       PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CB);
 383    }
 384 }
 385
 386 void
 387 nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
 388 {
 389    struct nvc0_context *nvc0 = nvc0_context(pipe);
 390    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 391    struct nvc0_program *cp = nvc0->compprog;
 392    int ret;
 393
 394    ret = !nvc0_state_validate_cp(nvc0, ~0);
 395    if (ret) {
 396       NOUVEAU_ERR("Failed to launch grid !\n");
 397       return;
 398    }
 399
 400    nvc0_compute_upload_input(nvc0, info->input);
 401
 402    BEGIN_NVC0(push, NVC0_CP(CP_START_ID), 1);
 403    PUSH_DATA (push, nvc0_program_symbol_offset(cp, info->pc));
 404
 405    BEGIN_NVC0(push, NVC0_CP(LOCAL_POS_ALLOC), 3);
 406    PUSH_DATA (push, (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10));
 407    PUSH_DATA (push, 0);
 408    PUSH_DATA (push, 0x800); /* WARP_CSTACK_SIZE */
 409
 410    BEGIN_NVC0(push, NVC0_CP(SHARED_SIZE), 3);
 411    PUSH_DATA (push, align(cp->cp.smem_size, 0x100));
 412    PUSH_DATA (push, info->block[0] * info->block[1] * info->block[2]);
 413    PUSH_DATA (push, cp->num_barriers);
 414    BEGIN_NVC0(push, NVC0_CP(CP_GPR_ALLOC), 1);
 415    PUSH_DATA (push, cp->num_gprs);
 416
 417    /* launch preliminary setup */
 418    BEGIN_NVC0(push, NVC0_CP(GRIDID), 1);
 419    PUSH_DATA (push, 0x1);
 420    BEGIN_NVC0(push, SUBC_CP(0x036c), 1);
 421    PUSH_DATA (push, 0);
 422    BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
 423    PUSH_DATA (push, NVC0_COMPUTE_FLUSH_GLOBAL | NVC0_COMPUTE_FLUSH_UNK8);
 424
 425    /* block setup */
 426    BEGIN_NVC0(push, NVC0_CP(BLOCKDIM_YX), 2);
 427    PUSH_DATA (push, (info->block[1] << 16) | info->block[0]);
 428    PUSH_DATA (push, info->block[2]);
 429
 430    if (unlikely(info->indirect)) {
 431       struct nv04_resource *res = nv04_resource(info->indirect);
 432       uint32_t offset = res->offset + info->indirect_offset;
 433       unsigned macro = NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT;
 434
 435       nouveau_pushbuf_space(push, 16, 0, 1);
 436       PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
 437       PUSH_DATA(push, NVC0_FIFO_PKHDR_1I(1, macro, 3));
 438       nouveau_pushbuf_data(push, res->bo, offset,
 439                            NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
 440    } else {
 441       /* grid setup */
 442       BEGIN_NVC0(push, NVC0_CP(GRIDDIM_YX), 2);
 443       PUSH_DATA (push, (info->grid[1] << 16) | info->grid[0]);
 444       PUSH_DATA (push, info->grid[2]);
 445
 446       /* kernel launching */
 447       BEGIN_NVC0(push, NVC0_CP(COMPUTE_BEGIN), 1);
 448       PUSH_DATA (push, 0);
 449       BEGIN_NVC0(push, SUBC_CP(0x0a08), 1);
 450       PUSH_DATA (push, 0);
 451       BEGIN_NVC0(push, NVC0_CP(LAUNCH), 1);
 452       PUSH_DATA (push, 0x1000);
 453       BEGIN_NVC0(push, NVC0_CP(COMPUTE_END), 1);
 454       PUSH_DATA (push, 0);
 455       BEGIN_NVC0(push, SUBC_CP(0x0360), 1);
 456       PUSH_DATA (push, 0x1);
 457    }
 458
 459    /* TODO: Not sure if this is really necessary. */
 460    nvc0_compute_invalidate_surfaces(nvc0, 5);
 461 }