nvc0: add support for texture gather
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_compute.xml.h
1 #ifndef NVC0_COMPUTE_XML
2 #define NVC0_COMPUTE_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
9
10 The rules-ng-ng source files this header was generated from are:
11 - nvc0_compute.xml ( 11145 bytes, from 2013-04-27 14:00:13)
12 - copyright.xml ( 6452 bytes, from 2013-02-27 22:13:22)
13 - nvchipsets.xml ( 3954 bytes, from 2013-04-27 14:00:13)
14 - nv_object.xml ( 14395 bytes, from 2013-04-27 14:00:13)
15 - nv_defs.xml ( 4437 bytes, from 2013-02-27 22:13:22)
16 - nv50_defs.xml ( 16652 bytes, from 2013-06-20 13:45:33)
17
18 Copyright (C) 2006-2013 by the following authors:
19 - Artur Huillet <arthur.huillet@free.fr> (ahuillet)
20 - Ben Skeggs (darktama, darktama_)
21 - B. R. <koala_br@users.sourceforge.net> (koala_br)
22 - Carlos Martin <carlosmn@users.sf.net> (carlosmn)
23 - Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
24 - Dawid Gajownik <gajownik@users.sf.net> (gajownik)
25 - Dmitry Baryshkov
26 - Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
27 - EdB <edb_@users.sf.net> (edb_)
28 - Erik Waling <erikwailing@users.sf.net> (erikwaling)
29 - Francisco Jerez <currojerez@riseup.net> (curro)
30 - imirkin <imirkin@users.sf.net> (imirkin)
31 - jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
32 - Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
33 - Laurent Carlier <lordheavym@gmail.com> (lordheavy)
34 - Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
35 - Maarten Maathuis <madman2003@gmail.com> (stillunknown)
36 - Marcin Koƛcielnicki <koriakin@0x04.net> (mwk, koriakin)
37 - Mark Carey <mark.carey@gmail.com> (careym)
38 - Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
39 - nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
40 - Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
41 - Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
42 - Peter Popov <ironpeter@users.sf.net> (ironpeter)
43 - Richard Hughes <hughsient@users.sf.net> (hughsient)
44 - Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
45 - Serge Martin
46 - Simon Raffeiner
47 - Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
48 - Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
49 - sturmflut <sturmflut@users.sf.net> (sturmflut)
50 - Sylvain Munaut <tnt@246tNt.com>
51 - Victor Stinner <victor.stinner@haypocalc.com> (haypo)
52 - Wladmir van der Laan <laanwj@gmail.com> (miathan6)
53 - Younes Manton <younes.m@gmail.com> (ymanton)
54
55 Permission is hereby granted, free of charge, to any person obtaining
56 a copy of this software and associated documentation files (the
57 "Software"), to deal in the Software without restriction, including
58 without limitation the rights to use, copy, modify, merge, publish,
59 distribute, sublicense, and/or sell copies of the Software, and to
60 permit persons to whom the Software is furnished to do so, subject to
61 the following conditions:
62
63 The above copyright notice and this permission notice (including the
64 next paragraph) shall be included in all copies or substantial
65 portions of the Software.
66
67 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
68 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
69 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
70 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
71 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
72 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
73 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
74 */
75
76
77
78 #define NVC0_COMPUTE_LOCAL_POS_ALLOC 0x00000204
79
80 #define NVC0_COMPUTE_LOCAL_NEG_ALLOC 0x00000208
81
82 #define NVC0_COMPUTE_WARP_CSTACK_SIZE 0x0000020c
83
84 #define NVC0_COMPUTE_TEX_LIMITS 0x00000210
85 #define NVC0_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MASK 0x0000000f
86 #define NVC0_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__SHIFT 0
87 #define NVC0_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MIN 0x00000000
88 #define NVC0_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MAX 0x00000004
89 #define NVC0_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MASK 0x000000f0
90 #define NVC0_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__SHIFT 4
91 #define NVC0_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MIN 0x00000000
92 #define NVC0_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MAX 0x00000007
93
94 #define NVC0_COMPUTE_SHARED_BASE 0x00000214
95
96 #define NVC0_COMPUTE_MEM_BARRIER 0x0000021c
97 #define NVC0_COMPUTE_MEM_BARRIER_UNK0 0x00000001
98 #define NVC0_COMPUTE_MEM_BARRIER_UNK1 0x00000002
99 #define NVC0_COMPUTE_MEM_BARRIER_UNK2 0x00000004
100 #define NVC0_COMPUTE_MEM_BARRIER_UNK4 0x00000010
101 #define NVC0_COMPUTE_MEM_BARRIER_UNK8 0x00000100
102 #define NVC0_COMPUTE_MEM_BARRIER_UNK12 0x00001000
103
104 #define NVC0_COMPUTE_BIND_TSC 0x00000228
105 #define NVC0_COMPUTE_BIND_TSC_ACTIVE 0x00000001
106 #define NVC0_COMPUTE_BIND_TSC_SAMPLER__MASK 0x00000ff0
107 #define NVC0_COMPUTE_BIND_TSC_SAMPLER__SHIFT 4
108 #define NVC0_COMPUTE_BIND_TSC_TSC__MASK 0x01fff000
109 #define NVC0_COMPUTE_BIND_TSC_TSC__SHIFT 12
110
111 #define NVC0_COMPUTE_BIND_TIC 0x0000022c
112 #define NVC0_COMPUTE_BIND_TIC_ACTIVE 0x00000001
113 #define NVC0_COMPUTE_BIND_TIC_TEXTURE__MASK 0x000001fe
114 #define NVC0_COMPUTE_BIND_TIC_TEXTURE__SHIFT 1
115 #define NVC0_COMPUTE_BIND_TIC_TIC__MASK 0x7ffffe00
116 #define NVC0_COMPUTE_BIND_TIC_TIC__SHIFT 9
117
118 #define NVC0_COMPUTE_BIND_TSC2 0x00000230
119 #define NVC0_COMPUTE_BIND_TSC2_ACTIVE 0x00000001
120 #define NVC0_COMPUTE_BIND_TSC2_SAMPLER__MASK 0x00000010
121 #define NVC0_COMPUTE_BIND_TSC2_SAMPLER__SHIFT 4
122 #define NVC0_COMPUTE_BIND_TSC2_TSC__MASK 0x01fff000
123 #define NVC0_COMPUTE_BIND_TSC2_TSC__SHIFT 12
124
125 #define NVC0_COMPUTE_BIND_TIC2 0x00000234
126 #define NVC0_COMPUTE_BIND_TIC2_ACTIVE 0x00000001
127 #define NVC0_COMPUTE_BIND_TIC2_TEXTURE__MASK 0x00000002
128 #define NVC0_COMPUTE_BIND_TIC2_TEXTURE__SHIFT 1
129 #define NVC0_COMPUTE_BIND_TIC2_TIC__MASK 0x7ffffe00
130 #define NVC0_COMPUTE_BIND_TIC2_TIC__SHIFT 9
131
132 #define NVC0_COMPUTE_GRIDDIM_YX 0x00000238
133 #define NVC0_COMPUTE_GRIDDIM_YX_X__MASK 0x0000ffff
134 #define NVC0_COMPUTE_GRIDDIM_YX_X__SHIFT 0
135 #define NVC0_COMPUTE_GRIDDIM_YX_Y__MASK 0xffff0000
136 #define NVC0_COMPUTE_GRIDDIM_YX_Y__SHIFT 16
137
138 #define NVC0_COMPUTE_GRIDDIM_Z 0x0000023c
139
140 #define NVC0_COMPUTE_UNK244_TIC_FLUSH 0x00000244
141
142 #define NVC0_COMPUTE_SHARED_SIZE 0x0000024c
143
144 #define NVC0_COMPUTE_THREADS_ALLOC 0x00000250
145
146 #define NVC0_COMPUTE_BARRIER_ALLOC 0x00000254
147
148 #define NVC0_COMPUTE_UNK028C 0x0000028c
149
150 #define NVC0_COMPUTE_COMPUTE_BEGIN 0x0000029c
151 #define NVC0_COMPUTE_COMPUTE_BEGIN_UNK0 0x00000001
152
153 #define NVC0_COMPUTE_UNK02A0 0x000002a0
154
155 #define NVC0_COMPUTE_CP_GPR_ALLOC 0x000002c0
156
157 #define NVC0_COMPUTE_UNK02C4 0x000002c4
158
159 #define NVC0_COMPUTE_GLOBAL_BASE 0x000002c8
160 #define NVC0_COMPUTE_GLOBAL_BASE_HIGH__MASK 0x000000ff
161 #define NVC0_COMPUTE_GLOBAL_BASE_HIGH__SHIFT 0
162 #define NVC0_COMPUTE_GLOBAL_BASE_INDEX__MASK 0x00ff0000
163 #define NVC0_COMPUTE_GLOBAL_BASE_INDEX__SHIFT 16
164 #define NVC0_COMPUTE_GLOBAL_BASE_READ_OK 0x40000000
165 #define NVC0_COMPUTE_GLOBAL_BASE_WRITE_OK 0x80000000
166
167 #define NVC8_COMPUTE_UNK02E0 0x000002e0
168
169 #define NVC0_COMPUTE_CACHE_SPLIT 0x00000308
170 #define NVC0_COMPUTE_CACHE_SPLIT_16K_SHARED_48K_L1 0x00000001
171 #define NVC0_COMPUTE_CACHE_SPLIT_48K_SHARED_16K_L1 0x00000003
172
173 #define NVC0_COMPUTE_UNK030C 0x0000030c
174
175 #define NVC0_COMPUTE_UNK0360 0x00000360
176 #define NVC0_COMPUTE_UNK0360_UNK0 0x00000001
177 #define NVC0_COMPUTE_UNK0360_UNK8__MASK 0x00000300
178 #define NVC0_COMPUTE_UNK0360_UNK8__SHIFT 8
179 #define NVC8_COMPUTE_UNK0360_UNK10__MASK 0x00000c00
180 #define NVC8_COMPUTE_UNK0360_UNK10__SHIFT 10
181
182 #define NVC0_COMPUTE_LAUNCH 0x00000368
183
184 #define NVC0_COMPUTE_UNK036C 0x0000036c
185 #define NVC0_COMPUTE_UNK036C_UNK0__MASK 0x00000003
186 #define NVC0_COMPUTE_UNK036C_UNK0__SHIFT 0
187 #define NVC8_COMPUTE_UNK036C_UNK2__MASK 0x0000000c
188 #define NVC8_COMPUTE_UNK036C_UNK2__SHIFT 2
189
190 #define NVC0_COMPUTE_BLOCKDIM_YX 0x000003ac
191 #define NVC0_COMPUTE_BLOCKDIM_YX_X__MASK 0x0000ffff
192 #define NVC0_COMPUTE_BLOCKDIM_YX_X__SHIFT 0
193 #define NVC0_COMPUTE_BLOCKDIM_YX_Y__MASK 0xffff0000
194 #define NVC0_COMPUTE_BLOCKDIM_YX_Y__SHIFT 16
195
196 #define NVC0_COMPUTE_BLOCKDIM_Z 0x000003b0
197
198 #define NVC0_COMPUTE_CP_START_ID 0x000003b4
199
200 #define NVC0_COMPUTE_FIRMWARE(i0) (0x00000500 + 0x4*(i0))
201 #define NVC0_COMPUTE_FIRMWARE__ESIZE 0x00000004
202 #define NVC0_COMPUTE_FIRMWARE__LEN 0x00000020
203
204 #define NVC0_COMPUTE_MP_LIMIT 0x00000758
205
206 #define NVC0_COMPUTE_LOCAL_BASE 0x0000077c
207
208 #define NVC0_COMPUTE_GRIDID 0x00000780
209
210 #define NVC0_COMPUTE_TEMP_ADDRESS_HIGH 0x00000790
211
212 #define NVC0_COMPUTE_TEMP_ADDRESS_LOW 0x00000794
213
214 #define NVC0_COMPUTE_TEMP_SIZE_HIGH 0x00000798
215
216 #define NVC0_COMPUTE_TEMP_SIZE_LOW 0x0000079c
217
218 #define NVC0_COMPUTE_WARP_TEMP_ALLOC 0x000007a0
219
220 #define NVC0_COMPUTE_COMPUTE_END 0x00000a04
221 #define NVC0_COMPUTE_COMPUTE_END_UNK0 0x00000001
222
223 #define NVC0_COMPUTE_UNK0A08 0x00000a08
224
225 #define NVC0_COMPUTE_CALL_LIMIT_LOG 0x00000d64
226
227 #define NVC0_COMPUTE_UNK0D94 0x00000d94
228
229 #define NVC0_COMPUTE_WATCHDOG_TIMER 0x00000de4
230
231 #define NVC0_COMPUTE_UNK10F4 0x000010f4
232 #define NVC0_COMPUTE_UNK10F4_UNK0 0x00000001
233 #define NVC0_COMPUTE_UNK10F4_UNK4 0x00000010
234 #define NVC0_COMPUTE_UNK10F4_UNK8 0x00000100
235
236 #define NVC0_COMPUTE_LINKED_TSC 0x00001234
237
238 #define NVC0_COMPUTE_UNK1288_TIC_FLUSH 0x00001288
239
240 #define NVC0_COMPUTE_UNK12AC 0x000012ac
241
242 #define NVC0_COMPUTE_TSC_FLUSH 0x00001330
243 #define NVC0_COMPUTE_TSC_FLUSH_SPECIFIC 0x00000001
244 #define NVC0_COMPUTE_TSC_FLUSH_ENTRY__MASK 0x03fffff0
245 #define NVC0_COMPUTE_TSC_FLUSH_ENTRY__SHIFT 4
246
247 #define NVC0_COMPUTE_TIC_FLUSH 0x00001334
248 #define NVC0_COMPUTE_TIC_FLUSH_SPECIFIC 0x00000001
249 #define NVC0_COMPUTE_TIC_FLUSH_ENTRY__MASK 0x03fffff0
250 #define NVC0_COMPUTE_TIC_FLUSH_ENTRY__SHIFT 4
251
252 #define NVC0_COMPUTE_TEX_CACHE_CTL 0x00001338
253 #define NVC0_COMPUTE_TEX_CACHE_CTL_UNK0__MASK 0x00000007
254 #define NVC0_COMPUTE_TEX_CACHE_CTL_UNK0__SHIFT 0
255 #define NVC0_COMPUTE_TEX_CACHE_CTL_ENTRY__MASK 0x03fffff0
256 #define NVC0_COMPUTE_TEX_CACHE_CTL_ENTRY__SHIFT 4
257
258 #define NVC0_COMPUTE_UNK1354 0x00001354
259
260 #define NVC0_COMPUTE_UNK1424_TSC_FLUSH 0x00001424
261
262 #define NVC0_COMPUTE_COND_ADDRESS_HIGH 0x00001550
263
264 #define NVC0_COMPUTE_COND_ADDRESS_LOW 0x00001554
265
266 #define NVC0_COMPUTE_COND_MODE 0x00001558
267 #define NVC0_COMPUTE_COND_MODE_NEVER 0x00000000
268 #define NVC0_COMPUTE_COND_MODE_ALWAYS 0x00000001
269 #define NVC0_COMPUTE_COND_MODE_RES_NON_ZERO 0x00000002
270 #define NVC0_COMPUTE_COND_MODE_EQUAL 0x00000003
271 #define NVC0_COMPUTE_COND_MODE_NOT_EQUAL 0x00000004
272
273 #define NVC0_COMPUTE_TSC_ADDRESS_HIGH 0x0000155c
274
275 #define NVC0_COMPUTE_TSC_ADDRESS_LOW 0x00001560
276
277 #define NVC0_COMPUTE_TSC_LIMIT 0x00001564
278
279 #define NVC0_COMPUTE_TIC_ADDRESS_HIGH 0x00001574
280
281 #define NVC0_COMPUTE_TIC_ADDRESS_LOW 0x00001578
282
283 #define NVC0_COMPUTE_TIC_LIMIT 0x0000157c
284
285 #define NVC0_COMPUTE_CODE_ADDRESS_HIGH 0x00001608
286
287 #define NVC0_COMPUTE_CODE_ADDRESS_LOW 0x0000160c
288
289 #define NVC0_COMPUTE_TEX_MISC 0x00001664
290 #define NVC0_COMPUTE_TEX_MISC_UNK 0x00000001
291 #define NVC0_COMPUTE_TEX_MISC_SEAMLESS_CUBE_MAP 0x00000002
292
293 #define NVC0_COMPUTE_UNK1690 0x00001690
294 #define NVC0_COMPUTE_UNK1690_ALWAYS_DERIV 0x00000001
295 #define NVC0_COMPUTE_UNK1690_UNK16 0x00010000
296
297 #define NVC0_COMPUTE_CB_BIND 0x00001694
298 #define NVC0_COMPUTE_CB_BIND_VALID 0x00000001
299 #define NVC0_COMPUTE_CB_BIND_INDEX__MASK 0x00001f00
300 #define NVC0_COMPUTE_CB_BIND_INDEX__SHIFT 8
301
302 #define NVC0_COMPUTE_FLUSH 0x00001698
303 #define NVC0_COMPUTE_FLUSH_CODE 0x00000001
304 #define NVC0_COMPUTE_FLUSH_GLOBAL 0x00000010
305 #define NVC0_COMPUTE_FLUSH_UNK8 0x00000100
306 #define NVC0_COMPUTE_FLUSH_CB 0x00001000
307
308 #define NVC0_COMPUTE_UNK1930 0x00001930
309
310 #define NVC0_COMPUTE_UNK1944 0x00001944
311
312 #define NVC0_COMPUTE_DELAY 0x00001a24
313
314 #define NVC0_COMPUTE_UNK1A2C(i0) (0x00001a2c + 0x4*(i0))
315 #define NVC0_COMPUTE_UNK1A2C__ESIZE 0x00000004
316 #define NVC0_COMPUTE_UNK1A2C__LEN 0x00000005
317
318 #define NVC0_COMPUTE_QUERY_ADDRESS_HIGH 0x00001b00
319
320 #define NVC0_COMPUTE_QUERY_ADDRESS_LOW 0x00001b04
321
322 #define NVC0_COMPUTE_QUERY_SEQUENCE 0x00001b08
323
324 #define NVC0_COMPUTE_QUERY_GET 0x00001b0c
325 #define NVC0_COMPUTE_QUERY_GET_MODE__MASK 0x00000003
326 #define NVC0_COMPUTE_QUERY_GET_MODE__SHIFT 0
327 #define NVC0_COMPUTE_QUERY_GET_MODE_WRITE 0x00000000
328 #define NVC0_COMPUTE_QUERY_GET_MODE_WRITE_INTR_NRHOST 0x00000003
329 #define NVC0_COMPUTE_QUERY_GET_INTR 0x00100000
330 #define NVC0_COMPUTE_QUERY_GET_SHORT 0x10000000
331
332 #define NVC0_COMPUTE_CB_SIZE 0x00002380
333
334 #define NVC0_COMPUTE_CB_ADDRESS_HIGH 0x00002384
335
336 #define NVC0_COMPUTE_CB_ADDRESS_LOW 0x00002388
337
338 #define NVC0_COMPUTE_CB_POS 0x0000238c
339
340 #define NVC0_COMPUTE_CB_DATA(i0) (0x00002390 + 0x4*(i0))
341 #define NVC0_COMPUTE_CB_DATA__ESIZE 0x00000004
342 #define NVC0_COMPUTE_CB_DATA__LEN 0x00000010
343
344 #define NVC0_COMPUTE_IMAGE(i0) (0x00002700 + 0x20*(i0))
345 #define NVC0_COMPUTE_IMAGE__ESIZE 0x00000020
346 #define NVC0_COMPUTE_IMAGE__LEN 0x00000008
347
348 #define NVC0_COMPUTE_IMAGE_ADDRESS_HIGH(i0) (0x00002700 + 0x20*(i0))
349
350 #define NVC0_COMPUTE_IMAGE_ADDRESS_LOW(i0) (0x00002704 + 0x20*(i0))
351
352 #define NVC0_COMPUTE_IMAGE_WIDTH(i0) (0x00002708 + 0x20*(i0))
353
354 #define NVC0_COMPUTE_IMAGE_HEIGHT(i0) (0x0000270c + 0x20*(i0))
355 #define NVC0_COMPUTE_IMAGE_HEIGHT_HEIGHT__MASK 0x0000ffff
356 #define NVC0_COMPUTE_IMAGE_HEIGHT_HEIGHT__SHIFT 0
357 #define NVC0_COMPUTE_IMAGE_HEIGHT_UNK16 0x00010000
358 #define NVC0_COMPUTE_IMAGE_HEIGHT_LINEAR 0x00100000
359
360 #define NVC0_COMPUTE_IMAGE_FORMAT(i0) (0x00002710 + 0x20*(i0))
361 #define NVC0_COMPUTE_IMAGE_FORMAT_UNK0 0x00000001
362 #define NVC0_COMPUTE_IMAGE_FORMAT_FORMAT_COLOR__MASK 0x00000ff0
363 #define NVC0_COMPUTE_IMAGE_FORMAT_FORMAT_COLOR__SHIFT 4
364 #define NVC0_COMPUTE_IMAGE_FORMAT_FORMAT_ZETA__MASK 0x0001f000
365 #define NVC0_COMPUTE_IMAGE_FORMAT_FORMAT_ZETA__SHIFT 12
366
367 #define NVC0_COMPUTE_IMAGE_TILE_MODE(i0) (0x00002714 + 0x20*(i0))
368
369 #define NVC0_COMPUTE_MP_PM_SET(i0) (0x0000335c + 0x4*(i0))
370 #define NVC0_COMPUTE_MP_PM_SET__ESIZE 0x00000004
371 #define NVC0_COMPUTE_MP_PM_SET__LEN 0x00000008
372
373 #define NVC0_COMPUTE_MP_PM_SIGSEL(i0) (0x0000337c + 0x4*(i0))
374 #define NVC0_COMPUTE_MP_PM_SIGSEL__ESIZE 0x00000004
375 #define NVC0_COMPUTE_MP_PM_SIGSEL__LEN 0x00000008
376
377 #define NVC0_COMPUTE_MP_PM_SRCSEL(i0) (0x0000339c + 0x4*(i0))
378 #define NVC0_COMPUTE_MP_PM_SRCSEL__ESIZE 0x00000004
379 #define NVC0_COMPUTE_MP_PM_SRCSEL__LEN 0x00000008
380 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP0__MASK 0x00000007
381 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP0__SHIFT 0
382 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG0__MASK 0x00000070
383 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG0__SHIFT 4
384 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP1__MASK 0x00000700
385 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP1__SHIFT 8
386 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG1__MASK 0x00007000
387 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG1__SHIFT 12
388 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP2__MASK 0x00070000
389 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP2__SHIFT 16
390 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG2__MASK 0x00700000
391 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG2__SHIFT 20
392 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP3__MASK 0x07000000
393 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP3__SHIFT 24
394 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG3__MASK 0x70000000
395 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG3__SHIFT 28
396
397 #define NVC0_COMPUTE_MP_PM_OP(i0) (0x000033bc + 0x4*(i0))
398 #define NVC0_COMPUTE_MP_PM_OP__ESIZE 0x00000004
399 #define NVC0_COMPUTE_MP_PM_OP__LEN 0x00000008
400 #define NVC0_COMPUTE_MP_PM_OP_MODE__MASK 0x00000001
401 #define NVC0_COMPUTE_MP_PM_OP_MODE__SHIFT 0
402 #define NVC0_COMPUTE_MP_PM_OP_MODE_LOGOP 0x00000000
403 #define NVC0_COMPUTE_MP_PM_OP_MODE_LOGOP_PULSE 0x00000001
404 #define NVC0_COMPUTE_MP_PM_OP_FUNC__MASK 0x000ffff0
405 #define NVC0_COMPUTE_MP_PM_OP_FUNC__SHIFT 4
406
407 #define NVC0_COMPUTE_MP_PM_UNK33DC 0x000033dc
408
409
410 #endif /* NVC0_COMPUTE_XML */