nvc0/cl: hande 64 bit pointers in nvc0_set_global_handle
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_compute.xml.h
1 #ifndef NVC0_COMPUTE_XML
2 #define NVC0_COMPUTE_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/envytools/envytools/
8 git clone https://github.com/envytools/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - rnndb/graph/gf100_compute.xml ( 11143 bytes, from 2014-09-25 06:32:11)
12 - rnndb/copyright.xml ( 6456 bytes, from 2014-12-31 02:13:31)
13 - rnndb/nvchipsets.xml ( 2759 bytes, from 2014-10-05 01:51:02)
14 - rnndb/fifo/nv_object.xml ( 15326 bytes, from 2014-09-25 06:32:11)
15 - rnndb/g80_defs.xml ( 18175 bytes, from 2014-09-25 06:32:11)
16
17 Copyright (C) 2006-2014 by the following authors:
18 - Artur Huillet <arthur.huillet@free.fr> (ahuillet)
19 - Ben Skeggs (darktama, darktama_)
20 - B. R. <koala_br@users.sourceforge.net> (koala_br)
21 - Carlos Martin <carlosmn@users.sf.net> (carlosmn)
22 - Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
23 - Dawid Gajownik <gajownik@users.sf.net> (gajownik)
24 - Dmitry Baryshkov
25 - Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
26 - EdB <edb_@users.sf.net> (edb_)
27 - Erik Waling <erikwailing@users.sf.net> (erikwaling)
28 - Francisco Jerez <currojerez@riseup.net> (curro)
29 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
30 - jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
31 - Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
32 - Laurent Carlier <lordheavym@gmail.com> (lordheavy)
33 - Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
34 - Maarten Maathuis <madman2003@gmail.com> (stillunknown)
35 - Marcin Koƛcielnicki <koriakin@0x04.net> (mwk, koriakin)
36 - Mark Carey <mark.carey@gmail.com> (careym)
37 - Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
38 - nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
39 - Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
40 - Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
41 - Peter Popov <ironpeter@users.sf.net> (ironpeter)
42 - Richard Hughes <hughsient@users.sf.net> (hughsient)
43 - Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
44 - Serge Martin
45 - Simon Raffeiner
46 - Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
47 - Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
48 - sturmflut <sturmflut@users.sf.net> (sturmflut)
49 - Sylvain Munaut <tnt@246tNt.com>
50 - Victor Stinner <victor.stinner@haypocalc.com> (haypo)
51 - Wladmir van der Laan <laanwj@gmail.com> (miathan6)
52 - Younes Manton <younes.m@gmail.com> (ymanton)
53
54 Permission is hereby granted, free of charge, to any person obtaining
55 a copy of this software and associated documentation files (the
56 "Software"), to deal in the Software without restriction, including
57 without limitation the rights to use, copy, modify, merge, publish,
58 distribute, sublicense, and/or sell copies of the Software, and to
59 permit persons to whom the Software is furnished to do so, subject to
60 the following conditions:
61
62 The above copyright notice and this permission notice (including the
63 next paragraph) shall be included in all copies or substantial
64 portions of the Software.
65
66 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
67 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
68 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
69 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
70 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
71 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
72 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
73 */
74
75
76
77 #define NVC0_COMPUTE_LOCAL_POS_ALLOC 0x00000204
78
79 #define NVC0_COMPUTE_LOCAL_NEG_ALLOC 0x00000208
80
81 #define NVC0_COMPUTE_WARP_CSTACK_SIZE 0x0000020c
82
83 #define NVC0_COMPUTE_TEX_LIMITS 0x00000210
84 #define NVC0_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MASK 0x0000000f
85 #define NVC0_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__SHIFT 0
86 #define NVC0_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MIN 0x00000000
87 #define NVC0_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2__MAX 0x00000004
88 #define NVC0_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MASK 0x000000f0
89 #define NVC0_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__SHIFT 4
90 #define NVC0_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MIN 0x00000000
91 #define NVC0_COMPUTE_TEX_LIMITS_TEXTURES_LOG2__MAX 0x00000007
92
93 #define NVC0_COMPUTE_SHARED_BASE 0x00000214
94
95 #define NVC0_COMPUTE_MEM_BARRIER 0x0000021c
96 #define NVC0_COMPUTE_MEM_BARRIER_UNK0 0x00000001
97 #define NVC0_COMPUTE_MEM_BARRIER_UNK1 0x00000002
98 #define NVC0_COMPUTE_MEM_BARRIER_UNK2 0x00000004
99 #define NVC0_COMPUTE_MEM_BARRIER_UNK4 0x00000010
100 #define NVC0_COMPUTE_MEM_BARRIER_UNK8 0x00000100
101 #define NVC0_COMPUTE_MEM_BARRIER_UNK12 0x00001000
102
103 #define NVC0_COMPUTE_BIND_TSC 0x00000228
104 #define NVC0_COMPUTE_BIND_TSC_ACTIVE 0x00000001
105 #define NVC0_COMPUTE_BIND_TSC_SAMPLER__MASK 0x00000ff0
106 #define NVC0_COMPUTE_BIND_TSC_SAMPLER__SHIFT 4
107 #define NVC0_COMPUTE_BIND_TSC_TSC__MASK 0x01fff000
108 #define NVC0_COMPUTE_BIND_TSC_TSC__SHIFT 12
109
110 #define NVC0_COMPUTE_BIND_TIC 0x0000022c
111 #define NVC0_COMPUTE_BIND_TIC_ACTIVE 0x00000001
112 #define NVC0_COMPUTE_BIND_TIC_TEXTURE__MASK 0x000001fe
113 #define NVC0_COMPUTE_BIND_TIC_TEXTURE__SHIFT 1
114 #define NVC0_COMPUTE_BIND_TIC_TIC__MASK 0x7ffffe00
115 #define NVC0_COMPUTE_BIND_TIC_TIC__SHIFT 9
116
117 #define NVC0_COMPUTE_BIND_TSC2 0x00000230
118 #define NVC0_COMPUTE_BIND_TSC2_ACTIVE 0x00000001
119 #define NVC0_COMPUTE_BIND_TSC2_SAMPLER__MASK 0x00000010
120 #define NVC0_COMPUTE_BIND_TSC2_SAMPLER__SHIFT 4
121 #define NVC0_COMPUTE_BIND_TSC2_TSC__MASK 0x01fff000
122 #define NVC0_COMPUTE_BIND_TSC2_TSC__SHIFT 12
123
124 #define NVC0_COMPUTE_BIND_TIC2 0x00000234
125 #define NVC0_COMPUTE_BIND_TIC2_ACTIVE 0x00000001
126 #define NVC0_COMPUTE_BIND_TIC2_TEXTURE__MASK 0x00000002
127 #define NVC0_COMPUTE_BIND_TIC2_TEXTURE__SHIFT 1
128 #define NVC0_COMPUTE_BIND_TIC2_TIC__MASK 0x7ffffe00
129 #define NVC0_COMPUTE_BIND_TIC2_TIC__SHIFT 9
130
131 #define NVC0_COMPUTE_GRIDDIM_YX 0x00000238
132 #define NVC0_COMPUTE_GRIDDIM_YX_X__MASK 0x0000ffff
133 #define NVC0_COMPUTE_GRIDDIM_YX_X__SHIFT 0
134 #define NVC0_COMPUTE_GRIDDIM_YX_Y__MASK 0xffff0000
135 #define NVC0_COMPUTE_GRIDDIM_YX_Y__SHIFT 16
136
137 #define NVC0_COMPUTE_GRIDDIM_Z 0x0000023c
138
139 #define NVC0_COMPUTE_UNK244_TIC_FLUSH 0x00000244
140
141 #define NVC0_COMPUTE_SHARED_SIZE 0x0000024c
142
143 #define NVC0_COMPUTE_THREADS_ALLOC 0x00000250
144
145 #define NVC0_COMPUTE_BARRIER_ALLOC 0x00000254
146
147 #define NVC0_COMPUTE_UNK028C 0x0000028c
148
149 #define NVC0_COMPUTE_COMPUTE_BEGIN 0x0000029c
150 #define NVC0_COMPUTE_COMPUTE_BEGIN_UNK0 0x00000001
151
152 #define NVC0_COMPUTE_UNK02A0 0x000002a0
153
154 #define NVC0_COMPUTE_CP_GPR_ALLOC 0x000002c0
155
156 #define NVC0_COMPUTE_UNK02C4 0x000002c4
157
158 #define NVC0_COMPUTE_GLOBAL_BASE 0x000002c8
159 #define NVC0_COMPUTE_GLOBAL_BASE_HIGH__MASK 0x000000ff
160 #define NVC0_COMPUTE_GLOBAL_BASE_HIGH__SHIFT 0
161 #define NVC0_COMPUTE_GLOBAL_BASE_INDEX__MASK 0x00ff0000
162 #define NVC0_COMPUTE_GLOBAL_BASE_INDEX__SHIFT 16
163 #define NVC0_COMPUTE_GLOBAL_BASE_READ_OK 0x40000000
164 #define NVC0_COMPUTE_GLOBAL_BASE_WRITE_OK 0x80000000
165
166 #define NVC8_COMPUTE_UNK02E0 0x000002e0
167
168 #define NVC0_COMPUTE_CACHE_SPLIT 0x00000308
169 #define NVC0_COMPUTE_CACHE_SPLIT_16K_SHARED_48K_L1 0x00000001
170 #define NVC0_COMPUTE_CACHE_SPLIT_48K_SHARED_16K_L1 0x00000003
171
172 #define NVC0_COMPUTE_UNK030C 0x0000030c
173
174 #define NVC0_COMPUTE_UNK0360 0x00000360
175 #define NVC0_COMPUTE_UNK0360_UNK0 0x00000001
176 #define NVC0_COMPUTE_UNK0360_UNK8__MASK 0x00000300
177 #define NVC0_COMPUTE_UNK0360_UNK8__SHIFT 8
178 #define NVC8_COMPUTE_UNK0360_UNK10__MASK 0x00000c00
179 #define NVC8_COMPUTE_UNK0360_UNK10__SHIFT 10
180
181 #define NVC0_COMPUTE_LAUNCH 0x00000368
182
183 #define NVC0_COMPUTE_UNK036C 0x0000036c
184 #define NVC0_COMPUTE_UNK036C_UNK0__MASK 0x00000003
185 #define NVC0_COMPUTE_UNK036C_UNK0__SHIFT 0
186 #define NVC8_COMPUTE_UNK036C_UNK2__MASK 0x0000000c
187 #define NVC8_COMPUTE_UNK036C_UNK2__SHIFT 2
188
189 #define NVC0_COMPUTE_BLOCKDIM_YX 0x000003ac
190 #define NVC0_COMPUTE_BLOCKDIM_YX_X__MASK 0x0000ffff
191 #define NVC0_COMPUTE_BLOCKDIM_YX_X__SHIFT 0
192 #define NVC0_COMPUTE_BLOCKDIM_YX_Y__MASK 0xffff0000
193 #define NVC0_COMPUTE_BLOCKDIM_YX_Y__SHIFT 16
194
195 #define NVC0_COMPUTE_BLOCKDIM_Z 0x000003b0
196
197 #define NVC0_COMPUTE_CP_START_ID 0x000003b4
198
199 #define NVC0_COMPUTE_FIRMWARE(i0) (0x00000500 + 0x4*(i0))
200 #define NVC0_COMPUTE_FIRMWARE__ESIZE 0x00000004
201 #define NVC0_COMPUTE_FIRMWARE__LEN 0x00000020
202
203 #define NVC0_COMPUTE_MP_LIMIT 0x00000758
204
205 #define NVC0_COMPUTE_LOCAL_BASE 0x0000077c
206
207 #define NVC0_COMPUTE_GRIDID 0x00000780
208
209 #define NVC0_COMPUTE_TEMP_ADDRESS_HIGH 0x00000790
210
211 #define NVC0_COMPUTE_TEMP_ADDRESS_LOW 0x00000794
212
213 #define NVC0_COMPUTE_TEMP_SIZE_HIGH 0x00000798
214
215 #define NVC0_COMPUTE_TEMP_SIZE_LOW 0x0000079c
216
217 #define NVC0_COMPUTE_WARP_TEMP_ALLOC 0x000007a0
218
219 #define NVC0_COMPUTE_COMPUTE_END 0x00000a04
220 #define NVC0_COMPUTE_COMPUTE_END_UNK0 0x00000001
221
222 #define NVC0_COMPUTE_UNK0A08 0x00000a08
223
224 #define NVC0_COMPUTE_CALL_LIMIT_LOG 0x00000d64
225
226 #define NVC0_COMPUTE_UNK0D94 0x00000d94
227
228 #define NVC0_COMPUTE_WATCHDOG_TIMER 0x00000de4
229
230 #define NVC0_COMPUTE_UNK10F4 0x000010f4
231 #define NVC0_COMPUTE_UNK10F4_UNK0 0x00000001
232 #define NVC0_COMPUTE_UNK10F4_UNK4 0x00000010
233 #define NVC0_COMPUTE_UNK10F4_UNK8 0x00000100
234
235 #define NVC0_COMPUTE_LINKED_TSC 0x00001234
236
237 #define NVC0_COMPUTE_UNK1288_TIC_FLUSH 0x00001288
238
239 #define NVC0_COMPUTE_UNK12AC 0x000012ac
240
241 #define NVC0_COMPUTE_TSC_FLUSH 0x00001330
242 #define NVC0_COMPUTE_TSC_FLUSH_SPECIFIC 0x00000001
243 #define NVC0_COMPUTE_TSC_FLUSH_ENTRY__MASK 0x03fffff0
244 #define NVC0_COMPUTE_TSC_FLUSH_ENTRY__SHIFT 4
245
246 #define NVC0_COMPUTE_TIC_FLUSH 0x00001334
247 #define NVC0_COMPUTE_TIC_FLUSH_SPECIFIC 0x00000001
248 #define NVC0_COMPUTE_TIC_FLUSH_ENTRY__MASK 0x03fffff0
249 #define NVC0_COMPUTE_TIC_FLUSH_ENTRY__SHIFT 4
250
251 #define NVC0_COMPUTE_TEX_CACHE_CTL 0x00001338
252 #define NVC0_COMPUTE_TEX_CACHE_CTL_UNK0__MASK 0x00000007
253 #define NVC0_COMPUTE_TEX_CACHE_CTL_UNK0__SHIFT 0
254 #define NVC0_COMPUTE_TEX_CACHE_CTL_ENTRY__MASK 0x03fffff0
255 #define NVC0_COMPUTE_TEX_CACHE_CTL_ENTRY__SHIFT 4
256
257 #define NVC0_COMPUTE_UNK1354 0x00001354
258
259 #define NVC0_COMPUTE_UNK1424_TSC_FLUSH 0x00001424
260
261 #define NVC0_COMPUTE_COND_ADDRESS_HIGH 0x00001550
262
263 #define NVC0_COMPUTE_COND_ADDRESS_LOW 0x00001554
264
265 #define NVC0_COMPUTE_COND_MODE 0x00001558
266 #define NVC0_COMPUTE_COND_MODE_NEVER 0x00000000
267 #define NVC0_COMPUTE_COND_MODE_ALWAYS 0x00000001
268 #define NVC0_COMPUTE_COND_MODE_RES_NON_ZERO 0x00000002
269 #define NVC0_COMPUTE_COND_MODE_EQUAL 0x00000003
270 #define NVC0_COMPUTE_COND_MODE_NOT_EQUAL 0x00000004
271
272 #define NVC0_COMPUTE_TSC_ADDRESS_HIGH 0x0000155c
273
274 #define NVC0_COMPUTE_TSC_ADDRESS_LOW 0x00001560
275
276 #define NVC0_COMPUTE_TSC_LIMIT 0x00001564
277
278 #define NVC0_COMPUTE_TIC_ADDRESS_HIGH 0x00001574
279
280 #define NVC0_COMPUTE_TIC_ADDRESS_LOW 0x00001578
281
282 #define NVC0_COMPUTE_TIC_LIMIT 0x0000157c
283
284 #define NVC0_COMPUTE_CODE_ADDRESS_HIGH 0x00001608
285
286 #define NVC0_COMPUTE_CODE_ADDRESS_LOW 0x0000160c
287
288 #define NVC0_COMPUTE_TEX_MISC 0x00001664
289 #define NVC0_COMPUTE_TEX_MISC_UNK 0x00000001
290 #define NVC0_COMPUTE_TEX_MISC_SEAMLESS_CUBE_MAP 0x00000002
291
292 #define NVC0_COMPUTE_UNK1690 0x00001690
293 #define NVC0_COMPUTE_UNK1690_ALWAYS_DERIV 0x00000001
294 #define NVC0_COMPUTE_UNK1690_UNK16 0x00010000
295
296 #define NVC0_COMPUTE_CB_BIND 0x00001694
297 #define NVC0_COMPUTE_CB_BIND_VALID 0x00000001
298 #define NVC0_COMPUTE_CB_BIND_INDEX__MASK 0x00001f00
299 #define NVC0_COMPUTE_CB_BIND_INDEX__SHIFT 8
300
301 #define NVC0_COMPUTE_FLUSH 0x00001698
302 #define NVC0_COMPUTE_FLUSH_CODE 0x00000001
303 #define NVC0_COMPUTE_FLUSH_GLOBAL 0x00000010
304 #define NVC0_COMPUTE_FLUSH_UNK8 0x00000100
305 #define NVC0_COMPUTE_FLUSH_CB 0x00001000
306
307 #define NVC0_COMPUTE_UNK1930 0x00001930
308
309 #define NVC0_COMPUTE_UNK1944 0x00001944
310
311 #define NVC0_COMPUTE_DELAY 0x00001a24
312
313 #define NVC0_COMPUTE_UNK1A2C(i0) (0x00001a2c + 0x4*(i0))
314 #define NVC0_COMPUTE_UNK1A2C__ESIZE 0x00000004
315 #define NVC0_COMPUTE_UNK1A2C__LEN 0x00000005
316
317 #define NVC0_COMPUTE_QUERY_ADDRESS_HIGH 0x00001b00
318
319 #define NVC0_COMPUTE_QUERY_ADDRESS_LOW 0x00001b04
320
321 #define NVC0_COMPUTE_QUERY_SEQUENCE 0x00001b08
322
323 #define NVC0_COMPUTE_QUERY_GET 0x00001b0c
324 #define NVC0_COMPUTE_QUERY_GET_MODE__MASK 0x00000003
325 #define NVC0_COMPUTE_QUERY_GET_MODE__SHIFT 0
326 #define NVC0_COMPUTE_QUERY_GET_MODE_WRITE 0x00000000
327 #define NVC0_COMPUTE_QUERY_GET_MODE_WRITE_INTR_NRHOST 0x00000003
328 #define NVC0_COMPUTE_QUERY_GET_INTR 0x00100000
329 #define NVC0_COMPUTE_QUERY_GET_SHORT 0x10000000
330
331 #define NVC0_COMPUTE_CB_SIZE 0x00002380
332
333 #define NVC0_COMPUTE_CB_ADDRESS_HIGH 0x00002384
334
335 #define NVC0_COMPUTE_CB_ADDRESS_LOW 0x00002388
336
337 #define NVC0_COMPUTE_CB_POS 0x0000238c
338
339 #define NVC0_COMPUTE_CB_DATA(i0) (0x00002390 + 0x4*(i0))
340 #define NVC0_COMPUTE_CB_DATA__ESIZE 0x00000004
341 #define NVC0_COMPUTE_CB_DATA__LEN 0x00000010
342
343 #define NVC0_COMPUTE_IMAGE(i0) (0x00002700 + 0x20*(i0))
344 #define NVC0_COMPUTE_IMAGE__ESIZE 0x00000020
345 #define NVC0_COMPUTE_IMAGE__LEN 0x00000008
346
347 #define NVC0_COMPUTE_IMAGE_ADDRESS_HIGH(i0) (0x00002700 + 0x20*(i0))
348
349 #define NVC0_COMPUTE_IMAGE_ADDRESS_LOW(i0) (0x00002704 + 0x20*(i0))
350
351 #define NVC0_COMPUTE_IMAGE_WIDTH(i0) (0x00002708 + 0x20*(i0))
352
353 #define NVC0_COMPUTE_IMAGE_HEIGHT(i0) (0x0000270c + 0x20*(i0))
354 #define NVC0_COMPUTE_IMAGE_HEIGHT_HEIGHT__MASK 0x0000ffff
355 #define NVC0_COMPUTE_IMAGE_HEIGHT_HEIGHT__SHIFT 0
356 #define NVC0_COMPUTE_IMAGE_HEIGHT_UNK16 0x00010000
357 #define NVC0_COMPUTE_IMAGE_HEIGHT_LINEAR 0x00100000
358
359 #define NVC0_COMPUTE_IMAGE_FORMAT(i0) (0x00002710 + 0x20*(i0))
360 #define NVC0_COMPUTE_IMAGE_FORMAT_UNK0 0x00000001
361 #define NVC0_COMPUTE_IMAGE_FORMAT_FORMAT_COLOR__MASK 0x00000ff0
362 #define NVC0_COMPUTE_IMAGE_FORMAT_FORMAT_COLOR__SHIFT 4
363 #define NVC0_COMPUTE_IMAGE_FORMAT_FORMAT_ZETA__MASK 0x0001f000
364 #define NVC0_COMPUTE_IMAGE_FORMAT_FORMAT_ZETA__SHIFT 12
365
366 #define NVC0_COMPUTE_IMAGE_TILE_MODE(i0) (0x00002714 + 0x20*(i0))
367
368 #define NVC0_COMPUTE_MP_PM_SET(i0) (0x0000335c + 0x4*(i0))
369 #define NVC0_COMPUTE_MP_PM_SET__ESIZE 0x00000004
370 #define NVC0_COMPUTE_MP_PM_SET__LEN 0x00000008
371
372 #define NVC0_COMPUTE_MP_PM_SIGSEL(i0) (0x0000337c + 0x4*(i0))
373 #define NVC0_COMPUTE_MP_PM_SIGSEL__ESIZE 0x00000004
374 #define NVC0_COMPUTE_MP_PM_SIGSEL__LEN 0x00000008
375
376 #define NVC0_COMPUTE_MP_PM_SRCSEL(i0) (0x0000339c + 0x4*(i0))
377 #define NVC0_COMPUTE_MP_PM_SRCSEL__ESIZE 0x00000004
378 #define NVC0_COMPUTE_MP_PM_SRCSEL__LEN 0x00000008
379 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP0__MASK 0x00000007
380 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP0__SHIFT 0
381 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG0__MASK 0x00000070
382 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG0__SHIFT 4
383 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP1__MASK 0x00000700
384 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP1__SHIFT 8
385 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG1__MASK 0x00007000
386 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG1__SHIFT 12
387 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP2__MASK 0x00070000
388 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP2__SHIFT 16
389 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG2__MASK 0x00700000
390 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG2__SHIFT 20
391 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP3__MASK 0x07000000
392 #define NVC0_COMPUTE_MP_PM_SRCSEL_GRP3__SHIFT 24
393 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG3__MASK 0x70000000
394 #define NVC0_COMPUTE_MP_PM_SRCSEL_SIG3__SHIFT 28
395
396 #define NVC0_COMPUTE_MP_PM_OP(i0) (0x000033bc + 0x4*(i0))
397 #define NVC0_COMPUTE_MP_PM_OP__ESIZE 0x00000004
398 #define NVC0_COMPUTE_MP_PM_OP__LEN 0x00000008
399 #define NVC0_COMPUTE_MP_PM_OP_MODE__MASK 0x00000001
400 #define NVC0_COMPUTE_MP_PM_OP_MODE__SHIFT 0
401 #define NVC0_COMPUTE_MP_PM_OP_MODE_LOGOP 0x00000000
402 #define NVC0_COMPUTE_MP_PM_OP_MODE_LOGOP_PULSE 0x00000001
403 #define NVC0_COMPUTE_MP_PM_OP_FUNC__MASK 0x000ffff0
404 #define NVC0_COMPUTE_MP_PM_OP_FUNC__SHIFT 4
405
406 #define NVC0_COMPUTE_MP_PM_UNK33DC 0x000033dc
407
408
409 #endif /* NVC0_COMPUTE_XML */