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nvc0: remove nvc0_program.tp.input_patch_size
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "compiler/nir/nir.h"
26 #include "tgsi/tgsi_ureg.h"
27
28 #include "nvc0/nvc0_context.h"
29
30 #include "codegen/nv50_ir_driver.h"
31 #include "nvc0/nve4_compute.h"
32
33 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
34 * 124 scalar varying values.
35 */
36 static uint32_t
37 nvc0_shader_input_address(unsigned sn, unsigned si)
38 {
39 switch (sn) {
40 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
41 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
42 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
43 case TGSI_SEMANTIC_PRIMID: return 0x060;
44 case TGSI_SEMANTIC_LAYER: return 0x064;
45 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
46 case TGSI_SEMANTIC_PSIZE: return 0x06c;
47 case TGSI_SEMANTIC_POSITION: return 0x070;
48 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
49 case TGSI_SEMANTIC_FOG: return 0x2e8;
50 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
51 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
52 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
53 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
54 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
55 case TGSI_SEMANTIC_TESSCOORD: return 0x2f0;
56 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
57 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
58 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
59 default:
60 assert(!"invalid TGSI input semantic");
61 return ~0;
62 }
63 }
64
65 static uint32_t
66 nvc0_shader_output_address(unsigned sn, unsigned si)
67 {
68 switch (sn) {
69 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
70 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
71 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
72 case TGSI_SEMANTIC_PRIMID: return 0x060;
73 case TGSI_SEMANTIC_LAYER: return 0x064;
74 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
75 case TGSI_SEMANTIC_PSIZE: return 0x06c;
76 case TGSI_SEMANTIC_POSITION: return 0x070;
77 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
78 case TGSI_SEMANTIC_FOG: return 0x2e8;
79 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
80 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
81 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
82 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
83 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
84 /* case TGSI_SEMANTIC_VIEWPORT_MASK: return 0x3a0; */
85 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
86 default:
87 assert(!"invalid TGSI output semantic");
88 return ~0;
89 }
90 }
91
92 static int
93 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
94 {
95 unsigned i, c, n;
96
97 for (n = 0, i = 0; i < info->numInputs; ++i) {
98 switch (info->in[i].sn) {
99 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
100 case TGSI_SEMANTIC_VERTEXID:
101 info->in[i].mask = 0x1;
102 info->in[i].slot[0] =
103 nvc0_shader_input_address(info->in[i].sn, 0) / 4;
104 continue;
105 default:
106 break;
107 }
108 for (c = 0; c < 4; ++c)
109 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
110 ++n;
111 }
112
113 return 0;
114 }
115
116 static int
117 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
118 {
119 unsigned offset;
120 unsigned i, c;
121
122 for (i = 0; i < info->numInputs; ++i) {
123 offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
124
125 for (c = 0; c < 4; ++c)
126 info->in[i].slot[c] = (offset + c * 0x4) / 4;
127 }
128
129 return 0;
130 }
131
132 static int
133 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
134 {
135 unsigned count = info->prop.fp.numColourResults * 4;
136 unsigned i, c;
137
138 /* Compute the relative position of each color output, since skipped MRT
139 * positions will not have registers allocated to them.
140 */
141 unsigned colors[8] = {0};
142 for (i = 0; i < info->numOutputs; ++i)
143 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
144 colors[info->out[i].si] = 1;
145 for (i = 0, c = 0; i < 8; i++)
146 if (colors[i])
147 colors[i] = c++;
148 for (i = 0; i < info->numOutputs; ++i)
149 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
150 for (c = 0; c < 4; ++c)
151 info->out[i].slot[c] = colors[info->out[i].si] * 4 + c;
152
153 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
154 info->out[info->io.sampleMask].slot[0] = count++;
155 else
156 if (info->target >= 0xe0)
157 count++; /* on Kepler, depth is always last colour reg + 2 */
158
159 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
160 info->out[info->io.fragDepth].slot[2] = count;
161
162 return 0;
163 }
164
165 static int
166 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
167 {
168 unsigned offset;
169 unsigned i, c;
170
171 for (i = 0; i < info->numOutputs; ++i) {
172 offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
173
174 for (c = 0; c < 4; ++c)
175 info->out[i].slot[c] = (offset + c * 0x4) / 4;
176 }
177
178 return 0;
179 }
180
181 static int
182 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
183 {
184 int ret;
185
186 if (info->type == PIPE_SHADER_VERTEX)
187 ret = nvc0_vp_assign_input_slots(info);
188 else
189 ret = nvc0_sp_assign_input_slots(info);
190 if (ret)
191 return ret;
192
193 if (info->type == PIPE_SHADER_FRAGMENT)
194 ret = nvc0_fp_assign_output_slots(info);
195 else
196 ret = nvc0_sp_assign_output_slots(info);
197 return ret;
198 }
199
200 static inline void
201 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
202 {
203 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
204 uint8_t max = (vp->hdr[4] >> 24);
205
206 min = MIN2(min, slot);
207 max = MAX2(max, slot);
208
209 vp->hdr[4] = (max << 24) | (min << 12);
210 }
211
212 /* Common part of header generation for VP, TCP, TEP and GP. */
213 static int
214 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
215 {
216 unsigned i, c, a;
217
218 for (i = 0; i < info->numInputs; ++i) {
219 if (info->in[i].patch)
220 continue;
221 for (c = 0; c < 4; ++c) {
222 a = info->in[i].slot[c];
223 if (info->in[i].mask & (1 << c))
224 vp->hdr[5 + a / 32] |= 1 << (a % 32);
225 }
226 }
227
228 for (i = 0; i < info->numOutputs; ++i) {
229 if (info->out[i].patch)
230 continue;
231 for (c = 0; c < 4; ++c) {
232 if (!(info->out[i].mask & (1 << c)))
233 continue;
234 assert(info->out[i].slot[c] >= 0x40 / 4);
235 a = info->out[i].slot[c] - 0x40 / 4;
236 vp->hdr[13 + a / 32] |= 1 << (a % 32);
237 if (info->out[i].oread)
238 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
239 }
240 }
241
242 for (i = 0; i < info->numSysVals; ++i) {
243 switch (info->sv[i].sn) {
244 case TGSI_SEMANTIC_PRIMID:
245 vp->hdr[5] |= 1 << 24;
246 break;
247 case TGSI_SEMANTIC_INSTANCEID:
248 vp->hdr[10] |= 1 << 30;
249 break;
250 case TGSI_SEMANTIC_VERTEXID:
251 vp->hdr[10] |= 1 << 31;
252 break;
253 case TGSI_SEMANTIC_TESSCOORD:
254 /* We don't have the mask, nor the slots populated. While this could
255 * be achieved, the vast majority of the time if either of the coords
256 * are read, then both will be read.
257 */
258 nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
259 nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
260 break;
261 default:
262 break;
263 }
264 }
265
266 vp->vp.clip_enable = (1 << info->io.clipDistances) - 1;
267 vp->vp.cull_enable =
268 ((1 << info->io.cullDistances) - 1) << info->io.clipDistances;
269 for (i = 0; i < info->io.cullDistances; ++i)
270 vp->vp.clip_mode |= 1 << ((info->io.clipDistances + i) * 4);
271
272 if (info->io.genUserClip < 0)
273 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
274
275 return 0;
276 }
277
278 static int
279 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
280 {
281 vp->hdr[0] = 0x20061 | (1 << 10);
282 vp->hdr[4] = 0xff000;
283
284 return nvc0_vtgp_gen_header(vp, info);
285 }
286
287 static void
288 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
289 {
290 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
291 tp->tp.tess_mode = ~0;
292 return;
293 }
294 switch (info->prop.tp.domain) {
295 case PIPE_PRIM_LINES:
296 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
297 break;
298 case PIPE_PRIM_TRIANGLES:
299 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
300 break;
301 case PIPE_PRIM_QUADS:
302 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
303 break;
304 default:
305 tp->tp.tess_mode = ~0;
306 return;
307 }
308
309 /* It seems like lines want the "CW" bit to indicate they're connected, and
310 * spit out errors in dmesg when the "CONNECTED" bit is set.
311 */
312 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS) {
313 if (info->prop.tp.domain == PIPE_PRIM_LINES)
314 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
315 else
316 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
317 }
318
319 /* Winding only matters for triangles/quads, not lines. */
320 if (info->prop.tp.domain != PIPE_PRIM_LINES &&
321 info->prop.tp.outputPrim != PIPE_PRIM_POINTS &&
322 info->prop.tp.winding > 0)
323 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
324
325 switch (info->prop.tp.partitioning) {
326 case PIPE_TESS_SPACING_EQUAL:
327 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
328 break;
329 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
330 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
331 break;
332 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
333 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
334 break;
335 default:
336 assert(!"invalid tessellator partitioning");
337 break;
338 }
339 }
340
341 static int
342 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
343 {
344 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
345
346 if (info->numPatchConstants)
347 opcs = 8 + info->numPatchConstants * 4;
348
349 tcp->hdr[0] = 0x20061 | (2 << 10);
350
351 tcp->hdr[1] = opcs << 24;
352 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
353
354 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
355
356 nvc0_vtgp_gen_header(tcp, info);
357
358 if (info->target >= NVISA_GM107_CHIPSET) {
359 /* On GM107+, the number of output patch components has moved in the TCP
360 * header, but it seems like blob still also uses the old position.
361 * Also, the high 8-bits are located inbetween the min/max parallel
362 * field and has to be set after updating the outputs. */
363 tcp->hdr[3] = (opcs & 0x0f) << 28;
364 tcp->hdr[4] |= (opcs & 0xf0) << 16;
365 }
366
367 nvc0_tp_get_tess_mode(tcp, info);
368
369 return 0;
370 }
371
372 static int
373 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
374 {
375 tep->hdr[0] = 0x20061 | (3 << 10);
376 tep->hdr[4] = 0xff000;
377
378 nvc0_vtgp_gen_header(tep, info);
379
380 nvc0_tp_get_tess_mode(tep, info);
381
382 tep->hdr[18] |= 0x3 << 12; /* ? */
383
384 return 0;
385 }
386
387 static int
388 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
389 {
390 gp->hdr[0] = 0x20061 | (4 << 10);
391
392 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
393
394 switch (info->prop.gp.outputPrim) {
395 case PIPE_PRIM_POINTS:
396 gp->hdr[3] = 0x01000000;
397 gp->hdr[0] |= 0xf0000000;
398 break;
399 case PIPE_PRIM_LINE_STRIP:
400 gp->hdr[3] = 0x06000000;
401 gp->hdr[0] |= 0x10000000;
402 break;
403 case PIPE_PRIM_TRIANGLE_STRIP:
404 gp->hdr[3] = 0x07000000;
405 gp->hdr[0] |= 0x10000000;
406 break;
407 default:
408 assert(0);
409 break;
410 }
411
412 gp->hdr[4] = CLAMP(info->prop.gp.maxVertices, 1, 1024);
413
414 return nvc0_vtgp_gen_header(gp, info);
415 }
416
417 #define NVC0_INTERP_FLAT (1 << 0)
418 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
419 #define NVC0_INTERP_LINEAR (3 << 0)
420 #define NVC0_INTERP_CENTROID (1 << 2)
421
422 static uint8_t
423 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
424 {
425 if (var->linear)
426 return NVC0_INTERP_LINEAR;
427 if (var->flat)
428 return NVC0_INTERP_FLAT;
429 return NVC0_INTERP_PERSPECTIVE;
430 }
431
432 static int
433 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
434 {
435 unsigned i, c, a, m;
436
437 /* just 00062 on Kepler */
438 fp->hdr[0] = 0x20062 | (5 << 10);
439 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
440
441 if (info->prop.fp.usesDiscard)
442 fp->hdr[0] |= 0x8000;
443 if (info->prop.fp.numColourResults > 1)
444 fp->hdr[0] |= 0x4000;
445 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
446 fp->hdr[19] |= 0x1;
447 if (info->prop.fp.writesDepth) {
448 fp->hdr[19] |= 0x2;
449 fp->flags[0] = 0x11; /* deactivate ZCULL */
450 }
451
452 for (i = 0; i < info->numInputs; ++i) {
453 m = nvc0_hdr_interp_mode(&info->in[i]);
454 if (info->in[i].sn == TGSI_SEMANTIC_COLOR) {
455 fp->fp.colors |= 1 << info->in[i].si;
456 if (info->in[i].sc)
457 fp->fp.color_interp[info->in[i].si] = m | (info->in[i].mask << 4);
458 }
459 for (c = 0; c < 4; ++c) {
460 if (!(info->in[i].mask & (1 << c)))
461 continue;
462 a = info->in[i].slot[c];
463 if (info->in[i].slot[0] >= (0x060 / 4) &&
464 info->in[i].slot[0] <= (0x07c / 4)) {
465 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
466 } else
467 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
468 info->in[i].slot[0] <= (0x2fc / 4)) {
469 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
470 } else {
471 if (info->in[i].slot[c] < (0x040 / 4) ||
472 info->in[i].slot[c] > (0x380 / 4))
473 continue;
474 a *= 2;
475 if (info->in[i].slot[0] >= (0x300 / 4))
476 a -= 32;
477 fp->hdr[4 + a / 32] |= m << (a % 32);
478 }
479 }
480 }
481 /* GM20x+ needs TGSI_SEMANTIC_POSITION to access sample locations */
482 if (info->prop.fp.readsSampleLocations && info->target >= NVISA_GM200_CHIPSET)
483 fp->hdr[5] |= 0x30000000;
484
485 for (i = 0; i < info->numOutputs; ++i) {
486 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
487 fp->hdr[18] |= 0xf << (4 * info->out[i].si);
488 }
489
490 /* There are no "regular" attachments, but the shader still needs to be
491 * executed. It seems like it wants to think that it has some color
492 * outputs in order to actually run.
493 */
494 if (info->prop.fp.numColourResults == 0 && !info->prop.fp.writesDepth)
495 fp->hdr[18] |= 0xf;
496
497 fp->fp.early_z = info->prop.fp.earlyFragTests;
498 fp->fp.sample_mask_in = info->prop.fp.usesSampleMaskIn;
499 fp->fp.reads_framebuffer = info->prop.fp.readsFramebuffer;
500 fp->fp.post_depth_coverage = info->prop.fp.postDepthCoverage;
501
502 /* Mark position xy and layer as read */
503 if (fp->fp.reads_framebuffer)
504 fp->hdr[5] |= 0x32000000;
505
506 return 0;
507 }
508
509 static struct nvc0_transform_feedback_state *
510 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
511 const struct pipe_stream_output_info *pso)
512 {
513 struct nvc0_transform_feedback_state *tfb;
514 unsigned b, i, c;
515
516 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
517 if (!tfb)
518 return NULL;
519 for (b = 0; b < 4; ++b) {
520 tfb->stride[b] = pso->stride[b] * 4;
521 tfb->varying_count[b] = 0;
522 }
523 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
524
525 for (i = 0; i < pso->num_outputs; ++i) {
526 unsigned s = pso->output[i].start_component;
527 unsigned p = pso->output[i].dst_offset;
528 const unsigned r = pso->output[i].register_index;
529 b = pso->output[i].output_buffer;
530
531 if (r >= info->numOutputs)
532 continue;
533
534 for (c = 0; c < pso->output[i].num_components; ++c)
535 tfb->varying_index[b][p++] = info->out[r].slot[s + c];
536
537 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
538 tfb->stream[b] = pso->output[i].stream;
539 }
540 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
541 for (c = tfb->varying_count[b]; c & 3; ++c)
542 tfb->varying_index[b][c] = 0;
543
544 return tfb;
545 }
546
547 #ifdef DEBUG
548 static void
549 nvc0_program_dump(struct nvc0_program *prog)
550 {
551 unsigned pos;
552
553 if (prog->type != PIPE_SHADER_COMPUTE) {
554 debug_printf("dumping HDR for type %i\n", prog->type);
555 for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
556 debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
557 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
558 }
559 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
560 for (pos = 0; pos < prog->code_size / 4; ++pos) {
561 if ((pos % 8) == 0)
562 debug_printf("\n");
563 debug_printf("%08x ", prog->code[pos]);
564 }
565 debug_printf("\n");
566 }
567 #endif
568
569 bool
570 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
571 struct pipe_debug_callback *debug)
572 {
573 struct nv50_ir_prog_info *info;
574 int ret;
575
576 info = CALLOC_STRUCT(nv50_ir_prog_info);
577 if (!info)
578 return false;
579
580 info->type = prog->type;
581 info->target = chipset;
582
583 info->bin.sourceRep = prog->pipe.type;
584 switch (prog->pipe.type) {
585 case PIPE_SHADER_IR_TGSI:
586 info->bin.source = (void *)prog->pipe.tokens;
587 break;
588 case PIPE_SHADER_IR_NIR:
589 info->bin.source = (void *)nir_shader_clone(NULL, prog->pipe.ir.nir);
590 break;
591 default:
592 assert(!"unsupported IR!");
593 free(info);
594 return false;
595 }
596
597 #ifdef DEBUG
598 info->target = debug_get_num_option("NV50_PROG_CHIPSET", chipset);
599 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
600 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
601 info->omitLineNum = debug_get_num_option("NV50_PROG_DEBUG_OMIT_LINENUM", 0);
602 #else
603 info->optLevel = 3;
604 #endif
605
606 info->bin.smemSize = prog->cp.smem_size;
607 info->io.genUserClip = prog->vp.num_ucps;
608 info->io.auxCBSlot = 15;
609 info->io.msInfoCBSlot = 15;
610 info->io.ucpBase = NVC0_CB_AUX_UCP_INFO;
611 info->io.drawInfoBase = NVC0_CB_AUX_DRAW_INFO;
612 info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
613 info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
614 info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
615 if (info->target >= NVISA_GK104_CHIPSET) {
616 info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
617 info->io.fbtexBindBase = NVC0_CB_AUX_FB_TEX_INFO;
618 info->io.bindlessBase = NVC0_CB_AUX_BINDLESS_INFO(0);
619 }
620
621 if (prog->type == PIPE_SHADER_COMPUTE) {
622 if (info->target >= NVISA_GK104_CHIPSET) {
623 info->io.auxCBSlot = 7;
624 info->io.msInfoCBSlot = 7;
625 info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
626 }
627 info->prop.cp.gridInfoBase = NVC0_CB_AUX_GRID_INFO(0);
628 } else {
629 info->io.sampleInfoBase = NVC0_CB_AUX_SAMPLE_INFO;
630 }
631
632 info->assignSlots = nvc0_program_assign_varying_slots;
633
634 ret = nv50_ir_generate_code(info);
635 if (ret) {
636 NOUVEAU_ERR("shader translation failed: %i\n", ret);
637 goto out;
638 }
639 if (prog->type != PIPE_SHADER_COMPUTE)
640 FREE(info->bin.syms);
641
642 prog->code = info->bin.code;
643 prog->code_size = info->bin.codeSize;
644 prog->relocs = info->bin.relocData;
645 prog->fixups = info->bin.fixupData;
646 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
647 prog->cp.smem_size = info->bin.smemSize;
648 prog->num_barriers = info->numBarriers;
649
650 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
651 prog->vp.need_draw_parameters = info->prop.vp.usesDrawParameters;
652
653 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
654 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
655 prog->vp.edgeflag = info->io.edgeFlagIn;
656
657 switch (prog->type) {
658 case PIPE_SHADER_VERTEX:
659 ret = nvc0_vp_gen_header(prog, info);
660 break;
661 case PIPE_SHADER_TESS_CTRL:
662 ret = nvc0_tcp_gen_header(prog, info);
663 break;
664 case PIPE_SHADER_TESS_EVAL:
665 ret = nvc0_tep_gen_header(prog, info);
666 break;
667 case PIPE_SHADER_GEOMETRY:
668 ret = nvc0_gp_gen_header(prog, info);
669 break;
670 case PIPE_SHADER_FRAGMENT:
671 ret = nvc0_fp_gen_header(prog, info);
672 break;
673 case PIPE_SHADER_COMPUTE:
674 prog->cp.syms = info->bin.syms;
675 prog->cp.num_syms = info->bin.numSyms;
676 break;
677 default:
678 ret = -1;
679 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
680 break;
681 }
682 if (ret)
683 goto out;
684
685 if (info->bin.tlsSpace) {
686 assert(info->bin.tlsSpace < (1 << 24));
687 prog->hdr[0] |= 1 << 26;
688 prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
689 prog->need_tls = true;
690 }
691 /* TODO: factor 2 only needed where joinat/precont is used,
692 * and we only have to count non-uniform branches
693 */
694 /*
695 if ((info->maxCFDepth * 2) > 16) {
696 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
697 prog->need_tls = true;
698 }
699 */
700 if (info->io.globalAccess)
701 prog->hdr[0] |= 1 << 26;
702 if (info->io.globalAccess & 0x2)
703 prog->hdr[0] |= 1 << 16;
704 if (info->io.fp64)
705 prog->hdr[0] |= 1 << 27;
706
707 if (prog->pipe.stream_output.num_outputs)
708 prog->tfb = nvc0_program_create_tfb_state(info,
709 &prog->pipe.stream_output);
710
711 pipe_debug_message(debug, SHADER_INFO,
712 "type: %d, local: %d, shared: %d, gpr: %d, inst: %d, bytes: %d",
713 prog->type, info->bin.tlsSpace, info->bin.smemSize,
714 prog->num_gprs, info->bin.instructions,
715 info->bin.codeSize);
716
717 #ifdef DEBUG
718 if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
719 nvc0_program_dump(prog);
720 #endif
721
722 out:
723 if (info->bin.sourceRep == PIPE_SHADER_IR_NIR)
724 ralloc_free((void *)info->bin.source);
725 FREE(info);
726 return !ret;
727 }
728
729 static inline int
730 nvc0_program_alloc_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
731 {
732 struct nvc0_screen *screen = nvc0->screen;
733 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
734 int ret;
735 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
736
737 /* On Fermi, SP_START_ID must be aligned to 0x40.
738 * On Kepler, the first instruction must be aligned to 0x80 because
739 * latency information is expected only at certain positions.
740 */
741 if (screen->base.class_3d >= NVE4_3D_CLASS)
742 size = size + (is_cp ? 0x40 : 0x70);
743 size = align(size, 0x40);
744
745 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
746 if (ret)
747 return ret;
748 prog->code_base = prog->mem->start;
749
750 if (!is_cp) {
751 if (screen->base.class_3d >= NVE4_3D_CLASS) {
752 switch (prog->mem->start & 0xff) {
753 case 0x40: prog->code_base += 0x70; break;
754 case 0x80: prog->code_base += 0x30; break;
755 case 0xc0: prog->code_base += 0x70; break;
756 default:
757 prog->code_base += 0x30;
758 assert((prog->mem->start & 0xff) == 0x00);
759 break;
760 }
761 }
762 } else {
763 if (screen->base.class_3d >= NVE4_3D_CLASS) {
764 if (prog->mem->start & 0x40)
765 prog->code_base += 0x40;
766 assert((prog->code_base & 0x7f) == 0x00);
767 }
768 }
769
770 return 0;
771 }
772
773 static inline void
774 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
775 {
776 struct nvc0_screen *screen = nvc0->screen;
777 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
778 uint32_t code_pos = prog->code_base + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
779
780 if (prog->relocs)
781 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos,
782 screen->lib_code->start, 0);
783 if (prog->fixups) {
784 nv50_ir_apply_fixups(prog->fixups, prog->code,
785 prog->fp.force_persample_interp,
786 prog->fp.flatshade,
787 0 /* alphatest */);
788 for (int i = 0; i < 2; i++) {
789 unsigned mask = prog->fp.color_interp[i] >> 4;
790 unsigned interp = prog->fp.color_interp[i] & 3;
791 if (!mask)
792 continue;
793 prog->hdr[14] &= ~(0xff << (8 * i));
794 if (prog->fp.flatshade)
795 interp = NVC0_INTERP_FLAT;
796 for (int c = 0; c < 4; c++)
797 if (mask & (1 << c))
798 prog->hdr[14] |= interp << (2 * (4 * i + c));
799 }
800 }
801
802 if (!is_cp)
803 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
804 NV_VRAM_DOMAIN(&screen->base),
805 NVC0_SHADER_HEADER_SIZE, prog->hdr);
806
807 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
808 NV_VRAM_DOMAIN(&screen->base), prog->code_size,
809 prog->code);
810 }
811
812 bool
813 nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog)
814 {
815 struct nvc0_screen *screen = nvc0->screen;
816 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
817 int ret;
818 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
819
820 ret = nvc0_program_alloc_code(nvc0, prog);
821 if (ret) {
822 struct nouveau_heap *heap = screen->text_heap;
823 struct nvc0_program *progs[] = { /* Sorted accordingly to SP_START_ID */
824 nvc0->compprog, nvc0->vertprog, nvc0->tctlprog,
825 nvc0->tevlprog, nvc0->gmtyprog, nvc0->fragprog
826 };
827
828 /* Note that the code library, which is allocated before anything else,
829 * does not have a priv pointer. We can stop once we hit it.
830 */
831 while (heap->next && heap->next->priv) {
832 struct nvc0_program *evict = heap->next->priv;
833 nouveau_heap_free(&evict->mem);
834 }
835 debug_printf("WARNING: out of code space, evicting all shaders.\n");
836
837 /* Make sure to synchronize before deleting the code segment. */
838 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
839
840 if ((screen->text->size << 1) <= (1 << 23)) {
841 ret = nvc0_screen_resize_text_area(screen, screen->text->size << 1);
842 if (ret) {
843 NOUVEAU_ERR("Error allocating TEXT area: %d\n", ret);
844 return false;
845 }
846
847 /* Re-upload the builtin function into the new code segment. */
848 nvc0_program_library_upload(nvc0);
849 }
850
851 ret = nvc0_program_alloc_code(nvc0, prog);
852 if (ret) {
853 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
854 return false;
855 }
856
857 /* All currently bound shaders have to be reuploaded. */
858 for (int i = 0; i < ARRAY_SIZE(progs); i++) {
859 if (!progs[i] || progs[i] == prog)
860 continue;
861
862 ret = nvc0_program_alloc_code(nvc0, progs[i]);
863 if (ret) {
864 NOUVEAU_ERR("failed to re-upload a shader after code eviction.\n");
865 return false;
866 }
867 nvc0_program_upload_code(nvc0, progs[i]);
868
869 if (progs[i]->type == PIPE_SHADER_COMPUTE) {
870 /* Caches have to be invalidated but the CP_START_ID will be
871 * updated in the launch_grid functions. */
872 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(FLUSH), 1);
873 PUSH_DATA (nvc0->base.pushbuf, NVC0_COMPUTE_FLUSH_CODE);
874 } else {
875 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(SP_START_ID(i)), 1);
876 PUSH_DATA (nvc0->base.pushbuf, progs[i]->code_base);
877 }
878 }
879 }
880
881 nvc0_program_upload_code(nvc0, prog);
882
883 #ifdef DEBUG
884 if (debug_get_bool_option("NV50_PROG_DEBUG", false))
885 nvc0_program_dump(prog);
886 #endif
887
888 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
889 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
890
891 return true;
892 }
893
894 /* Upload code for builtin functions like integer division emulation. */
895 void
896 nvc0_program_library_upload(struct nvc0_context *nvc0)
897 {
898 struct nvc0_screen *screen = nvc0->screen;
899 int ret;
900 uint32_t size;
901 const uint32_t *code;
902
903 if (screen->lib_code)
904 return;
905
906 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
907 if (!size)
908 return;
909
910 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
911 &screen->lib_code);
912 if (ret)
913 return;
914
915 nvc0->base.push_data(&nvc0->base,
916 screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
917 size, code);
918 /* no need for a memory barrier, will be emitted with first program */
919 }
920
921 void
922 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
923 {
924 const struct pipe_shader_state pipe = prog->pipe;
925 const ubyte type = prog->type;
926
927 if (prog->mem)
928 nouveau_heap_free(&prog->mem);
929 FREE(prog->code); /* may be 0 for hardcoded shaders */
930 FREE(prog->relocs);
931 FREE(prog->fixups);
932 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
933 FREE(prog->cp.syms);
934 if (prog->tfb) {
935 if (nvc0->state.tfb == prog->tfb)
936 nvc0->state.tfb = NULL;
937 FREE(prog->tfb);
938 }
939
940 memset(prog, 0, sizeof(*prog));
941
942 prog->pipe = pipe;
943 prog->type = type;
944 }
945
946 uint32_t
947 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
948 {
949 const struct nv50_ir_prog_symbol *syms =
950 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
951 unsigned base = 0;
952 unsigned i;
953 if (prog->type != PIPE_SHADER_COMPUTE)
954 base = NVC0_SHADER_HEADER_SIZE;
955 for (i = 0; i < prog->cp.num_syms; ++i)
956 if (syms[i].label == label)
957 return prog->code_base + base + syms[i].offset;
958 return prog->code_base; /* no symbols or symbol not found */
959 }
960
961 void
962 nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
963 {
964 struct ureg_program *ureg;
965
966 ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
967 if (!ureg)
968 return;
969
970 ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
971 ureg_END(ureg);
972
973 nvc0->tcp_empty = ureg_create_shader_and_destroy(ureg, &nvc0->base.pipe);
974 }