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nouveau: Silence unhandled cap warnings
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "tgsi/tgsi_ureg.h"
26
27 #include "nvc0/nvc0_context.h"
28
29 #include "codegen/nv50_ir_driver.h"
30 #include "nvc0/nve4_compute.h"
31
32 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
33 * 124 scalar varying values.
34 */
35 static uint32_t
36 nvc0_shader_input_address(unsigned sn, unsigned si)
37 {
38 switch (sn) {
39 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
40 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
41 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
42 case TGSI_SEMANTIC_PRIMID: return 0x060;
43 case TGSI_SEMANTIC_LAYER: return 0x064;
44 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
45 case TGSI_SEMANTIC_PSIZE: return 0x06c;
46 case TGSI_SEMANTIC_POSITION: return 0x070;
47 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
48 case TGSI_SEMANTIC_FOG: return 0x2e8;
49 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
50 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
51 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
52 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
53 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
54 case TGSI_SEMANTIC_TESSCOORD: return 0x2f0;
55 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
56 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
57 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
58 default:
59 assert(!"invalid TGSI input semantic");
60 return ~0;
61 }
62 }
63
64 static uint32_t
65 nvc0_shader_output_address(unsigned sn, unsigned si)
66 {
67 switch (sn) {
68 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
69 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
70 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
71 case TGSI_SEMANTIC_PRIMID: return 0x060;
72 case TGSI_SEMANTIC_LAYER: return 0x064;
73 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
74 case TGSI_SEMANTIC_PSIZE: return 0x06c;
75 case TGSI_SEMANTIC_POSITION: return 0x070;
76 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
77 case TGSI_SEMANTIC_FOG: return 0x2e8;
78 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
79 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
80 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
81 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
82 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
83 /* case TGSI_SEMANTIC_VIEWPORT_MASK: return 0x3a0; */
84 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
85 default:
86 assert(!"invalid TGSI output semantic");
87 return ~0;
88 }
89 }
90
91 static int
92 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
93 {
94 unsigned i, c, n;
95
96 for (n = 0, i = 0; i < info->numInputs; ++i) {
97 switch (info->in[i].sn) {
98 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
99 case TGSI_SEMANTIC_VERTEXID:
100 info->in[i].mask = 0x1;
101 info->in[i].slot[0] =
102 nvc0_shader_input_address(info->in[i].sn, 0) / 4;
103 continue;
104 default:
105 break;
106 }
107 for (c = 0; c < 4; ++c)
108 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
109 ++n;
110 }
111
112 return 0;
113 }
114
115 static int
116 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
117 {
118 unsigned offset;
119 unsigned i, c;
120
121 for (i = 0; i < info->numInputs; ++i) {
122 offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
123
124 for (c = 0; c < 4; ++c)
125 info->in[i].slot[c] = (offset + c * 0x4) / 4;
126 }
127
128 return 0;
129 }
130
131 static int
132 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
133 {
134 unsigned count = info->prop.fp.numColourResults * 4;
135 unsigned i, c;
136
137 /* Compute the relative position of each color output, since skipped MRT
138 * positions will not have registers allocated to them.
139 */
140 unsigned colors[8] = {0};
141 for (i = 0; i < info->numOutputs; ++i)
142 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
143 colors[info->out[i].si] = 1;
144 for (i = 0, c = 0; i < 8; i++)
145 if (colors[i])
146 colors[i] = c++;
147 for (i = 0; i < info->numOutputs; ++i)
148 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
149 for (c = 0; c < 4; ++c)
150 info->out[i].slot[c] = colors[info->out[i].si] * 4 + c;
151
152 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
153 info->out[info->io.sampleMask].slot[0] = count++;
154 else
155 if (info->target >= 0xe0)
156 count++; /* on Kepler, depth is always last colour reg + 2 */
157
158 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
159 info->out[info->io.fragDepth].slot[2] = count;
160
161 return 0;
162 }
163
164 static int
165 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
166 {
167 unsigned offset;
168 unsigned i, c;
169
170 for (i = 0; i < info->numOutputs; ++i) {
171 offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
172
173 for (c = 0; c < 4; ++c)
174 info->out[i].slot[c] = (offset + c * 0x4) / 4;
175 }
176
177 return 0;
178 }
179
180 static int
181 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
182 {
183 int ret;
184
185 if (info->type == PIPE_SHADER_VERTEX)
186 ret = nvc0_vp_assign_input_slots(info);
187 else
188 ret = nvc0_sp_assign_input_slots(info);
189 if (ret)
190 return ret;
191
192 if (info->type == PIPE_SHADER_FRAGMENT)
193 ret = nvc0_fp_assign_output_slots(info);
194 else
195 ret = nvc0_sp_assign_output_slots(info);
196 return ret;
197 }
198
199 static inline void
200 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
201 {
202 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
203 uint8_t max = (vp->hdr[4] >> 24);
204
205 min = MIN2(min, slot);
206 max = MAX2(max, slot);
207
208 vp->hdr[4] = (max << 24) | (min << 12);
209 }
210
211 /* Common part of header generation for VP, TCP, TEP and GP. */
212 static int
213 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
214 {
215 unsigned i, c, a;
216
217 for (i = 0; i < info->numInputs; ++i) {
218 if (info->in[i].patch)
219 continue;
220 for (c = 0; c < 4; ++c) {
221 a = info->in[i].slot[c];
222 if (info->in[i].mask & (1 << c))
223 vp->hdr[5 + a / 32] |= 1 << (a % 32);
224 }
225 }
226
227 for (i = 0; i < info->numOutputs; ++i) {
228 if (info->out[i].patch)
229 continue;
230 for (c = 0; c < 4; ++c) {
231 if (!(info->out[i].mask & (1 << c)))
232 continue;
233 assert(info->out[i].slot[c] >= 0x40 / 4);
234 a = info->out[i].slot[c] - 0x40 / 4;
235 vp->hdr[13 + a / 32] |= 1 << (a % 32);
236 if (info->out[i].oread)
237 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
238 }
239 }
240
241 for (i = 0; i < info->numSysVals; ++i) {
242 switch (info->sv[i].sn) {
243 case TGSI_SEMANTIC_PRIMID:
244 vp->hdr[5] |= 1 << 24;
245 break;
246 case TGSI_SEMANTIC_INSTANCEID:
247 vp->hdr[10] |= 1 << 30;
248 break;
249 case TGSI_SEMANTIC_VERTEXID:
250 vp->hdr[10] |= 1 << 31;
251 break;
252 case TGSI_SEMANTIC_TESSCOORD:
253 /* We don't have the mask, nor the slots populated. While this could
254 * be achieved, the vast majority of the time if either of the coords
255 * are read, then both will be read.
256 */
257 nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
258 nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
259 break;
260 default:
261 break;
262 }
263 }
264
265 vp->vp.clip_enable = (1 << info->io.clipDistances) - 1;
266 vp->vp.cull_enable =
267 ((1 << info->io.cullDistances) - 1) << info->io.clipDistances;
268 for (i = 0; i < info->io.cullDistances; ++i)
269 vp->vp.clip_mode |= 1 << ((info->io.clipDistances + i) * 4);
270
271 if (info->io.genUserClip < 0)
272 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
273
274 return 0;
275 }
276
277 static int
278 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
279 {
280 vp->hdr[0] = 0x20061 | (1 << 10);
281 vp->hdr[4] = 0xff000;
282
283 return nvc0_vtgp_gen_header(vp, info);
284 }
285
286 static void
287 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
288 {
289 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
290 tp->tp.tess_mode = ~0;
291 return;
292 }
293 switch (info->prop.tp.domain) {
294 case PIPE_PRIM_LINES:
295 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
296 break;
297 case PIPE_PRIM_TRIANGLES:
298 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
299 break;
300 case PIPE_PRIM_QUADS:
301 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
302 break;
303 default:
304 tp->tp.tess_mode = ~0;
305 return;
306 }
307
308 /* It seems like lines want the "CW" bit to indicate they're connected, and
309 * spit out errors in dmesg when the "CONNECTED" bit is set.
310 */
311 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS) {
312 if (info->prop.tp.domain == PIPE_PRIM_LINES)
313 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
314 else
315 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
316 }
317
318 /* Winding only matters for triangles/quads, not lines. */
319 if (info->prop.tp.domain != PIPE_PRIM_LINES &&
320 info->prop.tp.outputPrim != PIPE_PRIM_POINTS &&
321 info->prop.tp.winding > 0)
322 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
323
324 switch (info->prop.tp.partitioning) {
325 case PIPE_TESS_SPACING_EQUAL:
326 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
327 break;
328 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
329 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
330 break;
331 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
332 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
333 break;
334 default:
335 assert(!"invalid tessellator partitioning");
336 break;
337 }
338 }
339
340 static int
341 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
342 {
343 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
344
345 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
346
347 if (info->numPatchConstants)
348 opcs = 8 + info->numPatchConstants * 4;
349
350 tcp->hdr[0] = 0x20061 | (2 << 10);
351
352 tcp->hdr[1] = opcs << 24;
353 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
354
355 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
356
357 nvc0_vtgp_gen_header(tcp, info);
358
359 if (info->target >= NVISA_GM107_CHIPSET) {
360 /* On GM107+, the number of output patch components has moved in the TCP
361 * header, but it seems like blob still also uses the old position.
362 * Also, the high 8-bits are located inbetween the min/max parallel
363 * field and has to be set after updating the outputs. */
364 tcp->hdr[3] = (opcs & 0x0f) << 28;
365 tcp->hdr[4] |= (opcs & 0xf0) << 16;
366 }
367
368 nvc0_tp_get_tess_mode(tcp, info);
369
370 return 0;
371 }
372
373 static int
374 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
375 {
376 tep->tp.input_patch_size = ~0;
377
378 tep->hdr[0] = 0x20061 | (3 << 10);
379 tep->hdr[4] = 0xff000;
380
381 nvc0_vtgp_gen_header(tep, info);
382
383 nvc0_tp_get_tess_mode(tep, info);
384
385 tep->hdr[18] |= 0x3 << 12; /* ? */
386
387 return 0;
388 }
389
390 static int
391 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
392 {
393 gp->hdr[0] = 0x20061 | (4 << 10);
394
395 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
396
397 switch (info->prop.gp.outputPrim) {
398 case PIPE_PRIM_POINTS:
399 gp->hdr[3] = 0x01000000;
400 gp->hdr[0] |= 0xf0000000;
401 break;
402 case PIPE_PRIM_LINE_STRIP:
403 gp->hdr[3] = 0x06000000;
404 gp->hdr[0] |= 0x10000000;
405 break;
406 case PIPE_PRIM_TRIANGLE_STRIP:
407 gp->hdr[3] = 0x07000000;
408 gp->hdr[0] |= 0x10000000;
409 break;
410 default:
411 assert(0);
412 break;
413 }
414
415 gp->hdr[4] = CLAMP(info->prop.gp.maxVertices, 1, 1024);
416
417 return nvc0_vtgp_gen_header(gp, info);
418 }
419
420 #define NVC0_INTERP_FLAT (1 << 0)
421 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
422 #define NVC0_INTERP_LINEAR (3 << 0)
423 #define NVC0_INTERP_CENTROID (1 << 2)
424
425 static uint8_t
426 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
427 {
428 if (var->linear)
429 return NVC0_INTERP_LINEAR;
430 if (var->flat)
431 return NVC0_INTERP_FLAT;
432 return NVC0_INTERP_PERSPECTIVE;
433 }
434
435 static int
436 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
437 {
438 unsigned i, c, a, m;
439
440 /* just 00062 on Kepler */
441 fp->hdr[0] = 0x20062 | (5 << 10);
442 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
443
444 if (info->prop.fp.usesDiscard)
445 fp->hdr[0] |= 0x8000;
446 if (info->prop.fp.numColourResults > 1)
447 fp->hdr[0] |= 0x4000;
448 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
449 fp->hdr[19] |= 0x1;
450 if (info->prop.fp.writesDepth) {
451 fp->hdr[19] |= 0x2;
452 fp->flags[0] = 0x11; /* deactivate ZCULL */
453 }
454
455 for (i = 0; i < info->numInputs; ++i) {
456 m = nvc0_hdr_interp_mode(&info->in[i]);
457 if (info->in[i].sn == TGSI_SEMANTIC_COLOR) {
458 fp->fp.colors |= 1 << info->in[i].si;
459 if (info->in[i].sc)
460 fp->fp.color_interp[info->in[i].si] = m | (info->in[i].mask << 4);
461 }
462 for (c = 0; c < 4; ++c) {
463 if (!(info->in[i].mask & (1 << c)))
464 continue;
465 a = info->in[i].slot[c];
466 if (info->in[i].slot[0] >= (0x060 / 4) &&
467 info->in[i].slot[0] <= (0x07c / 4)) {
468 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
469 } else
470 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
471 info->in[i].slot[0] <= (0x2fc / 4)) {
472 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
473 } else {
474 if (info->in[i].slot[c] < (0x040 / 4) ||
475 info->in[i].slot[c] > (0x380 / 4))
476 continue;
477 a *= 2;
478 if (info->in[i].slot[0] >= (0x300 / 4))
479 a -= 32;
480 fp->hdr[4 + a / 32] |= m << (a % 32);
481 }
482 }
483 }
484 /* GM20x+ needs TGSI_SEMANTIC_POSITION to access sample locations */
485 if (info->prop.fp.readsSampleLocations && info->target >= NVISA_GM200_CHIPSET)
486 fp->hdr[5] |= 0x30000000;
487
488 for (i = 0; i < info->numOutputs; ++i) {
489 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
490 fp->hdr[18] |= 0xf << (4 * info->out[i].si);
491 }
492
493 /* There are no "regular" attachments, but the shader still needs to be
494 * executed. It seems like it wants to think that it has some color
495 * outputs in order to actually run.
496 */
497 if (info->prop.fp.numColourResults == 0 && !info->prop.fp.writesDepth)
498 fp->hdr[18] |= 0xf;
499
500 fp->fp.early_z = info->prop.fp.earlyFragTests;
501 fp->fp.sample_mask_in = info->prop.fp.usesSampleMaskIn;
502 fp->fp.reads_framebuffer = info->prop.fp.readsFramebuffer;
503 fp->fp.post_depth_coverage = info->prop.fp.postDepthCoverage;
504
505 /* Mark position xy and layer as read */
506 if (fp->fp.reads_framebuffer)
507 fp->hdr[5] |= 0x32000000;
508
509 return 0;
510 }
511
512 static struct nvc0_transform_feedback_state *
513 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
514 const struct pipe_stream_output_info *pso)
515 {
516 struct nvc0_transform_feedback_state *tfb;
517 unsigned b, i, c;
518
519 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
520 if (!tfb)
521 return NULL;
522 for (b = 0; b < 4; ++b) {
523 tfb->stride[b] = pso->stride[b] * 4;
524 tfb->varying_count[b] = 0;
525 }
526 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
527
528 for (i = 0; i < pso->num_outputs; ++i) {
529 unsigned s = pso->output[i].start_component;
530 unsigned p = pso->output[i].dst_offset;
531 const unsigned r = pso->output[i].register_index;
532 b = pso->output[i].output_buffer;
533
534 if (r >= info->numOutputs)
535 continue;
536
537 for (c = 0; c < pso->output[i].num_components; ++c)
538 tfb->varying_index[b][p++] = info->out[r].slot[s + c];
539
540 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
541 tfb->stream[b] = pso->output[i].stream;
542 }
543 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
544 for (c = tfb->varying_count[b]; c & 3; ++c)
545 tfb->varying_index[b][c] = 0;
546
547 return tfb;
548 }
549
550 #ifdef DEBUG
551 static void
552 nvc0_program_dump(struct nvc0_program *prog)
553 {
554 unsigned pos;
555
556 if (prog->type != PIPE_SHADER_COMPUTE) {
557 for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
558 debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
559 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
560 }
561 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
562 for (pos = 0; pos < prog->code_size / 4; ++pos) {
563 if ((pos % 8) == 0)
564 debug_printf("\n");
565 debug_printf("%08x ", prog->code[pos]);
566 }
567 debug_printf("\n");
568 }
569 #endif
570
571 bool
572 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
573 struct pipe_debug_callback *debug)
574 {
575 struct nv50_ir_prog_info *info;
576 int ret;
577
578 info = CALLOC_STRUCT(nv50_ir_prog_info);
579 if (!info)
580 return false;
581
582 info->type = prog->type;
583 info->target = chipset;
584 info->bin.sourceRep = PIPE_SHADER_IR_TGSI;
585 info->bin.source = (void *)prog->pipe.tokens;
586
587 #ifdef DEBUG
588 info->target = debug_get_num_option("NV50_PROG_CHIPSET", chipset);
589 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
590 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
591 info->omitLineNum = debug_get_num_option("NV50_PROG_DEBUG_OMIT_LINENUM", 0);
592 #else
593 info->optLevel = 3;
594 #endif
595
596 info->bin.smemSize = prog->cp.smem_size;
597 info->io.genUserClip = prog->vp.num_ucps;
598 info->io.auxCBSlot = 15;
599 info->io.msInfoCBSlot = 15;
600 info->io.ucpBase = NVC0_CB_AUX_UCP_INFO;
601 info->io.drawInfoBase = NVC0_CB_AUX_DRAW_INFO;
602 info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
603 info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
604 info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
605 if (info->target >= NVISA_GK104_CHIPSET) {
606 info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
607 info->io.fbtexBindBase = NVC0_CB_AUX_FB_TEX_INFO;
608 info->io.bindlessBase = NVC0_CB_AUX_BINDLESS_INFO(0);
609 }
610
611 if (prog->type == PIPE_SHADER_COMPUTE) {
612 if (info->target >= NVISA_GK104_CHIPSET) {
613 info->io.auxCBSlot = 7;
614 info->io.msInfoCBSlot = 7;
615 info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
616 }
617 info->prop.cp.gridInfoBase = NVC0_CB_AUX_GRID_INFO(0);
618 } else {
619 info->io.sampleInfoBase = NVC0_CB_AUX_SAMPLE_INFO;
620 }
621
622 info->assignSlots = nvc0_program_assign_varying_slots;
623
624 ret = nv50_ir_generate_code(info);
625 if (ret) {
626 NOUVEAU_ERR("shader translation failed: %i\n", ret);
627 goto out;
628 }
629 if (prog->type != PIPE_SHADER_COMPUTE)
630 FREE(info->bin.syms);
631
632 prog->code = info->bin.code;
633 prog->code_size = info->bin.codeSize;
634 prog->relocs = info->bin.relocData;
635 prog->fixups = info->bin.fixupData;
636 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
637 prog->cp.smem_size = info->bin.smemSize;
638 prog->num_barriers = info->numBarriers;
639
640 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
641 prog->vp.need_draw_parameters = info->prop.vp.usesDrawParameters;
642
643 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
644 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
645 prog->vp.edgeflag = info->io.edgeFlagIn;
646
647 switch (prog->type) {
648 case PIPE_SHADER_VERTEX:
649 ret = nvc0_vp_gen_header(prog, info);
650 break;
651 case PIPE_SHADER_TESS_CTRL:
652 ret = nvc0_tcp_gen_header(prog, info);
653 break;
654 case PIPE_SHADER_TESS_EVAL:
655 ret = nvc0_tep_gen_header(prog, info);
656 break;
657 case PIPE_SHADER_GEOMETRY:
658 ret = nvc0_gp_gen_header(prog, info);
659 break;
660 case PIPE_SHADER_FRAGMENT:
661 ret = nvc0_fp_gen_header(prog, info);
662 break;
663 case PIPE_SHADER_COMPUTE:
664 prog->cp.syms = info->bin.syms;
665 prog->cp.num_syms = info->bin.numSyms;
666 break;
667 default:
668 ret = -1;
669 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
670 break;
671 }
672 if (ret)
673 goto out;
674
675 if (info->bin.tlsSpace) {
676 assert(info->bin.tlsSpace < (1 << 24));
677 prog->hdr[0] |= 1 << 26;
678 prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
679 prog->need_tls = true;
680 }
681 /* TODO: factor 2 only needed where joinat/precont is used,
682 * and we only have to count non-uniform branches
683 */
684 /*
685 if ((info->maxCFDepth * 2) > 16) {
686 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
687 prog->need_tls = true;
688 }
689 */
690 if (info->io.globalAccess)
691 prog->hdr[0] |= 1 << 26;
692 if (info->io.globalAccess & 0x2)
693 prog->hdr[0] |= 1 << 16;
694 if (info->io.fp64)
695 prog->hdr[0] |= 1 << 27;
696
697 if (prog->pipe.stream_output.num_outputs)
698 prog->tfb = nvc0_program_create_tfb_state(info,
699 &prog->pipe.stream_output);
700
701 pipe_debug_message(debug, SHADER_INFO,
702 "type: %d, local: %d, shared: %d, gpr: %d, inst: %d, bytes: %d",
703 prog->type, info->bin.tlsSpace, info->bin.smemSize,
704 prog->num_gprs, info->bin.instructions,
705 info->bin.codeSize);
706
707 #ifdef DEBUG
708 if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
709 nvc0_program_dump(prog);
710 #endif
711
712 out:
713 FREE(info);
714 return !ret;
715 }
716
717 static inline int
718 nvc0_program_alloc_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
719 {
720 struct nvc0_screen *screen = nvc0->screen;
721 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
722 int ret;
723 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
724
725 /* On Fermi, SP_START_ID must be aligned to 0x40.
726 * On Kepler, the first instruction must be aligned to 0x80 because
727 * latency information is expected only at certain positions.
728 */
729 if (screen->base.class_3d >= NVE4_3D_CLASS)
730 size = size + (is_cp ? 0x40 : 0x70);
731 size = align(size, 0x40);
732
733 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
734 if (ret)
735 return ret;
736 prog->code_base = prog->mem->start;
737
738 if (!is_cp) {
739 if (screen->base.class_3d >= NVE4_3D_CLASS) {
740 switch (prog->mem->start & 0xff) {
741 case 0x40: prog->code_base += 0x70; break;
742 case 0x80: prog->code_base += 0x30; break;
743 case 0xc0: prog->code_base += 0x70; break;
744 default:
745 prog->code_base += 0x30;
746 assert((prog->mem->start & 0xff) == 0x00);
747 break;
748 }
749 }
750 } else {
751 if (screen->base.class_3d >= NVE4_3D_CLASS) {
752 if (prog->mem->start & 0x40)
753 prog->code_base += 0x40;
754 assert((prog->code_base & 0x7f) == 0x00);
755 }
756 }
757
758 return 0;
759 }
760
761 static inline void
762 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
763 {
764 struct nvc0_screen *screen = nvc0->screen;
765 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
766 uint32_t code_pos = prog->code_base + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
767
768 if (prog->relocs)
769 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos,
770 screen->lib_code->start, 0);
771 if (prog->fixups) {
772 nv50_ir_apply_fixups(prog->fixups, prog->code,
773 prog->fp.force_persample_interp,
774 prog->fp.flatshade,
775 0 /* alphatest */);
776 for (int i = 0; i < 2; i++) {
777 unsigned mask = prog->fp.color_interp[i] >> 4;
778 unsigned interp = prog->fp.color_interp[i] & 3;
779 if (!mask)
780 continue;
781 prog->hdr[14] &= ~(0xff << (8 * i));
782 if (prog->fp.flatshade)
783 interp = NVC0_INTERP_FLAT;
784 for (int c = 0; c < 4; c++)
785 if (mask & (1 << c))
786 prog->hdr[14] |= interp << (2 * (4 * i + c));
787 }
788 }
789
790 if (!is_cp)
791 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
792 NV_VRAM_DOMAIN(&screen->base),
793 NVC0_SHADER_HEADER_SIZE, prog->hdr);
794
795 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
796 NV_VRAM_DOMAIN(&screen->base), prog->code_size,
797 prog->code);
798 }
799
800 bool
801 nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog)
802 {
803 struct nvc0_screen *screen = nvc0->screen;
804 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
805 int ret;
806 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
807
808 ret = nvc0_program_alloc_code(nvc0, prog);
809 if (ret) {
810 struct nouveau_heap *heap = screen->text_heap;
811 struct nvc0_program *progs[] = { /* Sorted accordingly to SP_START_ID */
812 nvc0->compprog, nvc0->vertprog, nvc0->tctlprog,
813 nvc0->tevlprog, nvc0->gmtyprog, nvc0->fragprog
814 };
815
816 /* Note that the code library, which is allocated before anything else,
817 * does not have a priv pointer. We can stop once we hit it.
818 */
819 while (heap->next && heap->next->priv) {
820 struct nvc0_program *evict = heap->next->priv;
821 nouveau_heap_free(&evict->mem);
822 }
823 debug_printf("WARNING: out of code space, evicting all shaders.\n");
824
825 /* Make sure to synchronize before deleting the code segment. */
826 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
827
828 if ((screen->text->size << 1) <= (1 << 23)) {
829 ret = nvc0_screen_resize_text_area(screen, screen->text->size << 1);
830 if (ret) {
831 NOUVEAU_ERR("Error allocating TEXT area: %d\n", ret);
832 return false;
833 }
834
835 /* Re-upload the builtin function into the new code segment. */
836 nvc0_program_library_upload(nvc0);
837 }
838
839 ret = nvc0_program_alloc_code(nvc0, prog);
840 if (ret) {
841 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
842 return false;
843 }
844
845 /* All currently bound shaders have to be reuploaded. */
846 for (int i = 0; i < ARRAY_SIZE(progs); i++) {
847 if (!progs[i] || progs[i] == prog)
848 continue;
849
850 ret = nvc0_program_alloc_code(nvc0, progs[i]);
851 if (ret) {
852 NOUVEAU_ERR("failed to re-upload a shader after code eviction.\n");
853 return false;
854 }
855 nvc0_program_upload_code(nvc0, progs[i]);
856
857 if (progs[i]->type == PIPE_SHADER_COMPUTE) {
858 /* Caches have to be invalidated but the CP_START_ID will be
859 * updated in the launch_grid functions. */
860 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(FLUSH), 1);
861 PUSH_DATA (nvc0->base.pushbuf, NVC0_COMPUTE_FLUSH_CODE);
862 } else {
863 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(SP_START_ID(i)), 1);
864 PUSH_DATA (nvc0->base.pushbuf, progs[i]->code_base);
865 }
866 }
867 }
868
869 nvc0_program_upload_code(nvc0, prog);
870
871 #ifdef DEBUG
872 if (debug_get_bool_option("NV50_PROG_DEBUG", false))
873 nvc0_program_dump(prog);
874 #endif
875
876 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
877 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
878
879 return true;
880 }
881
882 /* Upload code for builtin functions like integer division emulation. */
883 void
884 nvc0_program_library_upload(struct nvc0_context *nvc0)
885 {
886 struct nvc0_screen *screen = nvc0->screen;
887 int ret;
888 uint32_t size;
889 const uint32_t *code;
890
891 if (screen->lib_code)
892 return;
893
894 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
895 if (!size)
896 return;
897
898 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
899 &screen->lib_code);
900 if (ret)
901 return;
902
903 nvc0->base.push_data(&nvc0->base,
904 screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
905 size, code);
906 /* no need for a memory barrier, will be emitted with first program */
907 }
908
909 void
910 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
911 {
912 const struct pipe_shader_state pipe = prog->pipe;
913 const ubyte type = prog->type;
914
915 if (prog->mem)
916 nouveau_heap_free(&prog->mem);
917 FREE(prog->code); /* may be 0 for hardcoded shaders */
918 FREE(prog->relocs);
919 FREE(prog->fixups);
920 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
921 FREE(prog->cp.syms);
922 if (prog->tfb) {
923 if (nvc0->state.tfb == prog->tfb)
924 nvc0->state.tfb = NULL;
925 FREE(prog->tfb);
926 }
927
928 memset(prog, 0, sizeof(*prog));
929
930 prog->pipe = pipe;
931 prog->type = type;
932 }
933
934 uint32_t
935 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
936 {
937 const struct nv50_ir_prog_symbol *syms =
938 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
939 unsigned base = 0;
940 unsigned i;
941 if (prog->type != PIPE_SHADER_COMPUTE)
942 base = NVC0_SHADER_HEADER_SIZE;
943 for (i = 0; i < prog->cp.num_syms; ++i)
944 if (syms[i].label == label)
945 return prog->code_base + base + syms[i].offset;
946 return prog->code_base; /* no symbols or symbol not found */
947 }
948
949 void
950 nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
951 {
952 struct ureg_program *ureg;
953
954 ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
955 if (!ureg)
956 return;
957
958 ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
959 ureg_END(ureg);
960
961 nvc0->tcp_empty = ureg_create_shader_and_destroy(ureg, &nvc0->base.pipe);
962 }