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nvc0: add support for PIPE_CAP_SAMPLE_SHADING
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "nvc0/nvc0_context.h"
26
27 #include "codegen/nv50_ir_driver.h"
28 #include "nvc0/nve4_compute.h"
29
30 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
31 * 124 scalar varying values.
32 */
33 static uint32_t
34 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
35 {
36 switch (sn) {
37 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
38 case TGSI_SEMANTIC_PRIMID: return 0x060;
39 case TGSI_SEMANTIC_PSIZE: return 0x06c;
40 case TGSI_SEMANTIC_POSITION: return 0x070;
41 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
42 case TGSI_SEMANTIC_FOG: return 0x2e8;
43 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
44 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
45 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
46 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
47 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
48 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
49 case NV50_SEMANTIC_TESSCOORD: return 0x2f0;
50 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
51 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
52 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
53 case TGSI_SEMANTIC_FACE: return 0x3fc;
54 case NV50_SEMANTIC_INVOCATIONID: return ~0;
55 default:
56 assert(!"invalid TGSI input semantic");
57 return ~0;
58 }
59 }
60
61 static uint32_t
62 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
63 {
64 switch (sn) {
65 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
66 case TGSI_SEMANTIC_PRIMID: return 0x060;
67 case TGSI_SEMANTIC_LAYER: return 0x064;
68 case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
69 case TGSI_SEMANTIC_PSIZE: return 0x06c;
70 case TGSI_SEMANTIC_POSITION: return 0x070;
71 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
72 case TGSI_SEMANTIC_FOG: return 0x2e8;
73 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
74 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
75 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
76 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
77 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
78 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
79 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
80 default:
81 assert(!"invalid TGSI output semantic");
82 return ~0;
83 }
84 }
85
86 static int
87 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
88 {
89 unsigned i, c, n;
90
91 for (n = 0, i = 0; i < info->numInputs; ++i) {
92 switch (info->in[i].sn) {
93 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
94 case TGSI_SEMANTIC_VERTEXID:
95 info->in[i].mask = 0x1;
96 info->in[i].slot[0] =
97 nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
98 continue;
99 default:
100 break;
101 }
102 for (c = 0; c < 4; ++c)
103 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
104 ++n;
105 }
106
107 return 0;
108 }
109
110 static int
111 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
112 {
113 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
114 unsigned offset;
115 unsigned i, c;
116
117 for (i = 0; i < info->numInputs; ++i) {
118 offset = nvc0_shader_input_address(info->in[i].sn,
119 info->in[i].si, ubase);
120 if (info->in[i].patch && offset >= 0x20)
121 offset = 0x20 + info->in[i].si * 0x10;
122
123 if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
124 info->in[i].mask &= 3;
125
126 for (c = 0; c < 4; ++c)
127 info->in[i].slot[c] = (offset + c * 0x4) / 4;
128 }
129
130 return 0;
131 }
132
133 static int
134 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
135 {
136 unsigned count = info->prop.fp.numColourResults * 4;
137 unsigned i, c, ci;
138
139 for (i = 0, ci = 0; i < info->numOutputs; ++i) {
140 if (info->out[i].sn == TGSI_SEMANTIC_COLOR) {
141 for (c = 0; c < 4; ++c)
142 info->out[i].slot[c] = ci * 4 + c;
143 ci++;
144 }
145 }
146
147 assert(ci == info->prop.fp.numColourResults);
148
149 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
150 info->out[info->io.sampleMask].slot[0] = count++;
151 else
152 if (info->target >= 0xe0)
153 count++; /* on Kepler, depth is always last colour reg + 2 */
154
155 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
156 info->out[info->io.fragDepth].slot[2] = count;
157
158 return 0;
159 }
160
161 static int
162 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
163 {
164 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
165 unsigned offset;
166 unsigned i, c;
167
168 for (i = 0; i < info->numOutputs; ++i) {
169 offset = nvc0_shader_output_address(info->out[i].sn,
170 info->out[i].si, ubase);
171 if (info->out[i].patch && offset >= 0x20)
172 offset = 0x20 + info->out[i].si * 0x10;
173
174 for (c = 0; c < 4; ++c)
175 info->out[i].slot[c] = (offset + c * 0x4) / 4;
176 }
177
178 return 0;
179 }
180
181 static int
182 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
183 {
184 int ret;
185
186 if (info->type == PIPE_SHADER_VERTEX)
187 ret = nvc0_vp_assign_input_slots(info);
188 else
189 ret = nvc0_sp_assign_input_slots(info);
190 if (ret)
191 return ret;
192
193 if (info->type == PIPE_SHADER_FRAGMENT)
194 ret = nvc0_fp_assign_output_slots(info);
195 else
196 ret = nvc0_sp_assign_output_slots(info);
197 return ret;
198 }
199
200 static INLINE void
201 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
202 {
203 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
204 uint8_t max = (vp->hdr[4] >> 24);
205
206 min = MIN2(min, slot);
207 max = MAX2(max, slot);
208
209 vp->hdr[4] = (max << 24) | (min << 12);
210 }
211
212 /* Common part of header generation for VP, TCP, TEP and GP. */
213 static int
214 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
215 {
216 unsigned i, c, a;
217
218 for (i = 0; i < info->numInputs; ++i) {
219 if (info->in[i].patch)
220 continue;
221 for (c = 0; c < 4; ++c) {
222 a = info->in[i].slot[c];
223 if (info->in[i].mask & (1 << c)) {
224 if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
225 vp->hdr[5 + a / 32] |= 1 << (a % 32);
226 else
227 nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
228 }
229 }
230 }
231
232 for (i = 0; i < info->numOutputs; ++i) {
233 if (info->out[i].patch)
234 continue;
235 for (c = 0; c < 4; ++c) {
236 if (!(info->out[i].mask & (1 << c)))
237 continue;
238 assert(info->out[i].slot[c] >= 0x40 / 4);
239 a = info->out[i].slot[c] - 0x40 / 4;
240 vp->hdr[13 + a / 32] |= 1 << (a % 32);
241 if (info->out[i].oread)
242 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
243 }
244 }
245
246 for (i = 0; i < info->numSysVals; ++i) {
247 switch (info->sv[i].sn) {
248 case TGSI_SEMANTIC_PRIMID:
249 vp->hdr[5] |= 1 << 24;
250 break;
251 case TGSI_SEMANTIC_INSTANCEID:
252 vp->hdr[10] |= 1 << 30;
253 break;
254 case TGSI_SEMANTIC_VERTEXID:
255 vp->hdr[10] |= 1 << 31;
256 break;
257 default:
258 break;
259 }
260 }
261
262 vp->vp.clip_enable = info->io.clipDistanceMask;
263 for (i = 0; i < 8; ++i)
264 if (info->io.cullDistanceMask & (1 << i))
265 vp->vp.clip_mode |= 1 << (i * 4);
266
267 if (info->io.genUserClip < 0)
268 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
269
270 return 0;
271 }
272
273 static int
274 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
275 {
276 vp->hdr[0] = 0x20061 | (1 << 10);
277 vp->hdr[4] = 0xff000;
278
279 vp->hdr[18] = info->io.clipDistanceMask;
280
281 return nvc0_vtgp_gen_header(vp, info);
282 }
283
284 #if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
285 static void
286 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
287 {
288 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
289 tp->tp.tess_mode = ~0;
290 return;
291 }
292 switch (info->prop.tp.domain) {
293 case PIPE_PRIM_LINES:
294 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
295 break;
296 case PIPE_PRIM_TRIANGLES:
297 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
298 if (info->prop.tp.winding > 0)
299 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
300 break;
301 case PIPE_PRIM_QUADS:
302 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
303 break;
304 default:
305 tp->tp.tess_mode = ~0;
306 return;
307 }
308 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
309 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
310
311 switch (info->prop.tp.partitioning) {
312 case PIPE_TESS_PART_INTEGER:
313 case PIPE_TESS_PART_POW2:
314 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
315 break;
316 case PIPE_TESS_PART_FRACT_ODD:
317 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
318 break;
319 case PIPE_TESS_PART_FRACT_EVEN:
320 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
321 break;
322 default:
323 assert(!"invalid tessellator partitioning");
324 break;
325 }
326 }
327 #endif
328
329 #ifdef PIPE_SHADER_HULL
330 static int
331 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
332 {
333 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
334
335 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
336
337 if (info->numPatchConstants)
338 opcs = 8 + info->numPatchConstants * 4;
339
340 tcp->hdr[0] = 0x20061 | (2 << 10);
341
342 tcp->hdr[1] = opcs << 24;
343 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
344
345 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
346
347 nvc0_vtgp_gen_header(tcp, info);
348
349 nvc0_tp_get_tess_mode(tcp, info);
350
351 return 0;
352 }
353 #endif
354
355 #ifdef PIPE_SHADER_DOMAIN
356 static int
357 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
358 {
359 tep->tp.input_patch_size = ~0;
360
361 tep->hdr[0] = 0x20061 | (3 << 10);
362 tep->hdr[4] = 0xff000;
363
364 nvc0_vtgp_gen_header(tep, info);
365
366 nvc0_tp_get_tess_mode(tep, info);
367
368 tep->hdr[18] |= 0x3 << 12; /* ? */
369
370 return 0;
371 }
372 #endif
373
374 static int
375 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
376 {
377 gp->hdr[0] = 0x20061 | (4 << 10);
378
379 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
380
381 switch (info->prop.gp.outputPrim) {
382 case PIPE_PRIM_POINTS:
383 gp->hdr[3] = 0x01000000;
384 gp->hdr[0] |= 0xf0000000;
385 break;
386 case PIPE_PRIM_LINE_STRIP:
387 gp->hdr[3] = 0x06000000;
388 gp->hdr[0] |= 0x10000000;
389 break;
390 case PIPE_PRIM_TRIANGLE_STRIP:
391 gp->hdr[3] = 0x07000000;
392 gp->hdr[0] |= 0x10000000;
393 break;
394 default:
395 assert(0);
396 break;
397 }
398
399 gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff;
400
401 return nvc0_vtgp_gen_header(gp, info);
402 }
403
404 #define NVC0_INTERP_FLAT (1 << 0)
405 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
406 #define NVC0_INTERP_LINEAR (3 << 0)
407 #define NVC0_INTERP_CENTROID (1 << 2)
408
409 static uint8_t
410 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
411 {
412 if (var->linear)
413 return NVC0_INTERP_LINEAR;
414 if (var->flat)
415 return NVC0_INTERP_FLAT;
416 return NVC0_INTERP_PERSPECTIVE;
417 }
418
419 static int
420 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
421 {
422 unsigned i, c, a, m;
423
424 /* just 00062 on Kepler */
425 fp->hdr[0] = 0x20062 | (5 << 10);
426 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
427
428 if (info->prop.fp.usesDiscard)
429 fp->hdr[0] |= 0x8000;
430 if (info->prop.fp.numColourResults > 1)
431 fp->hdr[0] |= 0x4000;
432 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
433 fp->hdr[19] |= 0x1;
434 if (info->prop.fp.writesDepth) {
435 fp->hdr[19] |= 0x2;
436 fp->flags[0] = 0x11; /* deactivate ZCULL */
437 }
438
439 for (i = 0; i < info->numInputs; ++i) {
440 m = nvc0_hdr_interp_mode(&info->in[i]);
441 for (c = 0; c < 4; ++c) {
442 if (!(info->in[i].mask & (1 << c)))
443 continue;
444 a = info->in[i].slot[c];
445 if (info->in[i].slot[0] >= (0x060 / 4) &&
446 info->in[i].slot[0] <= (0x07c / 4)) {
447 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
448 } else
449 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
450 info->in[i].slot[0] <= (0x2fc / 4)) {
451 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
452 } else {
453 if (info->in[i].slot[c] < (0x040 / 4) ||
454 info->in[i].slot[c] > (0x380 / 4))
455 continue;
456 a *= 2;
457 if (info->in[i].slot[0] >= (0x300 / 4))
458 a -= 32;
459 fp->hdr[4 + a / 32] |= m << (a % 32);
460 }
461 }
462 }
463
464 for (i = 0; i < info->numOutputs; ++i) {
465 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
466 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
467 }
468
469 fp->fp.early_z = info->prop.fp.earlyFragTests;
470
471 return 0;
472 }
473
474 static struct nvc0_transform_feedback_state *
475 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
476 const struct pipe_stream_output_info *pso)
477 {
478 struct nvc0_transform_feedback_state *tfb;
479 unsigned b, i, c;
480
481 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
482 if (!tfb)
483 return NULL;
484 for (b = 0; b < 4; ++b) {
485 tfb->stride[b] = pso->stride[b] * 4;
486 tfb->varying_count[b] = 0;
487 }
488 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
489
490 for (i = 0; i < pso->num_outputs; ++i) {
491 unsigned s = pso->output[i].start_component;
492 unsigned p = pso->output[i].dst_offset;
493 b = pso->output[i].output_buffer;
494
495 for (c = 0; c < pso->output[i].num_components; ++c)
496 tfb->varying_index[b][p++] =
497 info->out[pso->output[i].register_index].slot[s + c];
498
499 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
500 }
501 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
502 for (c = tfb->varying_count[b]; c & 3; ++c)
503 tfb->varying_index[b][c] = 0;
504
505 return tfb;
506 }
507
508 #ifdef DEBUG
509 static void
510 nvc0_program_dump(struct nvc0_program *prog)
511 {
512 unsigned pos;
513
514 if (prog->type != PIPE_SHADER_COMPUTE) {
515 for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
516 debug_printf("HDR[%02lx] = 0x%08x\n",
517 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
518 }
519 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
520 for (pos = 0; pos < prog->code_size / 4; ++pos) {
521 if ((pos % 8) == 0)
522 debug_printf("\n");
523 debug_printf("%08x ", prog->code[pos]);
524 }
525 debug_printf("\n");
526 }
527 #endif
528
529 boolean
530 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
531 {
532 struct nv50_ir_prog_info *info;
533 int ret;
534
535 info = CALLOC_STRUCT(nv50_ir_prog_info);
536 if (!info)
537 return FALSE;
538
539 info->type = prog->type;
540 info->target = chipset;
541 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
542 info->bin.source = (void *)prog->pipe.tokens;
543
544 info->io.genUserClip = prog->vp.num_ucps;
545 info->io.ucpBase = 256;
546 info->io.ucpCBSlot = 15;
547 info->io.sampleInterp = prog->fp.sample_interp;
548
549 if (prog->type == PIPE_SHADER_COMPUTE) {
550 if (chipset >= NVISA_GK104_CHIPSET) {
551 info->io.resInfoCBSlot = 0;
552 info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
553 info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
554 info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
555 }
556 info->io.msInfoCBSlot = 0;
557 info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
558 } else {
559 if (chipset >= NVISA_GK104_CHIPSET) {
560 info->io.texBindBase = 0x20;
561 info->io.suInfoBase = 0; /* TODO */
562 }
563 info->io.resInfoCBSlot = 15;
564 info->io.sampleInfoBase = 256 + 128;
565 info->io.msInfoCBSlot = 15;
566 info->io.msInfoBase = 0; /* TODO */
567 }
568
569 info->assignSlots = nvc0_program_assign_varying_slots;
570
571 #ifdef DEBUG
572 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
573 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
574 #else
575 info->optLevel = 3;
576 #endif
577
578 ret = nv50_ir_generate_code(info);
579 if (ret) {
580 NOUVEAU_ERR("shader translation failed: %i\n", ret);
581 goto out;
582 }
583 if (prog->type != PIPE_SHADER_COMPUTE)
584 FREE(info->bin.syms);
585
586 prog->code = info->bin.code;
587 prog->code_size = info->bin.codeSize;
588 prog->immd_data = info->immd.buf;
589 prog->immd_size = info->immd.bufSize;
590 prog->relocs = info->bin.relocData;
591 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
592 prog->num_barriers = info->numBarriers;
593
594 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
595
596 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
597 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
598 prog->vp.edgeflag = info->io.edgeFlagIn;
599
600 switch (prog->type) {
601 case PIPE_SHADER_VERTEX:
602 ret = nvc0_vp_gen_header(prog, info);
603 break;
604 #ifdef PIPE_SHADER_HULL
605 case PIPE_SHADER_HULL:
606 ret = nvc0_tcp_gen_header(prog, info);
607 break;
608 #endif
609 #ifdef PIPE_SHADER_DOMAIN
610 case PIPE_SHADER_DOMAIN:
611 ret = nvc0_tep_gen_header(prog, info);
612 break;
613 #endif
614 case PIPE_SHADER_GEOMETRY:
615 ret = nvc0_gp_gen_header(prog, info);
616 break;
617 case PIPE_SHADER_FRAGMENT:
618 ret = nvc0_fp_gen_header(prog, info);
619 break;
620 case PIPE_SHADER_COMPUTE:
621 prog->cp.syms = info->bin.syms;
622 prog->cp.num_syms = info->bin.numSyms;
623 break;
624 default:
625 ret = -1;
626 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
627 break;
628 }
629 if (ret)
630 goto out;
631
632 if (info->bin.tlsSpace) {
633 assert(info->bin.tlsSpace < (1 << 24));
634 prog->hdr[0] |= 1 << 26;
635 prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
636 prog->need_tls = TRUE;
637 }
638 /* TODO: factor 2 only needed where joinat/precont is used,
639 * and we only have to count non-uniform branches
640 */
641 /*
642 if ((info->maxCFDepth * 2) > 16) {
643 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
644 prog->need_tls = TRUE;
645 }
646 */
647 if (info->io.globalAccess)
648 prog->hdr[0] |= 1 << 16;
649
650 if (prog->pipe.stream_output.num_outputs)
651 prog->tfb = nvc0_program_create_tfb_state(info,
652 &prog->pipe.stream_output);
653
654 out:
655 FREE(info);
656 return !ret;
657 }
658
659 boolean
660 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
661 {
662 struct nvc0_screen *screen = nvc0->screen;
663 const boolean is_cp = prog->type == PIPE_SHADER_COMPUTE;
664 int ret;
665 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
666 uint32_t lib_pos = screen->lib_code->start;
667 uint32_t code_pos;
668
669 /* c[] bindings need to be aligned to 0x100, but we could use relocations
670 * to save space. */
671 if (prog->immd_size) {
672 prog->immd_base = size;
673 size = align(size, 0x40);
674 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
675 }
676 /* On Fermi, SP_START_ID must be aligned to 0x40.
677 * On Kepler, the first instruction must be aligned to 0x80 because
678 * latency information is expected only at certain positions.
679 */
680 if (screen->base.class_3d >= NVE4_3D_CLASS)
681 size = size + (is_cp ? 0x40 : 0x70);
682 size = align(size, 0x40);
683
684 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
685 if (ret) {
686 struct nouveau_heap *heap = screen->text_heap;
687 struct nouveau_heap *iter;
688 for (iter = heap; iter && iter->next != heap; iter = iter->next) {
689 struct nvc0_program *evict = iter->priv;
690 if (evict)
691 nouveau_heap_free(&evict->mem);
692 }
693 debug_printf("WARNING: out of code space, evicting all shaders.\n");
694 ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
695 if (ret) {
696 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
697 return FALSE;
698 }
699 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
700 }
701 prog->code_base = prog->mem->start;
702 prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
703 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
704 prog->mem->start + prog->mem->size));
705
706 if (!is_cp) {
707 if (screen->base.class_3d >= NVE4_3D_CLASS) {
708 switch (prog->mem->start & 0xff) {
709 case 0x40: prog->code_base += 0x70; break;
710 case 0x80: prog->code_base += 0x30; break;
711 case 0xc0: prog->code_base += 0x70; break;
712 default:
713 prog->code_base += 0x30;
714 assert((prog->mem->start & 0xff) == 0x00);
715 break;
716 }
717 }
718 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
719 } else {
720 if (screen->base.class_3d >= NVE4_3D_CLASS) {
721 if (prog->mem->start & 0x40)
722 prog->code_base += 0x40;
723 assert((prog->code_base & 0x7f) == 0x00);
724 }
725 code_pos = prog->code_base;
726 }
727
728 if (prog->relocs)
729 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
730
731 #ifdef DEBUG
732 if (debug_get_bool_option("NV50_PROG_DEBUG", FALSE))
733 nvc0_program_dump(prog);
734 #endif
735
736 if (!is_cp)
737 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
738 NOUVEAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr);
739 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
740 NOUVEAU_BO_VRAM, prog->code_size, prog->code);
741 if (prog->immd_size)
742 nvc0->base.push_data(&nvc0->base,
743 screen->text, prog->immd_base, NOUVEAU_BO_VRAM,
744 prog->immd_size, prog->immd_data);
745
746 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
747 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
748
749 return TRUE;
750 }
751
752 /* Upload code for builtin functions like integer division emulation. */
753 void
754 nvc0_program_library_upload(struct nvc0_context *nvc0)
755 {
756 struct nvc0_screen *screen = nvc0->screen;
757 int ret;
758 uint32_t size;
759 const uint32_t *code;
760
761 if (screen->lib_code)
762 return;
763
764 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
765 if (!size)
766 return;
767
768 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
769 &screen->lib_code);
770 if (ret)
771 return;
772
773 nvc0->base.push_data(&nvc0->base,
774 screen->text, screen->lib_code->start, NOUVEAU_BO_VRAM,
775 size, code);
776 /* no need for a memory barrier, will be emitted with first program */
777 }
778
779 void
780 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
781 {
782 const struct pipe_shader_state pipe = prog->pipe;
783 const ubyte type = prog->type;
784
785 if (prog->mem)
786 nouveau_heap_free(&prog->mem);
787 if (prog->code)
788 FREE(prog->code); /* may be 0 for hardcoded shaders */
789 FREE(prog->immd_data);
790 FREE(prog->relocs);
791 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
792 FREE(prog->cp.syms);
793 if (prog->tfb) {
794 if (nvc0->state.tfb == prog->tfb)
795 nvc0->state.tfb = NULL;
796 FREE(prog->tfb);
797 }
798
799 memset(prog, 0, sizeof(*prog));
800
801 prog->pipe = pipe;
802 prog->type = type;
803 }
804
805 uint32_t
806 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
807 {
808 const struct nv50_ir_prog_symbol *syms =
809 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
810 unsigned base = 0;
811 unsigned i;
812 if (prog->type != PIPE_SHADER_COMPUTE)
813 base = NVC0_SHADER_HEADER_SIZE;
814 for (i = 0; i < prog->cp.num_syms; ++i)
815 if (syms[i].label == label)
816 return prog->code_base + base + syms[i].offset;
817 return prog->code_base; /* no symbols or symbol not found */
818 }