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667fbc893230d91fae0c4ddc1a3394998b33810a
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "nvc0/nvc0_context.h"
26
27 #include "codegen/nv50_ir_driver.h"
28 #include "nvc0/nve4_compute.h"
29
30 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
31 * 124 scalar varying values.
32 */
33 static uint32_t
34 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
35 {
36 switch (sn) {
37 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
38 case TGSI_SEMANTIC_PRIMID: return 0x060;
39 case TGSI_SEMANTIC_PSIZE: return 0x06c;
40 case TGSI_SEMANTIC_POSITION: return 0x070;
41 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
42 case TGSI_SEMANTIC_FOG: return 0x2e8;
43 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
44 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
45 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
46 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
47 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
48 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
49 case NV50_SEMANTIC_TESSCOORD: return 0x2f0;
50 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
51 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
52 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
53 case TGSI_SEMANTIC_FACE: return 0x3fc;
54 default:
55 assert(!"invalid TGSI input semantic");
56 return ~0;
57 }
58 }
59
60 static uint32_t
61 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
62 {
63 switch (sn) {
64 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
65 case TGSI_SEMANTIC_PRIMID: return 0x060;
66 case TGSI_SEMANTIC_LAYER: return 0x064;
67 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
68 case TGSI_SEMANTIC_PSIZE: return 0x06c;
69 case TGSI_SEMANTIC_POSITION: return 0x070;
70 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
71 case TGSI_SEMANTIC_FOG: return 0x2e8;
72 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
73 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
74 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
75 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
76 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
77 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
78 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
79 default:
80 assert(!"invalid TGSI output semantic");
81 return ~0;
82 }
83 }
84
85 static int
86 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
87 {
88 unsigned i, c, n;
89
90 for (n = 0, i = 0; i < info->numInputs; ++i) {
91 switch (info->in[i].sn) {
92 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
93 case TGSI_SEMANTIC_VERTEXID:
94 info->in[i].mask = 0x1;
95 info->in[i].slot[0] =
96 nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
97 continue;
98 default:
99 break;
100 }
101 for (c = 0; c < 4; ++c)
102 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
103 ++n;
104 }
105
106 return 0;
107 }
108
109 static int
110 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
111 {
112 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
113 unsigned offset;
114 unsigned i, c;
115
116 for (i = 0; i < info->numInputs; ++i) {
117 offset = nvc0_shader_input_address(info->in[i].sn,
118 info->in[i].si, ubase);
119 if (info->in[i].patch && offset >= 0x20)
120 offset = 0x20 + info->in[i].si * 0x10;
121
122 if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
123 info->in[i].mask &= 3;
124
125 for (c = 0; c < 4; ++c)
126 info->in[i].slot[c] = (offset + c * 0x4) / 4;
127 }
128
129 return 0;
130 }
131
132 static int
133 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
134 {
135 unsigned count = info->prop.fp.numColourResults * 4;
136 unsigned i, c;
137
138 for (i = 0; i < info->numOutputs; ++i)
139 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
140 for (c = 0; c < 4; ++c)
141 info->out[i].slot[c] = info->out[i].si * 4 + c;
142
143 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
144 info->out[info->io.sampleMask].slot[0] = count++;
145 else
146 if (info->target >= 0xe0)
147 count++; /* on Kepler, depth is always last colour reg + 2 */
148
149 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
150 info->out[info->io.fragDepth].slot[2] = count;
151
152 return 0;
153 }
154
155 static int
156 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
157 {
158 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
159 unsigned offset;
160 unsigned i, c;
161
162 for (i = 0; i < info->numOutputs; ++i) {
163 offset = nvc0_shader_output_address(info->out[i].sn,
164 info->out[i].si, ubase);
165 if (info->out[i].patch && offset >= 0x20)
166 offset = 0x20 + info->out[i].si * 0x10;
167
168 for (c = 0; c < 4; ++c)
169 info->out[i].slot[c] = (offset + c * 0x4) / 4;
170 }
171
172 return 0;
173 }
174
175 static int
176 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
177 {
178 int ret;
179
180 if (info->type == PIPE_SHADER_VERTEX)
181 ret = nvc0_vp_assign_input_slots(info);
182 else
183 ret = nvc0_sp_assign_input_slots(info);
184 if (ret)
185 return ret;
186
187 if (info->type == PIPE_SHADER_FRAGMENT)
188 ret = nvc0_fp_assign_output_slots(info);
189 else
190 ret = nvc0_sp_assign_output_slots(info);
191 return ret;
192 }
193
194 static INLINE void
195 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
196 {
197 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
198 uint8_t max = (vp->hdr[4] >> 24);
199
200 min = MIN2(min, slot);
201 max = MAX2(max, slot);
202
203 vp->hdr[4] = (max << 24) | (min << 12);
204 }
205
206 /* Common part of header generation for VP, TCP, TEP and GP. */
207 static int
208 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
209 {
210 unsigned i, c, a;
211
212 for (i = 0; i < info->numInputs; ++i) {
213 if (info->in[i].patch)
214 continue;
215 for (c = 0; c < 4; ++c) {
216 a = info->in[i].slot[c];
217 if (info->in[i].mask & (1 << c)) {
218 if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
219 vp->hdr[5 + a / 32] |= 1 << (a % 32);
220 else
221 nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
222 }
223 }
224 }
225
226 for (i = 0; i < info->numOutputs; ++i) {
227 if (info->out[i].patch)
228 continue;
229 for (c = 0; c < 4; ++c) {
230 if (!(info->out[i].mask & (1 << c)))
231 continue;
232 assert(info->out[i].slot[c] >= 0x40 / 4);
233 a = info->out[i].slot[c] - 0x40 / 4;
234 vp->hdr[13 + a / 32] |= 1 << (a % 32);
235 if (info->out[i].oread)
236 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
237 }
238 }
239
240 for (i = 0; i < info->numSysVals; ++i) {
241 switch (info->sv[i].sn) {
242 case TGSI_SEMANTIC_PRIMID:
243 vp->hdr[5] |= 1 << 24;
244 break;
245 case TGSI_SEMANTIC_INSTANCEID:
246 vp->hdr[10] |= 1 << 30;
247 break;
248 case TGSI_SEMANTIC_VERTEXID:
249 vp->hdr[10] |= 1 << 31;
250 break;
251 default:
252 break;
253 }
254 }
255
256 vp->vp.clip_enable = info->io.clipDistanceMask;
257 for (i = 0; i < 8; ++i)
258 if (info->io.cullDistanceMask & (1 << i))
259 vp->vp.clip_mode |= 1 << (i * 4);
260
261 if (info->io.genUserClip < 0)
262 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
263
264 return 0;
265 }
266
267 static int
268 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
269 {
270 vp->hdr[0] = 0x20061 | (1 << 10);
271 vp->hdr[4] = 0xff000;
272
273 vp->hdr[18] = info->io.clipDistanceMask;
274
275 return nvc0_vtgp_gen_header(vp, info);
276 }
277
278 #if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
279 static void
280 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
281 {
282 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
283 tp->tp.tess_mode = ~0;
284 return;
285 }
286 switch (info->prop.tp.domain) {
287 case PIPE_PRIM_LINES:
288 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
289 break;
290 case PIPE_PRIM_TRIANGLES:
291 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
292 if (info->prop.tp.winding > 0)
293 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
294 break;
295 case PIPE_PRIM_QUADS:
296 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
297 break;
298 default:
299 tp->tp.tess_mode = ~0;
300 return;
301 }
302 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
303 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
304
305 switch (info->prop.tp.partitioning) {
306 case PIPE_TESS_PART_INTEGER:
307 case PIPE_TESS_PART_POW2:
308 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
309 break;
310 case PIPE_TESS_PART_FRACT_ODD:
311 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
312 break;
313 case PIPE_TESS_PART_FRACT_EVEN:
314 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
315 break;
316 default:
317 assert(!"invalid tessellator partitioning");
318 break;
319 }
320 }
321 #endif
322
323 #ifdef PIPE_SHADER_HULL
324 static int
325 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
326 {
327 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
328
329 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
330
331 if (info->numPatchConstants)
332 opcs = 8 + info->numPatchConstants * 4;
333
334 tcp->hdr[0] = 0x20061 | (2 << 10);
335
336 tcp->hdr[1] = opcs << 24;
337 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
338
339 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
340
341 nvc0_vtgp_gen_header(tcp, info);
342
343 nvc0_tp_get_tess_mode(tcp, info);
344
345 return 0;
346 }
347 #endif
348
349 #ifdef PIPE_SHADER_DOMAIN
350 static int
351 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
352 {
353 tep->tp.input_patch_size = ~0;
354
355 tep->hdr[0] = 0x20061 | (3 << 10);
356 tep->hdr[4] = 0xff000;
357
358 nvc0_vtgp_gen_header(tep, info);
359
360 nvc0_tp_get_tess_mode(tep, info);
361
362 tep->hdr[18] |= 0x3 << 12; /* ? */
363
364 return 0;
365 }
366 #endif
367
368 static int
369 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
370 {
371 gp->hdr[0] = 0x20061 | (4 << 10);
372
373 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
374
375 switch (info->prop.gp.outputPrim) {
376 case PIPE_PRIM_POINTS:
377 gp->hdr[3] = 0x01000000;
378 gp->hdr[0] |= 0xf0000000;
379 break;
380 case PIPE_PRIM_LINE_STRIP:
381 gp->hdr[3] = 0x06000000;
382 gp->hdr[0] |= 0x10000000;
383 break;
384 case PIPE_PRIM_TRIANGLE_STRIP:
385 gp->hdr[3] = 0x07000000;
386 gp->hdr[0] |= 0x10000000;
387 break;
388 default:
389 assert(0);
390 break;
391 }
392
393 gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff;
394
395 return nvc0_vtgp_gen_header(gp, info);
396 }
397
398 #define NVC0_INTERP_FLAT (1 << 0)
399 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
400 #define NVC0_INTERP_LINEAR (3 << 0)
401 #define NVC0_INTERP_CENTROID (1 << 2)
402
403 static uint8_t
404 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
405 {
406 if (var->linear)
407 return NVC0_INTERP_LINEAR;
408 if (var->flat)
409 return NVC0_INTERP_FLAT;
410 return NVC0_INTERP_PERSPECTIVE;
411 }
412
413 static int
414 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
415 {
416 unsigned i, c, a, m;
417
418 /* just 00062 on Kepler */
419 fp->hdr[0] = 0x20062 | (5 << 10);
420 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
421
422 if (info->prop.fp.usesDiscard)
423 fp->hdr[0] |= 0x8000;
424 if (info->prop.fp.numColourResults > 1)
425 fp->hdr[0] |= 0x4000;
426 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
427 fp->hdr[19] |= 0x1;
428 if (info->prop.fp.writesDepth) {
429 fp->hdr[19] |= 0x2;
430 fp->flags[0] = 0x11; /* deactivate ZCULL */
431 }
432
433 for (i = 0; i < info->numInputs; ++i) {
434 m = nvc0_hdr_interp_mode(&info->in[i]);
435 for (c = 0; c < 4; ++c) {
436 if (!(info->in[i].mask & (1 << c)))
437 continue;
438 a = info->in[i].slot[c];
439 if (info->in[i].slot[0] >= (0x060 / 4) &&
440 info->in[i].slot[0] <= (0x07c / 4)) {
441 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
442 } else
443 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
444 info->in[i].slot[0] <= (0x2fc / 4)) {
445 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
446 } else {
447 if (info->in[i].slot[c] < (0x040 / 4) ||
448 info->in[i].slot[c] > (0x380 / 4))
449 continue;
450 a *= 2;
451 if (info->in[i].slot[0] >= (0x300 / 4))
452 a -= 32;
453 fp->hdr[4 + a / 32] |= m << (a % 32);
454 }
455 }
456 }
457
458 for (i = 0; i < info->numOutputs; ++i) {
459 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
460 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
461 }
462
463 fp->fp.early_z = info->prop.fp.earlyFragTests;
464
465 return 0;
466 }
467
468 static struct nvc0_transform_feedback_state *
469 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
470 const struct pipe_stream_output_info *pso)
471 {
472 struct nvc0_transform_feedback_state *tfb;
473 unsigned b, i, c;
474
475 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
476 if (!tfb)
477 return NULL;
478 for (b = 0; b < 4; ++b) {
479 tfb->stride[b] = pso->stride[b] * 4;
480 tfb->varying_count[b] = 0;
481 }
482 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
483
484 for (i = 0; i < pso->num_outputs; ++i) {
485 unsigned s = pso->output[i].start_component;
486 unsigned p = pso->output[i].dst_offset;
487 b = pso->output[i].output_buffer;
488
489 for (c = 0; c < pso->output[i].num_components; ++c)
490 tfb->varying_index[b][p++] =
491 info->out[pso->output[i].register_index].slot[s + c];
492
493 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
494 }
495 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
496 for (c = tfb->varying_count[b]; c & 3; ++c)
497 tfb->varying_index[b][c] = 0;
498
499 return tfb;
500 }
501
502 #ifdef DEBUG
503 static void
504 nvc0_program_dump(struct nvc0_program *prog)
505 {
506 unsigned pos;
507
508 if (prog->type != PIPE_SHADER_COMPUTE) {
509 for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
510 debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
511 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
512 }
513 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
514 for (pos = 0; pos < prog->code_size / 4; ++pos) {
515 if ((pos % 8) == 0)
516 debug_printf("\n");
517 debug_printf("%08x ", prog->code[pos]);
518 }
519 debug_printf("\n");
520 }
521 #endif
522
523 boolean
524 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
525 {
526 struct nv50_ir_prog_info *info;
527 int ret;
528
529 info = CALLOC_STRUCT(nv50_ir_prog_info);
530 if (!info)
531 return FALSE;
532
533 info->type = prog->type;
534 info->target = chipset;
535 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
536 info->bin.source = (void *)prog->pipe.tokens;
537
538 info->io.genUserClip = prog->vp.num_ucps;
539 info->io.ucpBase = 256;
540 info->io.ucpCBSlot = 15;
541 info->io.sampleInterp = prog->fp.sample_interp;
542
543 if (prog->type == PIPE_SHADER_COMPUTE) {
544 if (chipset >= NVISA_GK104_CHIPSET) {
545 info->io.resInfoCBSlot = 0;
546 info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
547 info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
548 info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
549 }
550 info->io.msInfoCBSlot = 0;
551 info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
552 } else {
553 if (chipset >= NVISA_GK104_CHIPSET) {
554 info->io.texBindBase = 0x20;
555 info->io.suInfoBase = 0; /* TODO */
556 }
557 info->io.resInfoCBSlot = 15;
558 info->io.sampleInfoBase = 256 + 128;
559 info->io.msInfoCBSlot = 15;
560 info->io.msInfoBase = 0; /* TODO */
561 }
562
563 info->assignSlots = nvc0_program_assign_varying_slots;
564
565 #ifdef DEBUG
566 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
567 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
568 #else
569 info->optLevel = 3;
570 #endif
571
572 ret = nv50_ir_generate_code(info);
573 if (ret) {
574 NOUVEAU_ERR("shader translation failed: %i\n", ret);
575 goto out;
576 }
577 if (prog->type != PIPE_SHADER_COMPUTE)
578 FREE(info->bin.syms);
579
580 prog->code = info->bin.code;
581 prog->code_size = info->bin.codeSize;
582 prog->immd_data = info->immd.buf;
583 prog->immd_size = info->immd.bufSize;
584 prog->relocs = info->bin.relocData;
585 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
586 prog->num_barriers = info->numBarriers;
587
588 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
589
590 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
591 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
592 prog->vp.edgeflag = info->io.edgeFlagIn;
593
594 switch (prog->type) {
595 case PIPE_SHADER_VERTEX:
596 ret = nvc0_vp_gen_header(prog, info);
597 break;
598 #ifdef PIPE_SHADER_HULL
599 case PIPE_SHADER_HULL:
600 ret = nvc0_tcp_gen_header(prog, info);
601 break;
602 #endif
603 #ifdef PIPE_SHADER_DOMAIN
604 case PIPE_SHADER_DOMAIN:
605 ret = nvc0_tep_gen_header(prog, info);
606 break;
607 #endif
608 case PIPE_SHADER_GEOMETRY:
609 ret = nvc0_gp_gen_header(prog, info);
610 break;
611 case PIPE_SHADER_FRAGMENT:
612 ret = nvc0_fp_gen_header(prog, info);
613 break;
614 case PIPE_SHADER_COMPUTE:
615 prog->cp.syms = info->bin.syms;
616 prog->cp.num_syms = info->bin.numSyms;
617 break;
618 default:
619 ret = -1;
620 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
621 break;
622 }
623 if (ret)
624 goto out;
625
626 if (info->bin.tlsSpace) {
627 assert(info->bin.tlsSpace < (1 << 24));
628 prog->hdr[0] |= 1 << 26;
629 prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
630 prog->need_tls = TRUE;
631 }
632 /* TODO: factor 2 only needed where joinat/precont is used,
633 * and we only have to count non-uniform branches
634 */
635 /*
636 if ((info->maxCFDepth * 2) > 16) {
637 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
638 prog->need_tls = TRUE;
639 }
640 */
641 if (info->io.globalAccess)
642 prog->hdr[0] |= 1 << 16;
643
644 if (prog->pipe.stream_output.num_outputs)
645 prog->tfb = nvc0_program_create_tfb_state(info,
646 &prog->pipe.stream_output);
647
648 out:
649 FREE(info);
650 return !ret;
651 }
652
653 boolean
654 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
655 {
656 struct nvc0_screen *screen = nvc0->screen;
657 const boolean is_cp = prog->type == PIPE_SHADER_COMPUTE;
658 int ret;
659 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
660 uint32_t lib_pos = screen->lib_code->start;
661 uint32_t code_pos;
662
663 /* c[] bindings need to be aligned to 0x100, but we could use relocations
664 * to save space. */
665 if (prog->immd_size) {
666 prog->immd_base = size;
667 size = align(size, 0x40);
668 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
669 }
670 /* On Fermi, SP_START_ID must be aligned to 0x40.
671 * On Kepler, the first instruction must be aligned to 0x80 because
672 * latency information is expected only at certain positions.
673 */
674 if (screen->base.class_3d >= NVE4_3D_CLASS)
675 size = size + (is_cp ? 0x40 : 0x70);
676 size = align(size, 0x40);
677
678 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
679 if (ret) {
680 struct nouveau_heap *heap = screen->text_heap;
681 struct nouveau_heap *iter;
682 for (iter = heap; iter && iter->next != heap; iter = iter->next) {
683 struct nvc0_program *evict = iter->priv;
684 if (evict)
685 nouveau_heap_free(&evict->mem);
686 }
687 debug_printf("WARNING: out of code space, evicting all shaders.\n");
688 ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
689 if (ret) {
690 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
691 return FALSE;
692 }
693 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
694 }
695 prog->code_base = prog->mem->start;
696 prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
697 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
698 prog->mem->start + prog->mem->size));
699
700 if (!is_cp) {
701 if (screen->base.class_3d >= NVE4_3D_CLASS) {
702 switch (prog->mem->start & 0xff) {
703 case 0x40: prog->code_base += 0x70; break;
704 case 0x80: prog->code_base += 0x30; break;
705 case 0xc0: prog->code_base += 0x70; break;
706 default:
707 prog->code_base += 0x30;
708 assert((prog->mem->start & 0xff) == 0x00);
709 break;
710 }
711 }
712 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
713 } else {
714 if (screen->base.class_3d >= NVE4_3D_CLASS) {
715 if (prog->mem->start & 0x40)
716 prog->code_base += 0x40;
717 assert((prog->code_base & 0x7f) == 0x00);
718 }
719 code_pos = prog->code_base;
720 }
721
722 if (prog->relocs)
723 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
724
725 #ifdef DEBUG
726 if (debug_get_bool_option("NV50_PROG_DEBUG", FALSE))
727 nvc0_program_dump(prog);
728 #endif
729
730 if (!is_cp)
731 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
732 NOUVEAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr);
733 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
734 NOUVEAU_BO_VRAM, prog->code_size, prog->code);
735 if (prog->immd_size)
736 nvc0->base.push_data(&nvc0->base,
737 screen->text, prog->immd_base, NOUVEAU_BO_VRAM,
738 prog->immd_size, prog->immd_data);
739
740 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
741 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
742
743 return TRUE;
744 }
745
746 /* Upload code for builtin functions like integer division emulation. */
747 void
748 nvc0_program_library_upload(struct nvc0_context *nvc0)
749 {
750 struct nvc0_screen *screen = nvc0->screen;
751 int ret;
752 uint32_t size;
753 const uint32_t *code;
754
755 if (screen->lib_code)
756 return;
757
758 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
759 if (!size)
760 return;
761
762 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
763 &screen->lib_code);
764 if (ret)
765 return;
766
767 nvc0->base.push_data(&nvc0->base,
768 screen->text, screen->lib_code->start, NOUVEAU_BO_VRAM,
769 size, code);
770 /* no need for a memory barrier, will be emitted with first program */
771 }
772
773 void
774 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
775 {
776 const struct pipe_shader_state pipe = prog->pipe;
777 const ubyte type = prog->type;
778
779 if (prog->mem)
780 nouveau_heap_free(&prog->mem);
781 if (prog->code)
782 FREE(prog->code); /* may be 0 for hardcoded shaders */
783 FREE(prog->immd_data);
784 FREE(prog->relocs);
785 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
786 FREE(prog->cp.syms);
787 if (prog->tfb) {
788 if (nvc0->state.tfb == prog->tfb)
789 nvc0->state.tfb = NULL;
790 FREE(prog->tfb);
791 }
792
793 memset(prog, 0, sizeof(*prog));
794
795 prog->pipe = pipe;
796 prog->type = type;
797 }
798
799 uint32_t
800 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
801 {
802 const struct nv50_ir_prog_symbol *syms =
803 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
804 unsigned base = 0;
805 unsigned i;
806 if (prog->type != PIPE_SHADER_COMPUTE)
807 base = NVC0_SHADER_HEADER_SIZE;
808 for (i = 0; i < prog->cp.num_syms; ++i)
809 if (syms[i].label == label)
810 return prog->code_base + base + syms[i].offset;
811 return prog->code_base; /* no symbols or symbol not found */
812 }