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nvc0: change ACQUIRE_EQUAL to ACQUIRE_GEQUAL in nvc0_hw_query_fifo_wait
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "tgsi/tgsi_ureg.h"
26
27 #include "nvc0/nvc0_context.h"
28
29 #include "codegen/nv50_ir_driver.h"
30 #include "nvc0/nve4_compute.h"
31
32 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
33 * 124 scalar varying values.
34 */
35 static uint32_t
36 nvc0_shader_input_address(unsigned sn, unsigned si)
37 {
38 switch (sn) {
39 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
40 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
41 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
42 case TGSI_SEMANTIC_PRIMID: return 0x060;
43 case TGSI_SEMANTIC_LAYER: return 0x064;
44 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
45 case TGSI_SEMANTIC_PSIZE: return 0x06c;
46 case TGSI_SEMANTIC_POSITION: return 0x070;
47 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
48 case TGSI_SEMANTIC_FOG: return 0x2e8;
49 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
50 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
51 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
52 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
53 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
54 case TGSI_SEMANTIC_TESSCOORD: return 0x2f0;
55 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
56 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
57 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
58 default:
59 assert(!"invalid TGSI input semantic");
60 return ~0;
61 }
62 }
63
64 static uint32_t
65 nvc0_shader_output_address(unsigned sn, unsigned si)
66 {
67 switch (sn) {
68 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
69 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
70 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
71 case TGSI_SEMANTIC_PRIMID: return 0x060;
72 case TGSI_SEMANTIC_LAYER: return 0x064;
73 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
74 case TGSI_SEMANTIC_PSIZE: return 0x06c;
75 case TGSI_SEMANTIC_POSITION: return 0x070;
76 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
77 case TGSI_SEMANTIC_FOG: return 0x2e8;
78 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
79 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
80 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
81 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
82 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
83 /* case TGSI_SEMANTIC_VIEWPORT_MASK: return 0x3a0; */
84 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
85 default:
86 assert(!"invalid TGSI output semantic");
87 return ~0;
88 }
89 }
90
91 static int
92 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
93 {
94 unsigned i, c, n;
95
96 for (n = 0, i = 0; i < info->numInputs; ++i) {
97 switch (info->in[i].sn) {
98 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
99 case TGSI_SEMANTIC_VERTEXID:
100 info->in[i].mask = 0x1;
101 info->in[i].slot[0] =
102 nvc0_shader_input_address(info->in[i].sn, 0) / 4;
103 continue;
104 default:
105 break;
106 }
107 for (c = 0; c < 4; ++c)
108 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
109 ++n;
110 }
111
112 return 0;
113 }
114
115 static int
116 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
117 {
118 unsigned offset;
119 unsigned i, c;
120
121 for (i = 0; i < info->numInputs; ++i) {
122 offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
123
124 for (c = 0; c < 4; ++c)
125 info->in[i].slot[c] = (offset + c * 0x4) / 4;
126 }
127
128 return 0;
129 }
130
131 static int
132 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
133 {
134 unsigned count = info->prop.fp.numColourResults * 4;
135 unsigned i, c;
136
137 /* Compute the relative position of each color output, since skipped MRT
138 * positions will not have registers allocated to them.
139 */
140 unsigned colors[8] = {0};
141 for (i = 0; i < info->numOutputs; ++i)
142 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
143 colors[info->out[i].si] = 1;
144 for (i = 0, c = 0; i < 8; i++)
145 if (colors[i])
146 colors[i] = c++;
147 for (i = 0; i < info->numOutputs; ++i)
148 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
149 for (c = 0; c < 4; ++c)
150 info->out[i].slot[c] = colors[info->out[i].si] * 4 + c;
151
152 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
153 info->out[info->io.sampleMask].slot[0] = count++;
154 else
155 if (info->target >= 0xe0)
156 count++; /* on Kepler, depth is always last colour reg + 2 */
157
158 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
159 info->out[info->io.fragDepth].slot[2] = count;
160
161 return 0;
162 }
163
164 static int
165 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
166 {
167 unsigned offset;
168 unsigned i, c;
169
170 for (i = 0; i < info->numOutputs; ++i) {
171 offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
172
173 for (c = 0; c < 4; ++c)
174 info->out[i].slot[c] = (offset + c * 0x4) / 4;
175 }
176
177 return 0;
178 }
179
180 static int
181 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
182 {
183 int ret;
184
185 if (info->type == PIPE_SHADER_VERTEX)
186 ret = nvc0_vp_assign_input_slots(info);
187 else
188 ret = nvc0_sp_assign_input_slots(info);
189 if (ret)
190 return ret;
191
192 if (info->type == PIPE_SHADER_FRAGMENT)
193 ret = nvc0_fp_assign_output_slots(info);
194 else
195 ret = nvc0_sp_assign_output_slots(info);
196 return ret;
197 }
198
199 static inline void
200 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
201 {
202 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
203 uint8_t max = (vp->hdr[4] >> 24);
204
205 min = MIN2(min, slot);
206 max = MAX2(max, slot);
207
208 vp->hdr[4] = (max << 24) | (min << 12);
209 }
210
211 /* Common part of header generation for VP, TCP, TEP and GP. */
212 static int
213 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
214 {
215 unsigned i, c, a;
216
217 for (i = 0; i < info->numInputs; ++i) {
218 if (info->in[i].patch)
219 continue;
220 for (c = 0; c < 4; ++c) {
221 a = info->in[i].slot[c];
222 if (info->in[i].mask & (1 << c))
223 vp->hdr[5 + a / 32] |= 1 << (a % 32);
224 }
225 }
226
227 for (i = 0; i < info->numOutputs; ++i) {
228 if (info->out[i].patch)
229 continue;
230 for (c = 0; c < 4; ++c) {
231 if (!(info->out[i].mask & (1 << c)))
232 continue;
233 assert(info->out[i].slot[c] >= 0x40 / 4);
234 a = info->out[i].slot[c] - 0x40 / 4;
235 vp->hdr[13 + a / 32] |= 1 << (a % 32);
236 if (info->out[i].oread)
237 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
238 }
239 }
240
241 for (i = 0; i < info->numSysVals; ++i) {
242 switch (info->sv[i].sn) {
243 case TGSI_SEMANTIC_PRIMID:
244 vp->hdr[5] |= 1 << 24;
245 break;
246 case TGSI_SEMANTIC_INSTANCEID:
247 vp->hdr[10] |= 1 << 30;
248 break;
249 case TGSI_SEMANTIC_VERTEXID:
250 vp->hdr[10] |= 1 << 31;
251 break;
252 case TGSI_SEMANTIC_TESSCOORD:
253 /* We don't have the mask, nor the slots populated. While this could
254 * be achieved, the vast majority of the time if either of the coords
255 * are read, then both will be read.
256 */
257 nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
258 nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
259 break;
260 default:
261 break;
262 }
263 }
264
265 vp->vp.clip_enable = (1 << info->io.clipDistances) - 1;
266 vp->vp.cull_enable =
267 ((1 << info->io.cullDistances) - 1) << info->io.clipDistances;
268 for (i = 0; i < info->io.cullDistances; ++i)
269 vp->vp.clip_mode |= 1 << ((info->io.clipDistances + i) * 4);
270
271 if (info->io.genUserClip < 0)
272 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
273
274 return 0;
275 }
276
277 static int
278 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
279 {
280 vp->hdr[0] = 0x20061 | (1 << 10);
281 vp->hdr[4] = 0xff000;
282
283 return nvc0_vtgp_gen_header(vp, info);
284 }
285
286 static void
287 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
288 {
289 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
290 tp->tp.tess_mode = ~0;
291 return;
292 }
293 switch (info->prop.tp.domain) {
294 case PIPE_PRIM_LINES:
295 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
296 break;
297 case PIPE_PRIM_TRIANGLES:
298 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
299 break;
300 case PIPE_PRIM_QUADS:
301 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
302 break;
303 default:
304 tp->tp.tess_mode = ~0;
305 return;
306 }
307
308 /* It seems like lines want the "CW" bit to indicate they're connected, and
309 * spit out errors in dmesg when the "CONNECTED" bit is set.
310 */
311 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS) {
312 if (info->prop.tp.domain == PIPE_PRIM_LINES)
313 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
314 else
315 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
316 }
317
318 /* Winding only matters for triangles/quads, not lines. */
319 if (info->prop.tp.domain != PIPE_PRIM_LINES &&
320 info->prop.tp.outputPrim != PIPE_PRIM_POINTS &&
321 info->prop.tp.winding > 0)
322 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
323
324 switch (info->prop.tp.partitioning) {
325 case PIPE_TESS_SPACING_EQUAL:
326 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
327 break;
328 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
329 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
330 break;
331 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
332 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
333 break;
334 default:
335 assert(!"invalid tessellator partitioning");
336 break;
337 }
338 }
339
340 static int
341 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
342 {
343 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
344
345 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
346
347 if (info->numPatchConstants)
348 opcs = 8 + info->numPatchConstants * 4;
349
350 tcp->hdr[0] = 0x20061 | (2 << 10);
351
352 tcp->hdr[1] = opcs << 24;
353 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
354
355 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
356
357 nvc0_vtgp_gen_header(tcp, info);
358
359 if (info->target >= NVISA_GM107_CHIPSET) {
360 /* On GM107+, the number of output patch components has moved in the TCP
361 * header, but it seems like blob still also uses the old position.
362 * Also, the high 8-bits are located inbetween the min/max parallel
363 * field and has to be set after updating the outputs. */
364 tcp->hdr[3] = (opcs & 0x0f) << 28;
365 tcp->hdr[4] |= (opcs & 0xf0) << 16;
366 }
367
368 nvc0_tp_get_tess_mode(tcp, info);
369
370 return 0;
371 }
372
373 static int
374 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
375 {
376 tep->tp.input_patch_size = ~0;
377
378 tep->hdr[0] = 0x20061 | (3 << 10);
379 tep->hdr[4] = 0xff000;
380
381 nvc0_vtgp_gen_header(tep, info);
382
383 nvc0_tp_get_tess_mode(tep, info);
384
385 tep->hdr[18] |= 0x3 << 12; /* ? */
386
387 return 0;
388 }
389
390 static int
391 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
392 {
393 gp->hdr[0] = 0x20061 | (4 << 10);
394
395 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
396
397 switch (info->prop.gp.outputPrim) {
398 case PIPE_PRIM_POINTS:
399 gp->hdr[3] = 0x01000000;
400 gp->hdr[0] |= 0xf0000000;
401 break;
402 case PIPE_PRIM_LINE_STRIP:
403 gp->hdr[3] = 0x06000000;
404 gp->hdr[0] |= 0x10000000;
405 break;
406 case PIPE_PRIM_TRIANGLE_STRIP:
407 gp->hdr[3] = 0x07000000;
408 gp->hdr[0] |= 0x10000000;
409 break;
410 default:
411 assert(0);
412 break;
413 }
414
415 gp->hdr[4] = CLAMP(info->prop.gp.maxVertices, 1, 1024);
416
417 return nvc0_vtgp_gen_header(gp, info);
418 }
419
420 #define NVC0_INTERP_FLAT (1 << 0)
421 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
422 #define NVC0_INTERP_LINEAR (3 << 0)
423 #define NVC0_INTERP_CENTROID (1 << 2)
424
425 static uint8_t
426 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
427 {
428 if (var->linear)
429 return NVC0_INTERP_LINEAR;
430 if (var->flat)
431 return NVC0_INTERP_FLAT;
432 return NVC0_INTERP_PERSPECTIVE;
433 }
434
435 static int
436 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
437 {
438 unsigned i, c, a, m;
439
440 /* just 00062 on Kepler */
441 fp->hdr[0] = 0x20062 | (5 << 10);
442 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
443
444 if (info->prop.fp.usesDiscard)
445 fp->hdr[0] |= 0x8000;
446 if (info->prop.fp.numColourResults > 1)
447 fp->hdr[0] |= 0x4000;
448 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
449 fp->hdr[19] |= 0x1;
450 if (info->prop.fp.writesDepth) {
451 fp->hdr[19] |= 0x2;
452 fp->flags[0] = 0x11; /* deactivate ZCULL */
453 }
454
455 for (i = 0; i < info->numInputs; ++i) {
456 m = nvc0_hdr_interp_mode(&info->in[i]);
457 if (info->in[i].sn == TGSI_SEMANTIC_COLOR) {
458 fp->fp.colors |= 1 << info->in[i].si;
459 if (info->in[i].sc)
460 fp->fp.color_interp[info->in[i].si] = m | (info->in[i].mask << 4);
461 }
462 for (c = 0; c < 4; ++c) {
463 if (!(info->in[i].mask & (1 << c)))
464 continue;
465 a = info->in[i].slot[c];
466 if (info->in[i].slot[0] >= (0x060 / 4) &&
467 info->in[i].slot[0] <= (0x07c / 4)) {
468 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
469 } else
470 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
471 info->in[i].slot[0] <= (0x2fc / 4)) {
472 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
473 } else {
474 if (info->in[i].slot[c] < (0x040 / 4) ||
475 info->in[i].slot[c] > (0x380 / 4))
476 continue;
477 a *= 2;
478 if (info->in[i].slot[0] >= (0x300 / 4))
479 a -= 32;
480 fp->hdr[4 + a / 32] |= m << (a % 32);
481 }
482 }
483 }
484
485 for (i = 0; i < info->numOutputs; ++i) {
486 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
487 fp->hdr[18] |= 0xf << (4 * info->out[i].si);
488 }
489
490 /* There are no "regular" attachments, but the shader still needs to be
491 * executed. It seems like it wants to think that it has some color
492 * outputs in order to actually run.
493 */
494 if (info->prop.fp.numColourResults == 0 && !info->prop.fp.writesDepth)
495 fp->hdr[18] |= 0xf;
496
497 fp->fp.early_z = info->prop.fp.earlyFragTests;
498 fp->fp.sample_mask_in = info->prop.fp.usesSampleMaskIn;
499 fp->fp.reads_framebuffer = info->prop.fp.readsFramebuffer;
500 fp->fp.post_depth_coverage = info->prop.fp.postDepthCoverage;
501
502 /* Mark position xy and layer as read */
503 if (fp->fp.reads_framebuffer)
504 fp->hdr[5] |= 0x32000000;
505
506 return 0;
507 }
508
509 static struct nvc0_transform_feedback_state *
510 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
511 const struct pipe_stream_output_info *pso)
512 {
513 struct nvc0_transform_feedback_state *tfb;
514 unsigned b, i, c;
515
516 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
517 if (!tfb)
518 return NULL;
519 for (b = 0; b < 4; ++b) {
520 tfb->stride[b] = pso->stride[b] * 4;
521 tfb->varying_count[b] = 0;
522 }
523 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
524
525 for (i = 0; i < pso->num_outputs; ++i) {
526 unsigned s = pso->output[i].start_component;
527 unsigned p = pso->output[i].dst_offset;
528 const unsigned r = pso->output[i].register_index;
529 b = pso->output[i].output_buffer;
530
531 if (r >= info->numOutputs)
532 continue;
533
534 for (c = 0; c < pso->output[i].num_components; ++c)
535 tfb->varying_index[b][p++] = info->out[r].slot[s + c];
536
537 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
538 tfb->stream[b] = pso->output[i].stream;
539 }
540 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
541 for (c = tfb->varying_count[b]; c & 3; ++c)
542 tfb->varying_index[b][c] = 0;
543
544 return tfb;
545 }
546
547 #ifdef DEBUG
548 static void
549 nvc0_program_dump(struct nvc0_program *prog)
550 {
551 unsigned pos;
552
553 if (prog->type != PIPE_SHADER_COMPUTE) {
554 for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
555 debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
556 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
557 }
558 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
559 for (pos = 0; pos < prog->code_size / 4; ++pos) {
560 if ((pos % 8) == 0)
561 debug_printf("\n");
562 debug_printf("%08x ", prog->code[pos]);
563 }
564 debug_printf("\n");
565 }
566 #endif
567
568 bool
569 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
570 struct pipe_debug_callback *debug)
571 {
572 struct nv50_ir_prog_info *info;
573 int ret;
574
575 info = CALLOC_STRUCT(nv50_ir_prog_info);
576 if (!info)
577 return false;
578
579 info->type = prog->type;
580 info->target = chipset;
581 info->bin.sourceRep = PIPE_SHADER_IR_TGSI;
582 info->bin.source = (void *)prog->pipe.tokens;
583
584 #ifdef DEBUG
585 info->target = debug_get_num_option("NV50_PROG_CHIPSET", chipset);
586 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
587 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
588 info->omitLineNum = debug_get_num_option("NV50_PROG_DEBUG_OMIT_LINENUM", 0);
589 #else
590 info->optLevel = 3;
591 #endif
592
593 info->bin.smemSize = prog->cp.smem_size;
594 info->io.genUserClip = prog->vp.num_ucps;
595 info->io.auxCBSlot = 15;
596 info->io.msInfoCBSlot = 15;
597 info->io.ucpBase = NVC0_CB_AUX_UCP_INFO;
598 info->io.drawInfoBase = NVC0_CB_AUX_DRAW_INFO;
599 info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
600 info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
601 info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
602 if (info->target >= NVISA_GK104_CHIPSET) {
603 info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
604 info->io.fbtexBindBase = NVC0_CB_AUX_FB_TEX_INFO;
605 info->io.bindlessBase = NVC0_CB_AUX_BINDLESS_INFO(0);
606 }
607
608 if (prog->type == PIPE_SHADER_COMPUTE) {
609 if (info->target >= NVISA_GK104_CHIPSET) {
610 info->io.auxCBSlot = 7;
611 info->io.msInfoCBSlot = 7;
612 info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
613 }
614 info->prop.cp.gridInfoBase = NVC0_CB_AUX_GRID_INFO(0);
615 } else {
616 info->io.sampleInfoBase = NVC0_CB_AUX_SAMPLE_INFO;
617 }
618
619 info->assignSlots = nvc0_program_assign_varying_slots;
620
621 ret = nv50_ir_generate_code(info);
622 if (ret) {
623 NOUVEAU_ERR("shader translation failed: %i\n", ret);
624 goto out;
625 }
626 if (prog->type != PIPE_SHADER_COMPUTE)
627 FREE(info->bin.syms);
628
629 prog->code = info->bin.code;
630 prog->code_size = info->bin.codeSize;
631 prog->relocs = info->bin.relocData;
632 prog->fixups = info->bin.fixupData;
633 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
634 prog->cp.smem_size = info->bin.smemSize;
635 prog->num_barriers = info->numBarriers;
636
637 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
638 prog->vp.need_draw_parameters = info->prop.vp.usesDrawParameters;
639
640 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
641 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
642 prog->vp.edgeflag = info->io.edgeFlagIn;
643
644 switch (prog->type) {
645 case PIPE_SHADER_VERTEX:
646 ret = nvc0_vp_gen_header(prog, info);
647 break;
648 case PIPE_SHADER_TESS_CTRL:
649 ret = nvc0_tcp_gen_header(prog, info);
650 break;
651 case PIPE_SHADER_TESS_EVAL:
652 ret = nvc0_tep_gen_header(prog, info);
653 break;
654 case PIPE_SHADER_GEOMETRY:
655 ret = nvc0_gp_gen_header(prog, info);
656 break;
657 case PIPE_SHADER_FRAGMENT:
658 ret = nvc0_fp_gen_header(prog, info);
659 break;
660 case PIPE_SHADER_COMPUTE:
661 prog->cp.syms = info->bin.syms;
662 prog->cp.num_syms = info->bin.numSyms;
663 break;
664 default:
665 ret = -1;
666 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
667 break;
668 }
669 if (ret)
670 goto out;
671
672 if (info->bin.tlsSpace) {
673 assert(info->bin.tlsSpace < (1 << 24));
674 prog->hdr[0] |= 1 << 26;
675 prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
676 prog->need_tls = true;
677 }
678 /* TODO: factor 2 only needed where joinat/precont is used,
679 * and we only have to count non-uniform branches
680 */
681 /*
682 if ((info->maxCFDepth * 2) > 16) {
683 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
684 prog->need_tls = true;
685 }
686 */
687 if (info->io.globalAccess)
688 prog->hdr[0] |= 1 << 26;
689 if (info->io.globalAccess & 0x2)
690 prog->hdr[0] |= 1 << 16;
691 if (info->io.fp64)
692 prog->hdr[0] |= 1 << 27;
693
694 if (prog->pipe.stream_output.num_outputs)
695 prog->tfb = nvc0_program_create_tfb_state(info,
696 &prog->pipe.stream_output);
697
698 pipe_debug_message(debug, SHADER_INFO,
699 "type: %d, local: %d, shared: %d, gpr: %d, inst: %d, bytes: %d",
700 prog->type, info->bin.tlsSpace, info->bin.smemSize,
701 prog->num_gprs, info->bin.instructions,
702 info->bin.codeSize);
703
704 #ifdef DEBUG
705 if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
706 nvc0_program_dump(prog);
707 #endif
708
709 out:
710 FREE(info);
711 return !ret;
712 }
713
714 static inline int
715 nvc0_program_alloc_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
716 {
717 struct nvc0_screen *screen = nvc0->screen;
718 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
719 int ret;
720 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
721
722 /* On Fermi, SP_START_ID must be aligned to 0x40.
723 * On Kepler, the first instruction must be aligned to 0x80 because
724 * latency information is expected only at certain positions.
725 */
726 if (screen->base.class_3d >= NVE4_3D_CLASS)
727 size = size + (is_cp ? 0x40 : 0x70);
728 size = align(size, 0x40);
729
730 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
731 if (ret)
732 return ret;
733 prog->code_base = prog->mem->start;
734
735 if (!is_cp) {
736 if (screen->base.class_3d >= NVE4_3D_CLASS) {
737 switch (prog->mem->start & 0xff) {
738 case 0x40: prog->code_base += 0x70; break;
739 case 0x80: prog->code_base += 0x30; break;
740 case 0xc0: prog->code_base += 0x70; break;
741 default:
742 prog->code_base += 0x30;
743 assert((prog->mem->start & 0xff) == 0x00);
744 break;
745 }
746 }
747 } else {
748 if (screen->base.class_3d >= NVE4_3D_CLASS) {
749 if (prog->mem->start & 0x40)
750 prog->code_base += 0x40;
751 assert((prog->code_base & 0x7f) == 0x00);
752 }
753 }
754
755 return 0;
756 }
757
758 static inline void
759 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
760 {
761 struct nvc0_screen *screen = nvc0->screen;
762 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
763 uint32_t code_pos = prog->code_base + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
764
765 if (prog->relocs)
766 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos,
767 screen->lib_code->start, 0);
768 if (prog->fixups) {
769 nv50_ir_apply_fixups(prog->fixups, prog->code,
770 prog->fp.force_persample_interp,
771 prog->fp.flatshade,
772 0 /* alphatest */);
773 for (int i = 0; i < 2; i++) {
774 unsigned mask = prog->fp.color_interp[i] >> 4;
775 unsigned interp = prog->fp.color_interp[i] & 3;
776 if (!mask)
777 continue;
778 prog->hdr[14] &= ~(0xff << (8 * i));
779 if (prog->fp.flatshade)
780 interp = NVC0_INTERP_FLAT;
781 for (int c = 0; c < 4; c++)
782 if (mask & (1 << c))
783 prog->hdr[14] |= interp << (2 * (4 * i + c));
784 }
785 }
786
787 if (!is_cp)
788 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
789 NV_VRAM_DOMAIN(&screen->base),
790 NVC0_SHADER_HEADER_SIZE, prog->hdr);
791
792 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
793 NV_VRAM_DOMAIN(&screen->base), prog->code_size,
794 prog->code);
795 }
796
797 bool
798 nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog)
799 {
800 struct nvc0_screen *screen = nvc0->screen;
801 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
802 int ret;
803 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
804
805 ret = nvc0_program_alloc_code(nvc0, prog);
806 if (ret) {
807 struct nouveau_heap *heap = screen->text_heap;
808 struct nvc0_program *progs[] = { /* Sorted accordingly to SP_START_ID */
809 nvc0->compprog, nvc0->vertprog, nvc0->tctlprog,
810 nvc0->tevlprog, nvc0->gmtyprog, nvc0->fragprog
811 };
812
813 /* Note that the code library, which is allocated before anything else,
814 * does not have a priv pointer. We can stop once we hit it.
815 */
816 while (heap->next && heap->next->priv) {
817 struct nvc0_program *evict = heap->next->priv;
818 nouveau_heap_free(&evict->mem);
819 }
820 debug_printf("WARNING: out of code space, evicting all shaders.\n");
821
822 /* Make sure to synchronize before deleting the code segment. */
823 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
824
825 if ((screen->text->size << 1) <= (1 << 23)) {
826 ret = nvc0_screen_resize_text_area(screen, screen->text->size << 1);
827 if (ret) {
828 NOUVEAU_ERR("Error allocating TEXT area: %d\n", ret);
829 return false;
830 }
831 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
832 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT,
833 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
834 screen->text);
835 if (screen->compute) {
836 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEXT);
837 BCTX_REFN_bo(nvc0->bufctx_cp, CP_TEXT,
838 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
839 screen->text);
840 }
841
842 /* Re-upload the builtin function into the new code segment. */
843 nvc0_program_library_upload(nvc0);
844 }
845
846 ret = nvc0_program_alloc_code(nvc0, prog);
847 if (ret) {
848 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
849 return false;
850 }
851
852 /* All currently bound shaders have to be reuploaded. */
853 for (int i = 0; i < ARRAY_SIZE(progs); i++) {
854 if (!progs[i] || progs[i] == prog)
855 continue;
856
857 ret = nvc0_program_alloc_code(nvc0, progs[i]);
858 if (ret) {
859 NOUVEAU_ERR("failed to re-upload a shader after code eviction.\n");
860 return false;
861 }
862 nvc0_program_upload_code(nvc0, progs[i]);
863
864 if (progs[i]->type == PIPE_SHADER_COMPUTE) {
865 /* Caches have to be invalidated but the CP_START_ID will be
866 * updated in the launch_grid functions. */
867 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(FLUSH), 1);
868 PUSH_DATA (nvc0->base.pushbuf, NVC0_COMPUTE_FLUSH_CODE);
869 } else {
870 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(SP_START_ID(i)), 1);
871 PUSH_DATA (nvc0->base.pushbuf, progs[i]->code_base);
872 }
873 }
874 }
875
876 nvc0_program_upload_code(nvc0, prog);
877
878 #ifdef DEBUG
879 if (debug_get_bool_option("NV50_PROG_DEBUG", false))
880 nvc0_program_dump(prog);
881 #endif
882
883 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
884 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
885
886 return true;
887 }
888
889 /* Upload code for builtin functions like integer division emulation. */
890 void
891 nvc0_program_library_upload(struct nvc0_context *nvc0)
892 {
893 struct nvc0_screen *screen = nvc0->screen;
894 int ret;
895 uint32_t size;
896 const uint32_t *code;
897
898 if (screen->lib_code)
899 return;
900
901 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
902 if (!size)
903 return;
904
905 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
906 &screen->lib_code);
907 if (ret)
908 return;
909
910 nvc0->base.push_data(&nvc0->base,
911 screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
912 size, code);
913 /* no need for a memory barrier, will be emitted with first program */
914 }
915
916 void
917 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
918 {
919 const struct pipe_shader_state pipe = prog->pipe;
920 const ubyte type = prog->type;
921
922 if (prog->mem)
923 nouveau_heap_free(&prog->mem);
924 FREE(prog->code); /* may be 0 for hardcoded shaders */
925 FREE(prog->relocs);
926 FREE(prog->fixups);
927 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
928 FREE(prog->cp.syms);
929 if (prog->tfb) {
930 if (nvc0->state.tfb == prog->tfb)
931 nvc0->state.tfb = NULL;
932 FREE(prog->tfb);
933 }
934
935 memset(prog, 0, sizeof(*prog));
936
937 prog->pipe = pipe;
938 prog->type = type;
939 }
940
941 uint32_t
942 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
943 {
944 const struct nv50_ir_prog_symbol *syms =
945 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
946 unsigned base = 0;
947 unsigned i;
948 if (prog->type != PIPE_SHADER_COMPUTE)
949 base = NVC0_SHADER_HEADER_SIZE;
950 for (i = 0; i < prog->cp.num_syms; ++i)
951 if (syms[i].label == label)
952 return prog->code_base + base + syms[i].offset;
953 return prog->code_base; /* no symbols or symbol not found */
954 }
955
956 void
957 nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
958 {
959 struct ureg_program *ureg;
960
961 ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
962 if (!ureg)
963 return;
964
965 ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
966 ureg_END(ureg);
967
968 nvc0->tcp_empty = ureg_create_shader_and_destroy(ureg, &nvc0->base.pipe);
969 }