src/gallium/drivers/nouveau/nvc0/nvc0_program.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_defines.h"
  24
  25 #include "tgsi/tgsi_ureg.h"
  26
  27 #include "nvc0/nvc0_context.h"
  28
  29 #include "codegen/nv50_ir_driver.h"
  30 #include "nvc0/nve4_compute.h"
  31
  32 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
  33  * 124 scalar varying values.
  34  */
  35 static uint32_t
  36 nvc0_shader_input_address(unsigned sn, unsigned si)
  37 {
  38    switch (sn) {
  39    case TGSI_SEMANTIC_TESSOUTER:    return 0x000 + si * 0x4;
  40    case TGSI_SEMANTIC_TESSINNER:    return 0x010 + si * 0x4;
  41    case TGSI_SEMANTIC_PATCH:        return 0x020 + si * 0x10;
  42    case TGSI_SEMANTIC_PRIMID:       return 0x060;
  43    case TGSI_SEMANTIC_LAYER:        return 0x064;
  44    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
  45    case TGSI_SEMANTIC_PSIZE:        return 0x06c;
  46    case TGSI_SEMANTIC_POSITION:     return 0x070;
  47    case TGSI_SEMANTIC_GENERIC:      return 0x080 + si * 0x10;
  48    case TGSI_SEMANTIC_FOG:          return 0x2e8;
  49    case TGSI_SEMANTIC_COLOR:        return 0x280 + si * 0x10;
  50    case TGSI_SEMANTIC_BCOLOR:       return 0x2a0 + si * 0x10;
  51    case TGSI_SEMANTIC_CLIPDIST:     return 0x2c0 + si * 0x10;
  52    case TGSI_SEMANTIC_CLIPVERTEX:   return 0x270;
  53    case TGSI_SEMANTIC_PCOORD:       return 0x2e0;
  54    case TGSI_SEMANTIC_TESSCOORD:    return 0x2f0;
  55    case TGSI_SEMANTIC_INSTANCEID:   return 0x2f8;
  56    case TGSI_SEMANTIC_VERTEXID:     return 0x2fc;
  57    case TGSI_SEMANTIC_TEXCOORD:     return 0x300 + si * 0x10;
  58    case TGSI_SEMANTIC_FACE:         return 0x3fc;
  59    default:
  60       assert(!"invalid TGSI input semantic");
  61       return ~0;
  62    }
  63 }
  64
  65 static uint32_t
  66 nvc0_shader_output_address(unsigned sn, unsigned si)
  67 {
  68    switch (sn) {
  69    case TGSI_SEMANTIC_TESSOUTER:     return 0x000 + si * 0x4;
  70    case TGSI_SEMANTIC_TESSINNER:     return 0x010 + si * 0x4;
  71    case TGSI_SEMANTIC_PATCH:         return 0x020 + si * 0x10;
  72    case TGSI_SEMANTIC_PRIMID:        return 0x060;
  73    case TGSI_SEMANTIC_LAYER:         return 0x064;
  74    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
  75    case TGSI_SEMANTIC_PSIZE:         return 0x06c;
  76    case TGSI_SEMANTIC_POSITION:      return 0x070;
  77    case TGSI_SEMANTIC_GENERIC:       return 0x080 + si * 0x10;
  78    case TGSI_SEMANTIC_FOG:           return 0x2e8;
  79    case TGSI_SEMANTIC_COLOR:         return 0x280 + si * 0x10;
  80    case TGSI_SEMANTIC_BCOLOR:        return 0x2a0 + si * 0x10;
  81    case TGSI_SEMANTIC_CLIPDIST:      return 0x2c0 + si * 0x10;
  82    case TGSI_SEMANTIC_CLIPVERTEX:    return 0x270;
  83    case TGSI_SEMANTIC_TEXCOORD:      return 0x300 + si * 0x10;
  84    case TGSI_SEMANTIC_EDGEFLAG:      return ~0;
  85    default:
  86       assert(!"invalid TGSI output semantic");
  87       return ~0;
  88    }
  89 }
  90
  91 static int
  92 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
  93 {
  94    unsigned i, c, n;
  95
  96    for (n = 0, i = 0; i < info->numInputs; ++i) {
  97       switch (info->in[i].sn) {
  98       case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
  99       case TGSI_SEMANTIC_VERTEXID:
 100          info->in[i].mask = 0x1;
 101          info->in[i].slot[0] =
 102             nvc0_shader_input_address(info->in[i].sn, 0) / 4;
 103          continue;
 104       default:
 105          break;
 106       }
 107       for (c = 0; c < 4; ++c)
 108          info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
 109       ++n;
 110    }
 111
 112    return 0;
 113 }
 114
 115 static int
 116 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
 117 {
 118    unsigned offset;
 119    unsigned i, c;
 120
 121    for (i = 0; i < info->numInputs; ++i) {
 122       offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
 123
 124       for (c = 0; c < 4; ++c)
 125          info->in[i].slot[c] = (offset + c * 0x4) / 4;
 126    }
 127
 128    return 0;
 129 }
 130
 131 static int
 132 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
 133 {
 134    unsigned count = info->prop.fp.numColourResults * 4;
 135    unsigned i, c;
 136
 137    for (i = 0; i < info->numOutputs; ++i)
 138       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
 139          for (c = 0; c < 4; ++c)
 140             info->out[i].slot[c] = info->out[i].si * 4 + c;
 141
 142    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 143       info->out[info->io.sampleMask].slot[0] = count++;
 144    else
 145    if (info->target >= 0xe0)
 146       count++; /* on Kepler, depth is always last colour reg + 2 */
 147
 148    if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
 149       info->out[info->io.fragDepth].slot[2] = count;
 150
 151    return 0;
 152 }
 153
 154 static int
 155 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
 156 {
 157    unsigned offset;
 158    unsigned i, c;
 159
 160    for (i = 0; i < info->numOutputs; ++i) {
 161       offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
 162
 163       for (c = 0; c < 4; ++c)
 164          info->out[i].slot[c] = (offset + c * 0x4) / 4;
 165    }
 166
 167    return 0;
 168 }
 169
 170 static int
 171 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
 172 {
 173    int ret;
 174
 175    if (info->type == PIPE_SHADER_VERTEX)
 176       ret = nvc0_vp_assign_input_slots(info);
 177    else
 178       ret = nvc0_sp_assign_input_slots(info);
 179    if (ret)
 180       return ret;
 181
 182    if (info->type == PIPE_SHADER_FRAGMENT)
 183       ret = nvc0_fp_assign_output_slots(info);
 184    else
 185       ret = nvc0_sp_assign_output_slots(info);
 186    return ret;
 187 }
 188
 189 static inline void
 190 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
 191 {
 192    uint8_t min = (vp->hdr[4] >> 12) & 0xff;
 193    uint8_t max = (vp->hdr[4] >> 24);
 194
 195    min = MIN2(min, slot);
 196    max = MAX2(max, slot);
 197
 198    vp->hdr[4] = (max << 24) | (min << 12);
 199 }
 200
 201 /* Common part of header generation for VP, TCP, TEP and GP. */
 202 static int
 203 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
 204 {
 205    unsigned i, c, a;
 206
 207    for (i = 0; i < info->numInputs; ++i) {
 208       if (info->in[i].patch)
 209          continue;
 210       for (c = 0; c < 4; ++c) {
 211          a = info->in[i].slot[c];
 212          if (info->in[i].mask & (1 << c))
 213             vp->hdr[5 + a / 32] |= 1 << (a % 32);
 214       }
 215    }
 216
 217    for (i = 0; i < info->numOutputs; ++i) {
 218       if (info->out[i].patch)
 219          continue;
 220       for (c = 0; c < 4; ++c) {
 221          if (!(info->out[i].mask & (1 << c)))
 222             continue;
 223          assert(info->out[i].slot[c] >= 0x40 / 4);
 224          a = info->out[i].slot[c] - 0x40 / 4;
 225          vp->hdr[13 + a / 32] |= 1 << (a % 32);
 226          if (info->out[i].oread)
 227             nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
 228       }
 229    }
 230
 231    for (i = 0; i < info->numSysVals; ++i) {
 232       switch (info->sv[i].sn) {
 233       case TGSI_SEMANTIC_PRIMID:
 234          vp->hdr[5] |= 1 << 24;
 235          break;
 236       case TGSI_SEMANTIC_INSTANCEID:
 237          vp->hdr[10] |= 1 << 30;
 238          break;
 239       case TGSI_SEMANTIC_VERTEXID:
 240          vp->hdr[10] |= 1 << 31;
 241          break;
 242       case TGSI_SEMANTIC_TESSCOORD:
 243          /* We don't have the mask, nor the slots populated. While this could
 244           * be achieved, the vast majority of the time if either of the coords
 245           * are read, then both will be read.
 246           */
 247          nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
 248          nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
 249          break;
 250       default:
 251          break;
 252       }
 253    }
 254
 255    vp->vp.clip_enable = info->io.clipDistanceMask;
 256    for (i = 0; i < 8; ++i)
 257       if (info->io.cullDistanceMask & (1 << i))
 258          vp->vp.clip_mode |= 1 << (i * 4);
 259
 260    if (info->io.genUserClip < 0)
 261       vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
 262
 263    return 0;
 264 }
 265
 266 static int
 267 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
 268 {
 269    vp->hdr[0] = 0x20061 | (1 << 10);
 270    vp->hdr[4] = 0xff000;
 271
 272    vp->hdr[18] = info->io.clipDistanceMask;
 273
 274    return nvc0_vtgp_gen_header(vp, info);
 275 }
 276
 277 static void
 278 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
 279 {
 280    if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
 281       tp->tp.tess_mode = ~0;
 282       return;
 283    }
 284    switch (info->prop.tp.domain) {
 285    case PIPE_PRIM_LINES:
 286       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
 287       break;
 288    case PIPE_PRIM_TRIANGLES:
 289       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
 290       if (info->prop.tp.winding > 0)
 291          tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
 292       break;
 293    case PIPE_PRIM_QUADS:
 294       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
 295       break;
 296    default:
 297       tp->tp.tess_mode = ~0;
 298       return;
 299    }
 300    if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
 301       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
 302
 303    switch (info->prop.tp.partitioning) {
 304    case PIPE_TESS_SPACING_EQUAL:
 305       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
 306       break;
 307    case PIPE_TESS_SPACING_FRACTIONAL_ODD:
 308       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
 309       break;
 310    case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
 311       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
 312       break;
 313    default:
 314       assert(!"invalid tessellator partitioning");
 315       break;
 316    }
 317 }
 318
 319 static int
 320 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
 321 {
 322    unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
 323
 324    tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
 325
 326    if (info->numPatchConstants)
 327       opcs = 8 + info->numPatchConstants * 4;
 328
 329    tcp->hdr[0] = 0x20061 | (2 << 10);
 330
 331    tcp->hdr[1] = opcs << 24;
 332    tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
 333
 334    tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
 335
 336    nvc0_vtgp_gen_header(tcp, info);
 337
 338    nvc0_tp_get_tess_mode(tcp, info);
 339
 340    return 0;
 341 }
 342
 343 static int
 344 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
 345 {
 346    tep->tp.input_patch_size = ~0;
 347
 348    tep->hdr[0] = 0x20061 | (3 << 10);
 349    tep->hdr[4] = 0xff000;
 350
 351    nvc0_vtgp_gen_header(tep, info);
 352
 353    nvc0_tp_get_tess_mode(tep, info);
 354
 355    tep->hdr[18] |= 0x3 << 12; /* ? */
 356
 357    return 0;
 358 }
 359
 360 static int
 361 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
 362 {
 363    gp->hdr[0] = 0x20061 | (4 << 10);
 364
 365    gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
 366
 367    switch (info->prop.gp.outputPrim) {
 368    case PIPE_PRIM_POINTS:
 369       gp->hdr[3] = 0x01000000;
 370       gp->hdr[0] |= 0xf0000000;
 371       break;
 372    case PIPE_PRIM_LINE_STRIP:
 373       gp->hdr[3] = 0x06000000;
 374       gp->hdr[0] |= 0x10000000;
 375       break;
 376    case PIPE_PRIM_TRIANGLE_STRIP:
 377       gp->hdr[3] = 0x07000000;
 378       gp->hdr[0] |= 0x10000000;
 379       break;
 380    default:
 381       assert(0);
 382       break;
 383    }
 384
 385    gp->hdr[4] = MIN2(info->prop.gp.maxVertices, 1024);
 386
 387    return nvc0_vtgp_gen_header(gp, info);
 388 }
 389
 390 #define NVC0_INTERP_FLAT          (1 << 0)
 391 #define NVC0_INTERP_PERSPECTIVE   (2 << 0)
 392 #define NVC0_INTERP_LINEAR        (3 << 0)
 393 #define NVC0_INTERP_CENTROID      (1 << 2)
 394
 395 static uint8_t
 396 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
 397 {
 398    if (var->linear)
 399       return NVC0_INTERP_LINEAR;
 400    if (var->flat)
 401       return NVC0_INTERP_FLAT;
 402    return NVC0_INTERP_PERSPECTIVE;
 403 }
 404
 405 static int
 406 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
 407 {
 408    unsigned i, c, a, m;
 409
 410    /* just 00062 on Kepler */
 411    fp->hdr[0] = 0x20062 | (5 << 10);
 412    fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
 413
 414    if (info->prop.fp.usesDiscard)
 415       fp->hdr[0] |= 0x8000;
 416    if (info->prop.fp.numColourResults > 1)
 417       fp->hdr[0] |= 0x4000;
 418    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 419       fp->hdr[19] |= 0x1;
 420    if (info->prop.fp.writesDepth) {
 421       fp->hdr[19] |= 0x2;
 422       fp->flags[0] = 0x11; /* deactivate ZCULL */
 423    }
 424
 425    for (i = 0; i < info->numInputs; ++i) {
 426       m = nvc0_hdr_interp_mode(&info->in[i]);
 427       if (info->in[i].sn == TGSI_SEMANTIC_COLOR) {
 428          fp->fp.colors |= 1 << info->in[i].si;
 429          if (info->in[i].sc)
 430             fp->fp.color_interp[info->in[i].si] = m | (info->in[i].mask << 4);
 431       }
 432       for (c = 0; c < 4; ++c) {
 433          if (!(info->in[i].mask & (1 << c)))
 434             continue;
 435          a = info->in[i].slot[c];
 436          if (info->in[i].slot[0] >= (0x060 / 4) &&
 437              info->in[i].slot[0] <= (0x07c / 4)) {
 438             fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
 439          } else
 440          if (info->in[i].slot[0] >= (0x2c0 / 4) &&
 441              info->in[i].slot[0] <= (0x2fc / 4)) {
 442             fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
 443          } else {
 444             if (info->in[i].slot[c] < (0x040 / 4) ||
 445                 info->in[i].slot[c] > (0x380 / 4))
 446                continue;
 447             a *= 2;
 448             if (info->in[i].slot[0] >= (0x300 / 4))
 449                a -= 32;
 450             fp->hdr[4 + a / 32] |= m << (a % 32);
 451          }
 452       }
 453    }
 454
 455    for (i = 0; i < info->numOutputs; ++i) {
 456       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
 457          fp->hdr[18] |= 0xf << info->out[i].slot[0];
 458    }
 459
 460    fp->fp.early_z = info->prop.fp.earlyFragTests;
 461
 462    return 0;
 463 }
 464
 465 static struct nvc0_transform_feedback_state *
 466 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
 467                               const struct pipe_stream_output_info *pso)
 468 {
 469    struct nvc0_transform_feedback_state *tfb;
 470    unsigned b, i, c;
 471
 472    tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
 473    if (!tfb)
 474       return NULL;
 475    for (b = 0; b < 4; ++b) {
 476       tfb->stride[b] = pso->stride[b] * 4;
 477       tfb->varying_count[b] = 0;
 478    }
 479    memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
 480
 481    for (i = 0; i < pso->num_outputs; ++i) {
 482       unsigned s = pso->output[i].start_component;
 483       unsigned p = pso->output[i].dst_offset;
 484       b = pso->output[i].output_buffer;
 485
 486       for (c = 0; c < pso->output[i].num_components; ++c)
 487          tfb->varying_index[b][p++] =
 488             info->out[pso->output[i].register_index].slot[s + c];
 489
 490       tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
 491       tfb->stream[b] = pso->output[i].stream;
 492    }
 493    for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
 494       for (c = tfb->varying_count[b]; c & 3; ++c)
 495          tfb->varying_index[b][c] = 0;
 496
 497    return tfb;
 498 }
 499
 500 #ifdef DEBUG
 501 static void
 502 nvc0_program_dump(struct nvc0_program *prog)
 503 {
 504    unsigned pos;
 505
 506    if (prog->type != PIPE_SHADER_COMPUTE) {
 507       for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
 508          debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
 509                       pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
 510    }
 511    debug_printf("shader binary code (0x%x bytes):", prog->code_size);
 512    for (pos = 0; pos < prog->code_size / 4; ++pos) {
 513       if ((pos % 8) == 0)
 514          debug_printf("\n");
 515       debug_printf("%08x ", prog->code[pos]);
 516    }
 517    debug_printf("\n");
 518 }
 519 #endif
 520
 521 bool
 522 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
 523 {
 524    struct nv50_ir_prog_info *info;
 525    int ret;
 526
 527    info = CALLOC_STRUCT(nv50_ir_prog_info);
 528    if (!info)
 529       return false;
 530
 531    info->type = prog->type;
 532    info->target = chipset;
 533    info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
 534    info->bin.source = (void *)prog->pipe.tokens;
 535
 536    info->io.genUserClip = prog->vp.num_ucps;
 537    info->io.ucpBase = 256;
 538    info->io.ucpCBSlot = 15;
 539
 540    if (prog->type == PIPE_SHADER_COMPUTE) {
 541       if (chipset >= NVISA_GK104_CHIPSET) {
 542          info->io.resInfoCBSlot = 0;
 543          info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
 544          info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
 545          info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
 546       }
 547       info->io.msInfoCBSlot = 0;
 548       info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
 549    } else {
 550       if (chipset >= NVISA_GK104_CHIPSET) {
 551          info->io.texBindBase = 0x20;
 552          info->io.suInfoBase = 0; /* TODO */
 553       }
 554       info->io.resInfoCBSlot = 15;
 555       info->io.sampleInfoBase = 256 + 128;
 556       info->io.msInfoCBSlot = 15;
 557       info->io.msInfoBase = 0; /* TODO */
 558    }
 559
 560    info->assignSlots = nvc0_program_assign_varying_slots;
 561
 562 #ifdef DEBUG
 563    info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
 564    info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
 565 #else
 566    info->optLevel = 3;
 567 #endif
 568
 569    ret = nv50_ir_generate_code(info);
 570    if (ret) {
 571       NOUVEAU_ERR("shader translation failed: %i\n", ret);
 572       goto out;
 573    }
 574    if (prog->type != PIPE_SHADER_COMPUTE)
 575       FREE(info->bin.syms);
 576
 577    prog->code = info->bin.code;
 578    prog->code_size = info->bin.codeSize;
 579    prog->immd_data = info->immd.buf;
 580    prog->immd_size = info->immd.bufSize;
 581    prog->relocs = info->bin.relocData;
 582    prog->interps = info->bin.interpData;
 583    prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
 584    prog->num_barriers = info->numBarriers;
 585
 586    prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
 587
 588    if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
 589       info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
 590    prog->vp.edgeflag = info->io.edgeFlagIn;
 591
 592    switch (prog->type) {
 593    case PIPE_SHADER_VERTEX:
 594       ret = nvc0_vp_gen_header(prog, info);
 595       break;
 596    case PIPE_SHADER_TESS_CTRL:
 597       ret = nvc0_tcp_gen_header(prog, info);
 598       break;
 599    case PIPE_SHADER_TESS_EVAL:
 600       ret = nvc0_tep_gen_header(prog, info);
 601       break;
 602    case PIPE_SHADER_GEOMETRY:
 603       ret = nvc0_gp_gen_header(prog, info);
 604       break;
 605    case PIPE_SHADER_FRAGMENT:
 606       ret = nvc0_fp_gen_header(prog, info);
 607       break;
 608    case PIPE_SHADER_COMPUTE:
 609       prog->cp.syms = info->bin.syms;
 610       prog->cp.num_syms = info->bin.numSyms;
 611       break;
 612    default:
 613       ret = -1;
 614       NOUVEAU_ERR("unknown program type: %u\n", prog->type);
 615       break;
 616    }
 617    if (ret)
 618       goto out;
 619
 620    if (info->bin.tlsSpace) {
 621       assert(info->bin.tlsSpace < (1 << 24));
 622       prog->hdr[0] |= 1 << 26;
 623       prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
 624       prog->need_tls = true;
 625    }
 626    /* TODO: factor 2 only needed where joinat/precont is used,
 627     *       and we only have to count non-uniform branches
 628     */
 629    /*
 630    if ((info->maxCFDepth * 2) > 16) {
 631       prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
 632       prog->need_tls = true;
 633    }
 634    */
 635    if (info->io.globalAccess)
 636       prog->hdr[0] |= 1 << 16;
 637    if (info->io.fp64)
 638       prog->hdr[0] |= 1 << 27;
 639
 640    if (prog->pipe.stream_output.num_outputs)
 641       prog->tfb = nvc0_program_create_tfb_state(info,
 642                                                 &prog->pipe.stream_output);
 643
 644 out:
 645    FREE(info);
 646    return !ret;
 647 }
 648
 649 bool
 650 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
 651 {
 652    struct nvc0_screen *screen = nvc0->screen;
 653    const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
 654    int ret;
 655    uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
 656    uint32_t lib_pos = screen->lib_code->start;
 657    uint32_t code_pos;
 658
 659    /* c[] bindings need to be aligned to 0x100, but we could use relocations
 660     * to save space. */
 661    if (prog->immd_size) {
 662       prog->immd_base = size;
 663       size = align(size, 0x40);
 664       size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
 665    }
 666    /* On Fermi, SP_START_ID must be aligned to 0x40.
 667     * On Kepler, the first instruction must be aligned to 0x80 because
 668     * latency information is expected only at certain positions.
 669     */
 670    if (screen->base.class_3d >= NVE4_3D_CLASS)
 671       size = size + (is_cp ? 0x40 : 0x70);
 672    size = align(size, 0x40);
 673
 674    ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
 675    if (ret) {
 676       struct nouveau_heap *heap = screen->text_heap;
 677       /* Note that the code library, which is allocated before anything else,
 678        * does not have a priv pointer. We can stop once we hit it.
 679        */
 680       while (heap->next && heap->next->priv) {
 681          struct nvc0_program *evict = heap->next->priv;
 682          nouveau_heap_free(&evict->mem);
 683       }
 684       debug_printf("WARNING: out of code space, evicting all shaders.\n");
 685       ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
 686       if (ret) {
 687          NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
 688          return false;
 689       }
 690       IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
 691    }
 692    prog->code_base = prog->mem->start;
 693    prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
 694    assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
 695                                      prog->mem->start + prog->mem->size));
 696
 697    if (!is_cp) {
 698       if (screen->base.class_3d >= NVE4_3D_CLASS) {
 699          switch (prog->mem->start & 0xff) {
 700          case 0x40: prog->code_base += 0x70; break;
 701          case 0x80: prog->code_base += 0x30; break;
 702          case 0xc0: prog->code_base += 0x70; break;
 703          default:
 704             prog->code_base += 0x30;
 705             assert((prog->mem->start & 0xff) == 0x00);
 706             break;
 707          }
 708       }
 709       code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
 710    } else {
 711       if (screen->base.class_3d >= NVE4_3D_CLASS) {
 712          if (prog->mem->start & 0x40)
 713             prog->code_base += 0x40;
 714          assert((prog->code_base & 0x7f) == 0x00);
 715       }
 716       code_pos = prog->code_base;
 717    }
 718
 719    if (prog->relocs)
 720       nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
 721    if (prog->interps) {
 722       nv50_ir_change_interp(prog->interps, prog->code,
 723                             prog->fp.force_persample_interp,
 724                             prog->fp.flatshade);
 725       for (int i = 0; i < 2; i++) {
 726          unsigned mask = prog->fp.color_interp[i] >> 4;
 727          unsigned interp = prog->fp.color_interp[i] & 3;
 728          if (!mask)
 729             continue;
 730          prog->hdr[14] &= ~(0xff << (8 * i));
 731          if (prog->fp.flatshade)
 732             interp = NVC0_INTERP_FLAT;
 733          for (int c = 0; c < 4; c++)
 734             if (mask & (1 << c))
 735                prog->hdr[14] |= interp << (2 * (4 * i + c));
 736       }
 737    }
 738
 739 #ifdef DEBUG
 740    if (debug_get_bool_option("NV50_PROG_DEBUG", false))
 741       nvc0_program_dump(prog);
 742 #endif
 743
 744    if (!is_cp)
 745       nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
 746                            NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr);
 747    nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
 748                         NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code);
 749    if (prog->immd_size)
 750       nvc0->base.push_data(&nvc0->base,
 751                            screen->text, prog->immd_base, NV_VRAM_DOMAIN(&screen->base),
 752                            prog->immd_size, prog->immd_data);
 753
 754    BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
 755    PUSH_DATA (nvc0->base.pushbuf, 0x1011);
 756
 757    return true;
 758 }
 759
 760 /* Upload code for builtin functions like integer division emulation. */
 761 void
 762 nvc0_program_library_upload(struct nvc0_context *nvc0)
 763 {
 764    struct nvc0_screen *screen = nvc0->screen;
 765    int ret;
 766    uint32_t size;
 767    const uint32_t *code;
 768
 769    if (screen->lib_code)
 770       return;
 771
 772    nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
 773    if (!size)
 774       return;
 775
 776    ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
 777                             &screen->lib_code);
 778    if (ret)
 779       return;
 780
 781    nvc0->base.push_data(&nvc0->base,
 782                         screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
 783                         size, code);
 784    /* no need for a memory barrier, will be emitted with first program */
 785 }
 786
 787 void
 788 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
 789 {
 790    const struct pipe_shader_state pipe = prog->pipe;
 791    const ubyte type = prog->type;
 792
 793    if (prog->mem)
 794       nouveau_heap_free(&prog->mem);
 795    FREE(prog->code); /* may be 0 for hardcoded shaders */
 796    FREE(prog->immd_data);
 797    FREE(prog->relocs);
 798    FREE(prog->interps);
 799    if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
 800       FREE(prog->cp.syms);
 801    if (prog->tfb) {
 802       if (nvc0->state.tfb == prog->tfb)
 803          nvc0->state.tfb = NULL;
 804       FREE(prog->tfb);
 805    }
 806
 807    memset(prog, 0, sizeof(*prog));
 808
 809    prog->pipe = pipe;
 810    prog->type = type;
 811 }
 812
 813 uint32_t
 814 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
 815 {
 816    const struct nv50_ir_prog_symbol *syms =
 817       (const struct nv50_ir_prog_symbol *)prog->cp.syms;
 818    unsigned base = 0;
 819    unsigned i;
 820    if (prog->type != PIPE_SHADER_COMPUTE)
 821       base = NVC0_SHADER_HEADER_SIZE;
 822    for (i = 0; i < prog->cp.num_syms; ++i)
 823       if (syms[i].label == label)
 824          return prog->code_base + base + syms[i].offset;
 825    return prog->code_base; /* no symbols or symbol not found */
 826 }
 827
 828 void
 829 nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
 830 {
 831    struct ureg_program *ureg;
 832
 833    ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
 834    if (!ureg)
 835       return;
 836
 837    ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
 838    ureg_END(ureg);
 839
 840    nvc0->tcp_empty = ureg_create_shader_and_destroy(ureg, &nvc0->base.pipe);
 841 }