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nvc0: preliminary tess support
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "nvc0/nvc0_context.h"
26
27 #include "codegen/nv50_ir_driver.h"
28 #include "nvc0/nve4_compute.h"
29
30 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
31 * 124 scalar varying values.
32 */
33 static uint32_t
34 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
35 {
36 switch (sn) {
37 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
38 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
39 case TGSI_SEMANTIC_PRIMID: return 0x060;
40 case TGSI_SEMANTIC_LAYER: return 0x064;
41 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
42 case TGSI_SEMANTIC_PSIZE: return 0x06c;
43 case TGSI_SEMANTIC_POSITION: return 0x070;
44 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
45 case TGSI_SEMANTIC_FOG: return 0x2e8;
46 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
47 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
48 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
49 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
50 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
51 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
52 case TGSI_SEMANTIC_TESSCOORD: return 0x2f0;
53 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
54 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
55 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
56 case TGSI_SEMANTIC_FACE: return 0x3fc;
57 default:
58 assert(!"invalid TGSI input semantic");
59 return ~0;
60 }
61 }
62
63 static uint32_t
64 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
65 {
66 switch (sn) {
67 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
68 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
69 case TGSI_SEMANTIC_PRIMID: return 0x060;
70 case TGSI_SEMANTIC_LAYER: return 0x064;
71 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
72 case TGSI_SEMANTIC_PSIZE: return 0x06c;
73 case TGSI_SEMANTIC_POSITION: return 0x070;
74 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
75 case TGSI_SEMANTIC_FOG: return 0x2e8;
76 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
77 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
78 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
79 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
80 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
81 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
82 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
83 default:
84 assert(!"invalid TGSI output semantic");
85 return ~0;
86 }
87 }
88
89 static int
90 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
91 {
92 unsigned i, c, n;
93
94 for (n = 0, i = 0; i < info->numInputs; ++i) {
95 switch (info->in[i].sn) {
96 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
97 case TGSI_SEMANTIC_VERTEXID:
98 info->in[i].mask = 0x1;
99 info->in[i].slot[0] =
100 nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
101 continue;
102 default:
103 break;
104 }
105 for (c = 0; c < 4; ++c)
106 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
107 ++n;
108 }
109
110 return 0;
111 }
112
113 static int
114 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
115 {
116 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
117 unsigned offset;
118 unsigned i, c;
119
120 for (i = 0; i < info->numInputs; ++i) {
121 offset = nvc0_shader_input_address(info->in[i].sn,
122 info->in[i].si, ubase);
123 if (info->in[i].patch && offset >= 0x20)
124 offset = 0x20 + info->in[i].si * 0x10;
125
126 if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
127 info->in[i].mask &= 3;
128
129 for (c = 0; c < 4; ++c)
130 info->in[i].slot[c] = (offset + c * 0x4) / 4;
131 }
132
133 return 0;
134 }
135
136 static int
137 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
138 {
139 unsigned count = info->prop.fp.numColourResults * 4;
140 unsigned i, c;
141
142 for (i = 0; i < info->numOutputs; ++i)
143 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
144 for (c = 0; c < 4; ++c)
145 info->out[i].slot[c] = info->out[i].si * 4 + c;
146
147 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
148 info->out[info->io.sampleMask].slot[0] = count++;
149 else
150 if (info->target >= 0xe0)
151 count++; /* on Kepler, depth is always last colour reg + 2 */
152
153 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
154 info->out[info->io.fragDepth].slot[2] = count;
155
156 return 0;
157 }
158
159 static int
160 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
161 {
162 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
163 unsigned offset;
164 unsigned i, c;
165
166 for (i = 0; i < info->numOutputs; ++i) {
167 offset = nvc0_shader_output_address(info->out[i].sn,
168 info->out[i].si, ubase);
169 if (info->out[i].patch && offset >= 0x20)
170 offset = 0x20 + info->out[i].si * 0x10;
171
172 for (c = 0; c < 4; ++c)
173 info->out[i].slot[c] = (offset + c * 0x4) / 4;
174 }
175
176 return 0;
177 }
178
179 static int
180 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
181 {
182 int ret;
183
184 if (info->type == PIPE_SHADER_VERTEX)
185 ret = nvc0_vp_assign_input_slots(info);
186 else
187 ret = nvc0_sp_assign_input_slots(info);
188 if (ret)
189 return ret;
190
191 if (info->type == PIPE_SHADER_FRAGMENT)
192 ret = nvc0_fp_assign_output_slots(info);
193 else
194 ret = nvc0_sp_assign_output_slots(info);
195 return ret;
196 }
197
198 static inline void
199 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
200 {
201 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
202 uint8_t max = (vp->hdr[4] >> 24);
203
204 min = MIN2(min, slot);
205 max = MAX2(max, slot);
206
207 vp->hdr[4] = (max << 24) | (min << 12);
208 }
209
210 /* Common part of header generation for VP, TCP, TEP and GP. */
211 static int
212 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
213 {
214 unsigned i, c, a;
215
216 for (i = 0; i < info->numInputs; ++i) {
217 if (info->in[i].patch)
218 continue;
219 for (c = 0; c < 4; ++c) {
220 a = info->in[i].slot[c];
221 if (info->in[i].mask & (1 << c)) {
222 if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
223 vp->hdr[5 + a / 32] |= 1 << (a % 32);
224 else
225 nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
226 }
227 }
228 }
229
230 for (i = 0; i < info->numOutputs; ++i) {
231 if (info->out[i].patch)
232 continue;
233 for (c = 0; c < 4; ++c) {
234 if (!(info->out[i].mask & (1 << c)))
235 continue;
236 assert(info->out[i].slot[c] >= 0x40 / 4);
237 a = info->out[i].slot[c] - 0x40 / 4;
238 vp->hdr[13 + a / 32] |= 1 << (a % 32);
239 if (info->out[i].oread)
240 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
241 }
242 }
243
244 for (i = 0; i < info->numSysVals; ++i) {
245 switch (info->sv[i].sn) {
246 case TGSI_SEMANTIC_PRIMID:
247 vp->hdr[5] |= 1 << 24;
248 break;
249 case TGSI_SEMANTIC_INSTANCEID:
250 vp->hdr[10] |= 1 << 30;
251 break;
252 case TGSI_SEMANTIC_VERTEXID:
253 vp->hdr[10] |= 1 << 31;
254 break;
255 default:
256 break;
257 }
258 }
259
260 vp->vp.clip_enable = info->io.clipDistanceMask;
261 for (i = 0; i < 8; ++i)
262 if (info->io.cullDistanceMask & (1 << i))
263 vp->vp.clip_mode |= 1 << (i * 4);
264
265 if (info->io.genUserClip < 0)
266 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
267
268 return 0;
269 }
270
271 static int
272 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
273 {
274 vp->hdr[0] = 0x20061 | (1 << 10);
275 vp->hdr[4] = 0xff000;
276
277 vp->hdr[18] = info->io.clipDistanceMask;
278
279 return nvc0_vtgp_gen_header(vp, info);
280 }
281
282 static void
283 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
284 {
285 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
286 tp->tp.tess_mode = ~0;
287 return;
288 }
289 switch (info->prop.tp.domain) {
290 case PIPE_PRIM_LINES:
291 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
292 break;
293 case PIPE_PRIM_TRIANGLES:
294 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
295 if (info->prop.tp.winding > 0)
296 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
297 break;
298 case PIPE_PRIM_QUADS:
299 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
300 break;
301 default:
302 tp->tp.tess_mode = ~0;
303 return;
304 }
305 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
306 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
307
308 switch (info->prop.tp.partitioning) {
309 case PIPE_TESS_SPACING_EQUAL:
310 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
311 break;
312 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
313 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
314 break;
315 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
316 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
317 break;
318 default:
319 assert(!"invalid tessellator partitioning");
320 break;
321 }
322 }
323
324 static int
325 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
326 {
327 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
328
329 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
330
331 if (info->numPatchConstants)
332 opcs = 8 + info->numPatchConstants * 4;
333
334 tcp->hdr[0] = 0x20061 | (2 << 10);
335
336 tcp->hdr[1] = opcs << 24;
337 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
338
339 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
340
341 nvc0_vtgp_gen_header(tcp, info);
342
343 nvc0_tp_get_tess_mode(tcp, info);
344
345 return 0;
346 }
347
348 static int
349 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
350 {
351 tep->tp.input_patch_size = ~0;
352
353 tep->hdr[0] = 0x20061 | (3 << 10);
354 tep->hdr[4] = 0xff000;
355
356 nvc0_vtgp_gen_header(tep, info);
357
358 nvc0_tp_get_tess_mode(tep, info);
359
360 tep->hdr[18] |= 0x3 << 12; /* ? */
361
362 return 0;
363 }
364
365 static int
366 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
367 {
368 gp->hdr[0] = 0x20061 | (4 << 10);
369
370 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
371
372 switch (info->prop.gp.outputPrim) {
373 case PIPE_PRIM_POINTS:
374 gp->hdr[3] = 0x01000000;
375 gp->hdr[0] |= 0xf0000000;
376 break;
377 case PIPE_PRIM_LINE_STRIP:
378 gp->hdr[3] = 0x06000000;
379 gp->hdr[0] |= 0x10000000;
380 break;
381 case PIPE_PRIM_TRIANGLE_STRIP:
382 gp->hdr[3] = 0x07000000;
383 gp->hdr[0] |= 0x10000000;
384 break;
385 default:
386 assert(0);
387 break;
388 }
389
390 gp->hdr[4] = MIN2(info->prop.gp.maxVertices, 1024);
391
392 return nvc0_vtgp_gen_header(gp, info);
393 }
394
395 #define NVC0_INTERP_FLAT (1 << 0)
396 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
397 #define NVC0_INTERP_LINEAR (3 << 0)
398 #define NVC0_INTERP_CENTROID (1 << 2)
399
400 static uint8_t
401 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
402 {
403 if (var->linear)
404 return NVC0_INTERP_LINEAR;
405 if (var->flat)
406 return NVC0_INTERP_FLAT;
407 return NVC0_INTERP_PERSPECTIVE;
408 }
409
410 static int
411 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
412 {
413 unsigned i, c, a, m;
414
415 /* just 00062 on Kepler */
416 fp->hdr[0] = 0x20062 | (5 << 10);
417 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
418
419 if (info->prop.fp.usesDiscard)
420 fp->hdr[0] |= 0x8000;
421 if (info->prop.fp.numColourResults > 1)
422 fp->hdr[0] |= 0x4000;
423 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
424 fp->hdr[19] |= 0x1;
425 if (info->prop.fp.writesDepth) {
426 fp->hdr[19] |= 0x2;
427 fp->flags[0] = 0x11; /* deactivate ZCULL */
428 }
429
430 for (i = 0; i < info->numInputs; ++i) {
431 m = nvc0_hdr_interp_mode(&info->in[i]);
432 for (c = 0; c < 4; ++c) {
433 if (!(info->in[i].mask & (1 << c)))
434 continue;
435 a = info->in[i].slot[c];
436 if (info->in[i].slot[0] >= (0x060 / 4) &&
437 info->in[i].slot[0] <= (0x07c / 4)) {
438 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
439 } else
440 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
441 info->in[i].slot[0] <= (0x2fc / 4)) {
442 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
443 } else {
444 if (info->in[i].slot[c] < (0x040 / 4) ||
445 info->in[i].slot[c] > (0x380 / 4))
446 continue;
447 a *= 2;
448 if (info->in[i].slot[0] >= (0x300 / 4))
449 a -= 32;
450 fp->hdr[4 + a / 32] |= m << (a % 32);
451 }
452 }
453 }
454
455 for (i = 0; i < info->numOutputs; ++i) {
456 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
457 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
458 }
459
460 fp->fp.early_z = info->prop.fp.earlyFragTests;
461
462 return 0;
463 }
464
465 static struct nvc0_transform_feedback_state *
466 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
467 const struct pipe_stream_output_info *pso)
468 {
469 struct nvc0_transform_feedback_state *tfb;
470 unsigned b, i, c;
471
472 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
473 if (!tfb)
474 return NULL;
475 for (b = 0; b < 4; ++b) {
476 tfb->stride[b] = pso->stride[b] * 4;
477 tfb->varying_count[b] = 0;
478 }
479 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
480
481 for (i = 0; i < pso->num_outputs; ++i) {
482 unsigned s = pso->output[i].start_component;
483 unsigned p = pso->output[i].dst_offset;
484 b = pso->output[i].output_buffer;
485
486 for (c = 0; c < pso->output[i].num_components; ++c)
487 tfb->varying_index[b][p++] =
488 info->out[pso->output[i].register_index].slot[s + c];
489
490 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
491 tfb->stream[b] = pso->output[i].stream;
492 }
493 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
494 for (c = tfb->varying_count[b]; c & 3; ++c)
495 tfb->varying_index[b][c] = 0;
496
497 return tfb;
498 }
499
500 #ifdef DEBUG
501 static void
502 nvc0_program_dump(struct nvc0_program *prog)
503 {
504 unsigned pos;
505
506 if (prog->type != PIPE_SHADER_COMPUTE) {
507 for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
508 debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
509 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
510 }
511 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
512 for (pos = 0; pos < prog->code_size / 4; ++pos) {
513 if ((pos % 8) == 0)
514 debug_printf("\n");
515 debug_printf("%08x ", prog->code[pos]);
516 }
517 debug_printf("\n");
518 }
519 #endif
520
521 bool
522 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
523 {
524 struct nv50_ir_prog_info *info;
525 int ret;
526
527 info = CALLOC_STRUCT(nv50_ir_prog_info);
528 if (!info)
529 return false;
530
531 info->type = prog->type;
532 info->target = chipset;
533 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
534 info->bin.source = (void *)prog->pipe.tokens;
535
536 info->io.genUserClip = prog->vp.num_ucps;
537 info->io.ucpBase = 256;
538 info->io.ucpCBSlot = 15;
539 info->io.sampleInterp = prog->fp.sample_interp;
540
541 if (prog->type == PIPE_SHADER_COMPUTE) {
542 if (chipset >= NVISA_GK104_CHIPSET) {
543 info->io.resInfoCBSlot = 0;
544 info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
545 info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
546 info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
547 }
548 info->io.msInfoCBSlot = 0;
549 info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
550 } else {
551 if (chipset >= NVISA_GK104_CHIPSET) {
552 info->io.texBindBase = 0x20;
553 info->io.suInfoBase = 0; /* TODO */
554 }
555 info->io.resInfoCBSlot = 15;
556 info->io.sampleInfoBase = 256 + 128;
557 info->io.msInfoCBSlot = 15;
558 info->io.msInfoBase = 0; /* TODO */
559 }
560
561 info->assignSlots = nvc0_program_assign_varying_slots;
562
563 #ifdef DEBUG
564 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
565 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
566 #else
567 info->optLevel = 3;
568 #endif
569
570 ret = nv50_ir_generate_code(info);
571 if (ret) {
572 NOUVEAU_ERR("shader translation failed: %i\n", ret);
573 goto out;
574 }
575 if (prog->type != PIPE_SHADER_COMPUTE)
576 FREE(info->bin.syms);
577
578 prog->code = info->bin.code;
579 prog->code_size = info->bin.codeSize;
580 prog->immd_data = info->immd.buf;
581 prog->immd_size = info->immd.bufSize;
582 prog->relocs = info->bin.relocData;
583 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
584 prog->num_barriers = info->numBarriers;
585
586 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
587
588 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
589 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
590 prog->vp.edgeflag = info->io.edgeFlagIn;
591
592 switch (prog->type) {
593 case PIPE_SHADER_VERTEX:
594 ret = nvc0_vp_gen_header(prog, info);
595 break;
596 case PIPE_SHADER_TESS_CTRL:
597 ret = nvc0_tcp_gen_header(prog, info);
598 break;
599 case PIPE_SHADER_TESS_EVAL:
600 ret = nvc0_tep_gen_header(prog, info);
601 break;
602 case PIPE_SHADER_GEOMETRY:
603 ret = nvc0_gp_gen_header(prog, info);
604 break;
605 case PIPE_SHADER_FRAGMENT:
606 ret = nvc0_fp_gen_header(prog, info);
607 break;
608 case PIPE_SHADER_COMPUTE:
609 prog->cp.syms = info->bin.syms;
610 prog->cp.num_syms = info->bin.numSyms;
611 break;
612 default:
613 ret = -1;
614 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
615 break;
616 }
617 if (ret)
618 goto out;
619
620 if (info->bin.tlsSpace) {
621 assert(info->bin.tlsSpace < (1 << 24));
622 prog->hdr[0] |= 1 << 26;
623 prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
624 prog->need_tls = true;
625 }
626 /* TODO: factor 2 only needed where joinat/precont is used,
627 * and we only have to count non-uniform branches
628 */
629 /*
630 if ((info->maxCFDepth * 2) > 16) {
631 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
632 prog->need_tls = true;
633 }
634 */
635 if (info->io.globalAccess)
636 prog->hdr[0] |= 1 << 16;
637 if (info->io.fp64)
638 prog->hdr[0] |= 1 << 27;
639
640 if (prog->pipe.stream_output.num_outputs)
641 prog->tfb = nvc0_program_create_tfb_state(info,
642 &prog->pipe.stream_output);
643
644 out:
645 FREE(info);
646 return !ret;
647 }
648
649 bool
650 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
651 {
652 struct nvc0_screen *screen = nvc0->screen;
653 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
654 int ret;
655 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
656 uint32_t lib_pos = screen->lib_code->start;
657 uint32_t code_pos;
658
659 /* c[] bindings need to be aligned to 0x100, but we could use relocations
660 * to save space. */
661 if (prog->immd_size) {
662 prog->immd_base = size;
663 size = align(size, 0x40);
664 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
665 }
666 /* On Fermi, SP_START_ID must be aligned to 0x40.
667 * On Kepler, the first instruction must be aligned to 0x80 because
668 * latency information is expected only at certain positions.
669 */
670 if (screen->base.class_3d >= NVE4_3D_CLASS)
671 size = size + (is_cp ? 0x40 : 0x70);
672 size = align(size, 0x40);
673
674 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
675 if (ret) {
676 struct nouveau_heap *heap = screen->text_heap;
677 /* Note that the code library, which is allocated before anything else,
678 * does not have a priv pointer. We can stop once we hit it.
679 */
680 while (heap->next && heap->next->priv) {
681 struct nvc0_program *evict = heap->next->priv;
682 nouveau_heap_free(&evict->mem);
683 }
684 debug_printf("WARNING: out of code space, evicting all shaders.\n");
685 ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
686 if (ret) {
687 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
688 return false;
689 }
690 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
691 }
692 prog->code_base = prog->mem->start;
693 prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
694 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
695 prog->mem->start + prog->mem->size));
696
697 if (!is_cp) {
698 if (screen->base.class_3d >= NVE4_3D_CLASS) {
699 switch (prog->mem->start & 0xff) {
700 case 0x40: prog->code_base += 0x70; break;
701 case 0x80: prog->code_base += 0x30; break;
702 case 0xc0: prog->code_base += 0x70; break;
703 default:
704 prog->code_base += 0x30;
705 assert((prog->mem->start & 0xff) == 0x00);
706 break;
707 }
708 }
709 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
710 } else {
711 if (screen->base.class_3d >= NVE4_3D_CLASS) {
712 if (prog->mem->start & 0x40)
713 prog->code_base += 0x40;
714 assert((prog->code_base & 0x7f) == 0x00);
715 }
716 code_pos = prog->code_base;
717 }
718
719 if (prog->relocs)
720 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
721
722 #ifdef DEBUG
723 if (debug_get_bool_option("NV50_PROG_DEBUG", false))
724 nvc0_program_dump(prog);
725 #endif
726
727 if (!is_cp)
728 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
729 NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr);
730 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
731 NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code);
732 if (prog->immd_size)
733 nvc0->base.push_data(&nvc0->base,
734 screen->text, prog->immd_base, NV_VRAM_DOMAIN(&screen->base),
735 prog->immd_size, prog->immd_data);
736
737 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
738 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
739
740 return true;
741 }
742
743 /* Upload code for builtin functions like integer division emulation. */
744 void
745 nvc0_program_library_upload(struct nvc0_context *nvc0)
746 {
747 struct nvc0_screen *screen = nvc0->screen;
748 int ret;
749 uint32_t size;
750 const uint32_t *code;
751
752 if (screen->lib_code)
753 return;
754
755 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
756 if (!size)
757 return;
758
759 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
760 &screen->lib_code);
761 if (ret)
762 return;
763
764 nvc0->base.push_data(&nvc0->base,
765 screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
766 size, code);
767 /* no need for a memory barrier, will be emitted with first program */
768 }
769
770 void
771 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
772 {
773 const struct pipe_shader_state pipe = prog->pipe;
774 const ubyte type = prog->type;
775
776 if (prog->mem)
777 nouveau_heap_free(&prog->mem);
778 FREE(prog->code); /* may be 0 for hardcoded shaders */
779 FREE(prog->immd_data);
780 FREE(prog->relocs);
781 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
782 FREE(prog->cp.syms);
783 if (prog->tfb) {
784 if (nvc0->state.tfb == prog->tfb)
785 nvc0->state.tfb = NULL;
786 FREE(prog->tfb);
787 }
788
789 memset(prog, 0, sizeof(*prog));
790
791 prog->pipe = pipe;
792 prog->type = type;
793 }
794
795 uint32_t
796 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
797 {
798 const struct nv50_ir_prog_symbol *syms =
799 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
800 unsigned base = 0;
801 unsigned i;
802 if (prog->type != PIPE_SHADER_COMPUTE)
803 base = NVC0_SHADER_HEADER_SIZE;
804 for (i = 0; i < prog->cp.num_syms; ++i)
805 if (syms[i].label == label)
806 return prog->code_base + base + syms[i].offset;
807 return prog->code_base; /* no symbols or symbol not found */
808 }