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Merge remote-tracking branch 'public/master' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "tgsi/tgsi_ureg.h"
26
27 #include "nvc0/nvc0_context.h"
28
29 #include "codegen/nv50_ir_driver.h"
30 #include "nvc0/nve4_compute.h"
31
32 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
33 * 124 scalar varying values.
34 */
35 static uint32_t
36 nvc0_shader_input_address(unsigned sn, unsigned si)
37 {
38 switch (sn) {
39 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
40 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
41 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
42 case TGSI_SEMANTIC_PRIMID: return 0x060;
43 case TGSI_SEMANTIC_LAYER: return 0x064;
44 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
45 case TGSI_SEMANTIC_PSIZE: return 0x06c;
46 case TGSI_SEMANTIC_POSITION: return 0x070;
47 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
48 case TGSI_SEMANTIC_FOG: return 0x2e8;
49 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
50 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
51 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
52 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
53 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
54 case TGSI_SEMANTIC_TESSCOORD: return 0x2f0;
55 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
56 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
57 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
58 default:
59 assert(!"invalid TGSI input semantic");
60 return ~0;
61 }
62 }
63
64 static uint32_t
65 nvc0_shader_output_address(unsigned sn, unsigned si)
66 {
67 switch (sn) {
68 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
69 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
70 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
71 case TGSI_SEMANTIC_PRIMID: return 0x060;
72 case TGSI_SEMANTIC_LAYER: return 0x064;
73 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
74 case TGSI_SEMANTIC_PSIZE: return 0x06c;
75 case TGSI_SEMANTIC_POSITION: return 0x070;
76 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
77 case TGSI_SEMANTIC_FOG: return 0x2e8;
78 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
79 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
80 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
81 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
82 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
83 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
84 default:
85 assert(!"invalid TGSI output semantic");
86 return ~0;
87 }
88 }
89
90 static int
91 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
92 {
93 unsigned i, c, n;
94
95 for (n = 0, i = 0; i < info->numInputs; ++i) {
96 switch (info->in[i].sn) {
97 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
98 case TGSI_SEMANTIC_VERTEXID:
99 info->in[i].mask = 0x1;
100 info->in[i].slot[0] =
101 nvc0_shader_input_address(info->in[i].sn, 0) / 4;
102 continue;
103 default:
104 break;
105 }
106 for (c = 0; c < 4; ++c)
107 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
108 ++n;
109 }
110
111 return 0;
112 }
113
114 static int
115 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
116 {
117 unsigned offset;
118 unsigned i, c;
119
120 for (i = 0; i < info->numInputs; ++i) {
121 offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
122
123 for (c = 0; c < 4; ++c)
124 info->in[i].slot[c] = (offset + c * 0x4) / 4;
125 }
126
127 return 0;
128 }
129
130 static int
131 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
132 {
133 unsigned count = info->prop.fp.numColourResults * 4;
134 unsigned i, c;
135
136 for (i = 0; i < info->numOutputs; ++i)
137 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
138 for (c = 0; c < 4; ++c)
139 info->out[i].slot[c] = info->out[i].si * 4 + c;
140
141 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
142 info->out[info->io.sampleMask].slot[0] = count++;
143 else
144 if (info->target >= 0xe0)
145 count++; /* on Kepler, depth is always last colour reg + 2 */
146
147 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
148 info->out[info->io.fragDepth].slot[2] = count;
149
150 return 0;
151 }
152
153 static int
154 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
155 {
156 unsigned offset;
157 unsigned i, c;
158
159 for (i = 0; i < info->numOutputs; ++i) {
160 offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
161
162 for (c = 0; c < 4; ++c)
163 info->out[i].slot[c] = (offset + c * 0x4) / 4;
164 }
165
166 return 0;
167 }
168
169 static int
170 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
171 {
172 int ret;
173
174 if (info->type == PIPE_SHADER_VERTEX)
175 ret = nvc0_vp_assign_input_slots(info);
176 else
177 ret = nvc0_sp_assign_input_slots(info);
178 if (ret)
179 return ret;
180
181 if (info->type == PIPE_SHADER_FRAGMENT)
182 ret = nvc0_fp_assign_output_slots(info);
183 else
184 ret = nvc0_sp_assign_output_slots(info);
185 return ret;
186 }
187
188 static inline void
189 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
190 {
191 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
192 uint8_t max = (vp->hdr[4] >> 24);
193
194 min = MIN2(min, slot);
195 max = MAX2(max, slot);
196
197 vp->hdr[4] = (max << 24) | (min << 12);
198 }
199
200 /* Common part of header generation for VP, TCP, TEP and GP. */
201 static int
202 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
203 {
204 unsigned i, c, a;
205
206 for (i = 0; i < info->numInputs; ++i) {
207 if (info->in[i].patch)
208 continue;
209 for (c = 0; c < 4; ++c) {
210 a = info->in[i].slot[c];
211 if (info->in[i].mask & (1 << c))
212 vp->hdr[5 + a / 32] |= 1 << (a % 32);
213 }
214 }
215
216 for (i = 0; i < info->numOutputs; ++i) {
217 if (info->out[i].patch)
218 continue;
219 for (c = 0; c < 4; ++c) {
220 if (!(info->out[i].mask & (1 << c)))
221 continue;
222 assert(info->out[i].slot[c] >= 0x40 / 4);
223 a = info->out[i].slot[c] - 0x40 / 4;
224 vp->hdr[13 + a / 32] |= 1 << (a % 32);
225 if (info->out[i].oread)
226 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
227 }
228 }
229
230 for (i = 0; i < info->numSysVals; ++i) {
231 switch (info->sv[i].sn) {
232 case TGSI_SEMANTIC_PRIMID:
233 vp->hdr[5] |= 1 << 24;
234 break;
235 case TGSI_SEMANTIC_INSTANCEID:
236 vp->hdr[10] |= 1 << 30;
237 break;
238 case TGSI_SEMANTIC_VERTEXID:
239 vp->hdr[10] |= 1 << 31;
240 break;
241 case TGSI_SEMANTIC_TESSCOORD:
242 /* We don't have the mask, nor the slots populated. While this could
243 * be achieved, the vast majority of the time if either of the coords
244 * are read, then both will be read.
245 */
246 nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
247 nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
248 break;
249 default:
250 break;
251 }
252 }
253
254 vp->vp.clip_enable =
255 (1 << (info->io.clipDistances + info->io.cullDistances)) - 1;
256 for (i = 0; i < info->io.cullDistances; ++i)
257 vp->vp.clip_mode |= 1 << ((info->io.clipDistances + i) * 4);
258
259 if (info->io.genUserClip < 0)
260 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
261
262 return 0;
263 }
264
265 static int
266 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
267 {
268 vp->hdr[0] = 0x20061 | (1 << 10);
269 vp->hdr[4] = 0xff000;
270
271 return nvc0_vtgp_gen_header(vp, info);
272 }
273
274 static void
275 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
276 {
277 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
278 tp->tp.tess_mode = ~0;
279 return;
280 }
281 switch (info->prop.tp.domain) {
282 case PIPE_PRIM_LINES:
283 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
284 break;
285 case PIPE_PRIM_TRIANGLES:
286 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
287 break;
288 case PIPE_PRIM_QUADS:
289 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
290 break;
291 default:
292 tp->tp.tess_mode = ~0;
293 return;
294 }
295
296 if (info->prop.tp.winding > 0)
297 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
298
299 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
300 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
301
302 switch (info->prop.tp.partitioning) {
303 case PIPE_TESS_SPACING_EQUAL:
304 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
305 break;
306 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
307 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
308 break;
309 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
310 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
311 break;
312 default:
313 assert(!"invalid tessellator partitioning");
314 break;
315 }
316 }
317
318 static int
319 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
320 {
321 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
322
323 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
324
325 if (info->numPatchConstants)
326 opcs = 8 + info->numPatchConstants * 4;
327
328 tcp->hdr[0] = 0x20061 | (2 << 10);
329
330 tcp->hdr[1] = opcs << 24;
331 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
332
333 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
334
335 nvc0_vtgp_gen_header(tcp, info);
336
337 nvc0_tp_get_tess_mode(tcp, info);
338
339 return 0;
340 }
341
342 static int
343 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
344 {
345 tep->tp.input_patch_size = ~0;
346
347 tep->hdr[0] = 0x20061 | (3 << 10);
348 tep->hdr[4] = 0xff000;
349
350 nvc0_vtgp_gen_header(tep, info);
351
352 nvc0_tp_get_tess_mode(tep, info);
353
354 tep->hdr[18] |= 0x3 << 12; /* ? */
355
356 return 0;
357 }
358
359 static int
360 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
361 {
362 gp->hdr[0] = 0x20061 | (4 << 10);
363
364 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
365
366 switch (info->prop.gp.outputPrim) {
367 case PIPE_PRIM_POINTS:
368 gp->hdr[3] = 0x01000000;
369 gp->hdr[0] |= 0xf0000000;
370 break;
371 case PIPE_PRIM_LINE_STRIP:
372 gp->hdr[3] = 0x06000000;
373 gp->hdr[0] |= 0x10000000;
374 break;
375 case PIPE_PRIM_TRIANGLE_STRIP:
376 gp->hdr[3] = 0x07000000;
377 gp->hdr[0] |= 0x10000000;
378 break;
379 default:
380 assert(0);
381 break;
382 }
383
384 gp->hdr[4] = MIN2(info->prop.gp.maxVertices, 1024);
385
386 return nvc0_vtgp_gen_header(gp, info);
387 }
388
389 #define NVC0_INTERP_FLAT (1 << 0)
390 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
391 #define NVC0_INTERP_LINEAR (3 << 0)
392 #define NVC0_INTERP_CENTROID (1 << 2)
393
394 static uint8_t
395 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
396 {
397 if (var->linear)
398 return NVC0_INTERP_LINEAR;
399 if (var->flat)
400 return NVC0_INTERP_FLAT;
401 return NVC0_INTERP_PERSPECTIVE;
402 }
403
404 static int
405 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
406 {
407 unsigned i, c, a, m;
408
409 /* just 00062 on Kepler */
410 fp->hdr[0] = 0x20062 | (5 << 10);
411 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
412
413 if (info->prop.fp.usesDiscard)
414 fp->hdr[0] |= 0x8000;
415 if (info->prop.fp.numColourResults > 1)
416 fp->hdr[0] |= 0x4000;
417 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
418 fp->hdr[19] |= 0x1;
419 if (info->prop.fp.writesDepth) {
420 fp->hdr[19] |= 0x2;
421 fp->flags[0] = 0x11; /* deactivate ZCULL */
422 }
423
424 for (i = 0; i < info->numInputs; ++i) {
425 m = nvc0_hdr_interp_mode(&info->in[i]);
426 if (info->in[i].sn == TGSI_SEMANTIC_COLOR) {
427 fp->fp.colors |= 1 << info->in[i].si;
428 if (info->in[i].sc)
429 fp->fp.color_interp[info->in[i].si] = m | (info->in[i].mask << 4);
430 }
431 for (c = 0; c < 4; ++c) {
432 if (!(info->in[i].mask & (1 << c)))
433 continue;
434 a = info->in[i].slot[c];
435 if (info->in[i].slot[0] >= (0x060 / 4) &&
436 info->in[i].slot[0] <= (0x07c / 4)) {
437 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
438 } else
439 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
440 info->in[i].slot[0] <= (0x2fc / 4)) {
441 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
442 } else {
443 if (info->in[i].slot[c] < (0x040 / 4) ||
444 info->in[i].slot[c] > (0x380 / 4))
445 continue;
446 a *= 2;
447 if (info->in[i].slot[0] >= (0x300 / 4))
448 a -= 32;
449 fp->hdr[4 + a / 32] |= m << (a % 32);
450 }
451 }
452 }
453
454 for (i = 0; i < info->numOutputs; ++i) {
455 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
456 fp->hdr[18] |= 0xf << info->out[i].slot[0];
457 }
458
459 /* There are no "regular" attachments, but the shader still needs to be
460 * executed. It seems like it wants to think that it has some color
461 * outputs in order to actually run.
462 */
463 if (info->prop.fp.numColourResults == 0 && !info->prop.fp.writesDepth)
464 fp->hdr[18] |= 0xf;
465
466 fp->fp.early_z = info->prop.fp.earlyFragTests;
467
468 return 0;
469 }
470
471 static struct nvc0_transform_feedback_state *
472 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
473 const struct pipe_stream_output_info *pso)
474 {
475 struct nvc0_transform_feedback_state *tfb;
476 unsigned b, i, c;
477
478 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
479 if (!tfb)
480 return NULL;
481 for (b = 0; b < 4; ++b) {
482 tfb->stride[b] = pso->stride[b] * 4;
483 tfb->varying_count[b] = 0;
484 }
485 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
486
487 for (i = 0; i < pso->num_outputs; ++i) {
488 unsigned s = pso->output[i].start_component;
489 unsigned p = pso->output[i].dst_offset;
490 b = pso->output[i].output_buffer;
491
492 for (c = 0; c < pso->output[i].num_components; ++c)
493 tfb->varying_index[b][p++] =
494 info->out[pso->output[i].register_index].slot[s + c];
495
496 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
497 tfb->stream[b] = pso->output[i].stream;
498 }
499 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
500 for (c = tfb->varying_count[b]; c & 3; ++c)
501 tfb->varying_index[b][c] = 0;
502
503 return tfb;
504 }
505
506 #ifdef DEBUG
507 static void
508 nvc0_program_dump(struct nvc0_program *prog)
509 {
510 unsigned pos;
511
512 if (prog->type != PIPE_SHADER_COMPUTE) {
513 for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
514 debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
515 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
516 }
517 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
518 for (pos = 0; pos < prog->code_size / 4; ++pos) {
519 if ((pos % 8) == 0)
520 debug_printf("\n");
521 debug_printf("%08x ", prog->code[pos]);
522 }
523 debug_printf("\n");
524 }
525 #endif
526
527 bool
528 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
529 struct pipe_debug_callback *debug)
530 {
531 struct nv50_ir_prog_info *info;
532 int ret;
533
534 info = CALLOC_STRUCT(nv50_ir_prog_info);
535 if (!info)
536 return false;
537
538 info->type = prog->type;
539 info->target = chipset;
540 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
541 info->bin.source = (void *)prog->pipe.tokens;
542
543 info->io.genUserClip = prog->vp.num_ucps;
544 info->io.auxCBSlot = 15;
545 info->io.ucpBase = NVC0_CB_AUX_UCP_INFO;
546 info->io.drawInfoBase = NVC0_CB_AUX_DRAW_INFO;
547
548 if (prog->type == PIPE_SHADER_COMPUTE) {
549 if (chipset >= NVISA_GK104_CHIPSET) {
550 info->io.auxCBSlot = 7;
551 info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
552 info->prop.cp.gridInfoBase = NVC0_CB_AUX_GRID_INFO;
553 info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
554 }
555 info->io.msInfoCBSlot = 0;
556 info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
557 info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
558 info->io.suInfoBase = 0; /* TODO */
559 } else {
560 if (chipset >= NVISA_GK104_CHIPSET) {
561 info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
562 }
563 info->io.sampleInfoBase = NVC0_CB_AUX_SAMPLE_INFO;
564 info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
565 info->io.msInfoCBSlot = 15;
566 info->io.msInfoBase = 0; /* TODO */
567 info->io.suInfoBase = 0; /* TODO */
568 }
569
570 info->assignSlots = nvc0_program_assign_varying_slots;
571
572 #ifdef DEBUG
573 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
574 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
575 #else
576 info->optLevel = 3;
577 #endif
578
579 ret = nv50_ir_generate_code(info);
580 if (ret) {
581 NOUVEAU_ERR("shader translation failed: %i\n", ret);
582 goto out;
583 }
584 if (prog->type != PIPE_SHADER_COMPUTE)
585 FREE(info->bin.syms);
586
587 prog->code = info->bin.code;
588 prog->code_size = info->bin.codeSize;
589 prog->immd_data = info->immd.buf;
590 prog->immd_size = info->immd.bufSize;
591 prog->relocs = info->bin.relocData;
592 prog->interps = info->bin.interpData;
593 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
594 prog->num_barriers = info->numBarriers;
595
596 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
597 prog->vp.need_draw_parameters = info->prop.vp.usesDrawParameters;
598
599 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
600 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
601 prog->vp.edgeflag = info->io.edgeFlagIn;
602
603 switch (prog->type) {
604 case PIPE_SHADER_VERTEX:
605 ret = nvc0_vp_gen_header(prog, info);
606 break;
607 case PIPE_SHADER_TESS_CTRL:
608 ret = nvc0_tcp_gen_header(prog, info);
609 break;
610 case PIPE_SHADER_TESS_EVAL:
611 ret = nvc0_tep_gen_header(prog, info);
612 break;
613 case PIPE_SHADER_GEOMETRY:
614 ret = nvc0_gp_gen_header(prog, info);
615 break;
616 case PIPE_SHADER_FRAGMENT:
617 ret = nvc0_fp_gen_header(prog, info);
618 break;
619 case PIPE_SHADER_COMPUTE:
620 prog->cp.syms = info->bin.syms;
621 prog->cp.num_syms = info->bin.numSyms;
622 break;
623 default:
624 ret = -1;
625 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
626 break;
627 }
628 if (ret)
629 goto out;
630
631 if (info->bin.tlsSpace) {
632 assert(info->bin.tlsSpace < (1 << 24));
633 prog->hdr[0] |= 1 << 26;
634 prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
635 prog->need_tls = true;
636 }
637 /* TODO: factor 2 only needed where joinat/precont is used,
638 * and we only have to count non-uniform branches
639 */
640 /*
641 if ((info->maxCFDepth * 2) > 16) {
642 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
643 prog->need_tls = true;
644 }
645 */
646 if (info->io.globalAccess)
647 prog->hdr[0] |= 1 << 26;
648 if (info->io.globalAccess & 0x2)
649 prog->hdr[0] |= 1 << 16;
650 if (info->io.fp64)
651 prog->hdr[0] |= 1 << 27;
652
653 if (prog->pipe.stream_output.num_outputs)
654 prog->tfb = nvc0_program_create_tfb_state(info,
655 &prog->pipe.stream_output);
656
657 pipe_debug_message(debug, SHADER_INFO,
658 "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
659 prog->type, info->bin.tlsSpace, prog->num_gprs,
660 info->bin.instructions, info->bin.codeSize);
661
662 out:
663 FREE(info);
664 return !ret;
665 }
666
667 bool
668 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
669 {
670 struct nvc0_screen *screen = nvc0->screen;
671 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
672 int ret;
673 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
674 uint32_t lib_pos = screen->lib_code->start;
675 uint32_t code_pos;
676
677 /* c[] bindings need to be aligned to 0x100, but we could use relocations
678 * to save space. */
679 if (prog->immd_size) {
680 prog->immd_base = size;
681 size = align(size, 0x40);
682 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
683 }
684 /* On Fermi, SP_START_ID must be aligned to 0x40.
685 * On Kepler, the first instruction must be aligned to 0x80 because
686 * latency information is expected only at certain positions.
687 */
688 if (screen->base.class_3d >= NVE4_3D_CLASS)
689 size = size + (is_cp ? 0x40 : 0x70);
690 size = align(size, 0x40);
691
692 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
693 if (ret) {
694 struct nouveau_heap *heap = screen->text_heap;
695 /* Note that the code library, which is allocated before anything else,
696 * does not have a priv pointer. We can stop once we hit it.
697 */
698 while (heap->next && heap->next->priv) {
699 struct nvc0_program *evict = heap->next->priv;
700 nouveau_heap_free(&evict->mem);
701 }
702 debug_printf("WARNING: out of code space, evicting all shaders.\n");
703 ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
704 if (ret) {
705 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
706 return false;
707 }
708 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
709 }
710 prog->code_base = prog->mem->start;
711 prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
712 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
713 prog->mem->start + prog->mem->size));
714
715 if (!is_cp) {
716 if (screen->base.class_3d >= NVE4_3D_CLASS) {
717 switch (prog->mem->start & 0xff) {
718 case 0x40: prog->code_base += 0x70; break;
719 case 0x80: prog->code_base += 0x30; break;
720 case 0xc0: prog->code_base += 0x70; break;
721 default:
722 prog->code_base += 0x30;
723 assert((prog->mem->start & 0xff) == 0x00);
724 break;
725 }
726 }
727 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
728 } else {
729 if (screen->base.class_3d >= NVE4_3D_CLASS) {
730 if (prog->mem->start & 0x40)
731 prog->code_base += 0x40;
732 assert((prog->code_base & 0x7f) == 0x00);
733 }
734 code_pos = prog->code_base;
735 }
736
737 if (prog->relocs)
738 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
739 if (prog->interps) {
740 nv50_ir_change_interp(prog->interps, prog->code,
741 prog->fp.force_persample_interp,
742 prog->fp.flatshade);
743 for (int i = 0; i < 2; i++) {
744 unsigned mask = prog->fp.color_interp[i] >> 4;
745 unsigned interp = prog->fp.color_interp[i] & 3;
746 if (!mask)
747 continue;
748 prog->hdr[14] &= ~(0xff << (8 * i));
749 if (prog->fp.flatshade)
750 interp = NVC0_INTERP_FLAT;
751 for (int c = 0; c < 4; c++)
752 if (mask & (1 << c))
753 prog->hdr[14] |= interp << (2 * (4 * i + c));
754 }
755 }
756
757 #ifdef DEBUG
758 if (debug_get_bool_option("NV50_PROG_DEBUG", false))
759 nvc0_program_dump(prog);
760 #endif
761
762 if (!is_cp)
763 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
764 NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr);
765 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
766 NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code);
767 if (prog->immd_size)
768 nvc0->base.push_data(&nvc0->base,
769 screen->text, prog->immd_base, NV_VRAM_DOMAIN(&screen->base),
770 prog->immd_size, prog->immd_data);
771
772 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
773 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
774
775 return true;
776 }
777
778 /* Upload code for builtin functions like integer division emulation. */
779 void
780 nvc0_program_library_upload(struct nvc0_context *nvc0)
781 {
782 struct nvc0_screen *screen = nvc0->screen;
783 int ret;
784 uint32_t size;
785 const uint32_t *code;
786
787 if (screen->lib_code)
788 return;
789
790 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
791 if (!size)
792 return;
793
794 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
795 &screen->lib_code);
796 if (ret)
797 return;
798
799 nvc0->base.push_data(&nvc0->base,
800 screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
801 size, code);
802 /* no need for a memory barrier, will be emitted with first program */
803 }
804
805 void
806 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
807 {
808 const struct pipe_shader_state pipe = prog->pipe;
809 const ubyte type = prog->type;
810
811 if (prog->mem)
812 nouveau_heap_free(&prog->mem);
813 FREE(prog->code); /* may be 0 for hardcoded shaders */
814 FREE(prog->immd_data);
815 FREE(prog->relocs);
816 FREE(prog->interps);
817 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
818 FREE(prog->cp.syms);
819 if (prog->tfb) {
820 if (nvc0->state.tfb == prog->tfb)
821 nvc0->state.tfb = NULL;
822 FREE(prog->tfb);
823 }
824
825 memset(prog, 0, sizeof(*prog));
826
827 prog->pipe = pipe;
828 prog->type = type;
829 }
830
831 uint32_t
832 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
833 {
834 const struct nv50_ir_prog_symbol *syms =
835 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
836 unsigned base = 0;
837 unsigned i;
838 if (prog->type != PIPE_SHADER_COMPUTE)
839 base = NVC0_SHADER_HEADER_SIZE;
840 for (i = 0; i < prog->cp.num_syms; ++i)
841 if (syms[i].label == label)
842 return prog->code_base + base + syms[i].offset;
843 return prog->code_base; /* no symbols or symbol not found */
844 }
845
846 void
847 nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
848 {
849 struct ureg_program *ureg;
850
851 ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
852 if (!ureg)
853 return;
854
855 ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
856 ureg_END(ureg);
857
858 nvc0->tcp_empty = ureg_create_shader_and_destroy(ureg, &nvc0->base.pipe);
859 }