src/gallium/drivers/nouveau/nvc0/nvc0_program.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_defines.h"
  24
  25 #include "nvc0/nvc0_context.h"
  26
  27 #include "codegen/nv50_ir_driver.h"
  28 #include "nvc0/nve4_compute.h"
  29
  30 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
  31  * 124 scalar varying values.
  32  */
  33 static uint32_t
  34 nvc0_shader_input_address(unsigned sn, unsigned si)
  35 {
  36    switch (sn) {
  37    case TGSI_SEMANTIC_TESSOUTER:    return 0x000 + si * 0x4;
  38    case TGSI_SEMANTIC_TESSINNER:    return 0x010 + si * 0x4;
  39    case TGSI_SEMANTIC_PATCH:        return 0x020 + si * 0x10;
  40    case TGSI_SEMANTIC_PRIMID:       return 0x060;
  41    case TGSI_SEMANTIC_LAYER:        return 0x064;
  42    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
  43    case TGSI_SEMANTIC_PSIZE:        return 0x06c;
  44    case TGSI_SEMANTIC_POSITION:     return 0x070;
  45    case TGSI_SEMANTIC_GENERIC:      return 0x080 + si * 0x10;
  46    case TGSI_SEMANTIC_FOG:          return 0x2e8;
  47    case TGSI_SEMANTIC_COLOR:        return 0x280 + si * 0x10;
  48    case TGSI_SEMANTIC_BCOLOR:       return 0x2a0 + si * 0x10;
  49    case TGSI_SEMANTIC_CLIPDIST:     return 0x2c0 + si * 0x10;
  50    case TGSI_SEMANTIC_CLIPVERTEX:   return 0x270;
  51    case TGSI_SEMANTIC_PCOORD:       return 0x2e0;
  52    case TGSI_SEMANTIC_TESSCOORD:    return 0x2f0;
  53    case TGSI_SEMANTIC_INSTANCEID:   return 0x2f8;
  54    case TGSI_SEMANTIC_VERTEXID:     return 0x2fc;
  55    case TGSI_SEMANTIC_TEXCOORD:     return 0x300 + si * 0x10;
  56    case TGSI_SEMANTIC_FACE:         return 0x3fc;
  57    default:
  58       assert(!"invalid TGSI input semantic");
  59       return ~0;
  60    }
  61 }
  62
  63 static uint32_t
  64 nvc0_shader_output_address(unsigned sn, unsigned si)
  65 {
  66    switch (sn) {
  67    case TGSI_SEMANTIC_TESSOUTER:     return 0x000 + si * 0x4;
  68    case TGSI_SEMANTIC_TESSINNER:     return 0x010 + si * 0x4;
  69    case TGSI_SEMANTIC_PATCH:         return 0x020 + si * 0x10;
  70    case TGSI_SEMANTIC_PRIMID:        return 0x060;
  71    case TGSI_SEMANTIC_LAYER:         return 0x064;
  72    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
  73    case TGSI_SEMANTIC_PSIZE:         return 0x06c;
  74    case TGSI_SEMANTIC_POSITION:      return 0x070;
  75    case TGSI_SEMANTIC_GENERIC:       return 0x080 + si * 0x10;
  76    case TGSI_SEMANTIC_FOG:           return 0x2e8;
  77    case TGSI_SEMANTIC_COLOR:         return 0x280 + si * 0x10;
  78    case TGSI_SEMANTIC_BCOLOR:        return 0x2a0 + si * 0x10;
  79    case TGSI_SEMANTIC_CLIPDIST:      return 0x2c0 + si * 0x10;
  80    case TGSI_SEMANTIC_CLIPVERTEX:    return 0x270;
  81    case TGSI_SEMANTIC_TEXCOORD:      return 0x300 + si * 0x10;
  82    case TGSI_SEMANTIC_EDGEFLAG:      return ~0;
  83    default:
  84       assert(!"invalid TGSI output semantic");
  85       return ~0;
  86    }
  87 }
  88
  89 static int
  90 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
  91 {
  92    unsigned i, c, n;
  93
  94    for (n = 0, i = 0; i < info->numInputs; ++i) {
  95       switch (info->in[i].sn) {
  96       case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
  97       case TGSI_SEMANTIC_VERTEXID:
  98          info->in[i].mask = 0x1;
  99          info->in[i].slot[0] =
 100             nvc0_shader_input_address(info->in[i].sn, 0) / 4;
 101          continue;
 102       default:
 103          break;
 104       }
 105       for (c = 0; c < 4; ++c)
 106          info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
 107       ++n;
 108    }
 109
 110    return 0;
 111 }
 112
 113 static int
 114 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
 115 {
 116    unsigned offset;
 117    unsigned i, c;
 118
 119    for (i = 0; i < info->numInputs; ++i) {
 120       offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
 121
 122       for (c = 0; c < 4; ++c)
 123          info->in[i].slot[c] = (offset + c * 0x4) / 4;
 124    }
 125
 126    return 0;
 127 }
 128
 129 static int
 130 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
 131 {
 132    unsigned count = info->prop.fp.numColourResults * 4;
 133    unsigned i, c;
 134
 135    for (i = 0; i < info->numOutputs; ++i)
 136       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
 137          for (c = 0; c < 4; ++c)
 138             info->out[i].slot[c] = info->out[i].si * 4 + c;
 139
 140    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 141       info->out[info->io.sampleMask].slot[0] = count++;
 142    else
 143    if (info->target >= 0xe0)
 144       count++; /* on Kepler, depth is always last colour reg + 2 */
 145
 146    if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
 147       info->out[info->io.fragDepth].slot[2] = count;
 148
 149    return 0;
 150 }
 151
 152 static int
 153 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
 154 {
 155    unsigned offset;
 156    unsigned i, c;
 157
 158    for (i = 0; i < info->numOutputs; ++i) {
 159       offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
 160
 161       for (c = 0; c < 4; ++c)
 162          info->out[i].slot[c] = (offset + c * 0x4) / 4;
 163    }
 164
 165    return 0;
 166 }
 167
 168 static int
 169 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
 170 {
 171    int ret;
 172
 173    if (info->type == PIPE_SHADER_VERTEX)
 174       ret = nvc0_vp_assign_input_slots(info);
 175    else
 176       ret = nvc0_sp_assign_input_slots(info);
 177    if (ret)
 178       return ret;
 179
 180    if (info->type == PIPE_SHADER_FRAGMENT)
 181       ret = nvc0_fp_assign_output_slots(info);
 182    else
 183       ret = nvc0_sp_assign_output_slots(info);
 184    return ret;
 185 }
 186
 187 static inline void
 188 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
 189 {
 190    uint8_t min = (vp->hdr[4] >> 12) & 0xff;
 191    uint8_t max = (vp->hdr[4] >> 24);
 192
 193    min = MIN2(min, slot);
 194    max = MAX2(max, slot);
 195
 196    vp->hdr[4] = (max << 24) | (min << 12);
 197 }
 198
 199 /* Common part of header generation for VP, TCP, TEP and GP. */
 200 static int
 201 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
 202 {
 203    unsigned i, c, a;
 204
 205    for (i = 0; i < info->numInputs; ++i) {
 206       if (info->in[i].patch)
 207          continue;
 208       for (c = 0; c < 4; ++c) {
 209          a = info->in[i].slot[c];
 210          if (info->in[i].mask & (1 << c))
 211             vp->hdr[5 + a / 32] |= 1 << (a % 32);
 212       }
 213    }
 214
 215    for (i = 0; i < info->numOutputs; ++i) {
 216       if (info->out[i].patch)
 217          continue;
 218       for (c = 0; c < 4; ++c) {
 219          if (!(info->out[i].mask & (1 << c)))
 220             continue;
 221          assert(info->out[i].slot[c] >= 0x40 / 4);
 222          a = info->out[i].slot[c] - 0x40 / 4;
 223          vp->hdr[13 + a / 32] |= 1 << (a % 32);
 224          if (info->out[i].oread)
 225             nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
 226       }
 227    }
 228
 229    for (i = 0; i < info->numSysVals; ++i) {
 230       switch (info->sv[i].sn) {
 231       case TGSI_SEMANTIC_PRIMID:
 232          vp->hdr[5] |= 1 << 24;
 233          break;
 234       case TGSI_SEMANTIC_INSTANCEID:
 235          vp->hdr[10] |= 1 << 30;
 236          break;
 237       case TGSI_SEMANTIC_VERTEXID:
 238          vp->hdr[10] |= 1 << 31;
 239          break;
 240       case TGSI_SEMANTIC_TESSCOORD:
 241          /* We don't have the mask, nor the slots populated. While this could
 242           * be achieved, the vast majority of the time if either of the coords
 243           * are read, then both will be read.
 244           */
 245          nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
 246          nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
 247          break;
 248       default:
 249          break;
 250       }
 251    }
 252
 253    vp->vp.clip_enable = info->io.clipDistanceMask;
 254    for (i = 0; i < 8; ++i)
 255       if (info->io.cullDistanceMask & (1 << i))
 256          vp->vp.clip_mode |= 1 << (i * 4);
 257
 258    if (info->io.genUserClip < 0)
 259       vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
 260
 261    return 0;
 262 }
 263
 264 static int
 265 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
 266 {
 267    vp->hdr[0] = 0x20061 | (1 << 10);
 268    vp->hdr[4] = 0xff000;
 269
 270    vp->hdr[18] = info->io.clipDistanceMask;
 271
 272    return nvc0_vtgp_gen_header(vp, info);
 273 }
 274
 275 static void
 276 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
 277 {
 278    if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
 279       tp->tp.tess_mode = ~0;
 280       return;
 281    }
 282    switch (info->prop.tp.domain) {
 283    case PIPE_PRIM_LINES:
 284       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
 285       break;
 286    case PIPE_PRIM_TRIANGLES:
 287       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
 288       if (info->prop.tp.winding > 0)
 289          tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
 290       break;
 291    case PIPE_PRIM_QUADS:
 292       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
 293       break;
 294    default:
 295       tp->tp.tess_mode = ~0;
 296       return;
 297    }
 298    if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
 299       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
 300
 301    switch (info->prop.tp.partitioning) {
 302    case PIPE_TESS_SPACING_EQUAL:
 303       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
 304       break;
 305    case PIPE_TESS_SPACING_FRACTIONAL_ODD:
 306       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
 307       break;
 308    case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
 309       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
 310       break;
 311    default:
 312       assert(!"invalid tessellator partitioning");
 313       break;
 314    }
 315 }
 316
 317 static int
 318 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
 319 {
 320    unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
 321
 322    tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
 323
 324    if (info->numPatchConstants)
 325       opcs = 8 + info->numPatchConstants * 4;
 326
 327    tcp->hdr[0] = 0x20061 | (2 << 10);
 328
 329    tcp->hdr[1] = opcs << 24;
 330    tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
 331
 332    tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
 333
 334    nvc0_vtgp_gen_header(tcp, info);
 335
 336    nvc0_tp_get_tess_mode(tcp, info);
 337
 338    return 0;
 339 }
 340
 341 static int
 342 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
 343 {
 344    tep->tp.input_patch_size = ~0;
 345
 346    tep->hdr[0] = 0x20061 | (3 << 10);
 347    tep->hdr[4] = 0xff000;
 348
 349    nvc0_vtgp_gen_header(tep, info);
 350
 351    nvc0_tp_get_tess_mode(tep, info);
 352
 353    tep->hdr[18] |= 0x3 << 12; /* ? */
 354
 355    return 0;
 356 }
 357
 358 static int
 359 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
 360 {
 361    gp->hdr[0] = 0x20061 | (4 << 10);
 362
 363    gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
 364
 365    switch (info->prop.gp.outputPrim) {
 366    case PIPE_PRIM_POINTS:
 367       gp->hdr[3] = 0x01000000;
 368       gp->hdr[0] |= 0xf0000000;
 369       break;
 370    case PIPE_PRIM_LINE_STRIP:
 371       gp->hdr[3] = 0x06000000;
 372       gp->hdr[0] |= 0x10000000;
 373       break;
 374    case PIPE_PRIM_TRIANGLE_STRIP:
 375       gp->hdr[3] = 0x07000000;
 376       gp->hdr[0] |= 0x10000000;
 377       break;
 378    default:
 379       assert(0);
 380       break;
 381    }
 382
 383    gp->hdr[4] = MIN2(info->prop.gp.maxVertices, 1024);
 384
 385    return nvc0_vtgp_gen_header(gp, info);
 386 }
 387
 388 #define NVC0_INTERP_FLAT          (1 << 0)
 389 #define NVC0_INTERP_PERSPECTIVE   (2 << 0)
 390 #define NVC0_INTERP_LINEAR        (3 << 0)
 391 #define NVC0_INTERP_CENTROID      (1 << 2)
 392
 393 static uint8_t
 394 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
 395 {
 396    if (var->linear)
 397       return NVC0_INTERP_LINEAR;
 398    if (var->flat)
 399       return NVC0_INTERP_FLAT;
 400    return NVC0_INTERP_PERSPECTIVE;
 401 }
 402
 403 static int
 404 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
 405 {
 406    unsigned i, c, a, m;
 407
 408    /* just 00062 on Kepler */
 409    fp->hdr[0] = 0x20062 | (5 << 10);
 410    fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
 411
 412    if (info->prop.fp.usesDiscard)
 413       fp->hdr[0] |= 0x8000;
 414    if (info->prop.fp.numColourResults > 1)
 415       fp->hdr[0] |= 0x4000;
 416    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 417       fp->hdr[19] |= 0x1;
 418    if (info->prop.fp.writesDepth) {
 419       fp->hdr[19] |= 0x2;
 420       fp->flags[0] = 0x11; /* deactivate ZCULL */
 421    }
 422
 423    for (i = 0; i < info->numInputs; ++i) {
 424       m = nvc0_hdr_interp_mode(&info->in[i]);
 425       for (c = 0; c < 4; ++c) {
 426          if (!(info->in[i].mask & (1 << c)))
 427             continue;
 428          a = info->in[i].slot[c];
 429          if (info->in[i].slot[0] >= (0x060 / 4) &&
 430              info->in[i].slot[0] <= (0x07c / 4)) {
 431             fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
 432          } else
 433          if (info->in[i].slot[0] >= (0x2c0 / 4) &&
 434              info->in[i].slot[0] <= (0x2fc / 4)) {
 435             fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
 436          } else {
 437             if (info->in[i].slot[c] < (0x040 / 4) ||
 438                 info->in[i].slot[c] > (0x380 / 4))
 439                continue;
 440             a *= 2;
 441             if (info->in[i].slot[0] >= (0x300 / 4))
 442                a -= 32;
 443             fp->hdr[4 + a / 32] |= m << (a % 32);
 444          }
 445       }
 446    }
 447
 448    for (i = 0; i < info->numOutputs; ++i) {
 449       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
 450          fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
 451    }
 452
 453    fp->fp.early_z = info->prop.fp.earlyFragTests;
 454
 455    return 0;
 456 }
 457
 458 static struct nvc0_transform_feedback_state *
 459 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
 460                               const struct pipe_stream_output_info *pso)
 461 {
 462    struct nvc0_transform_feedback_state *tfb;
 463    unsigned b, i, c;
 464
 465    tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
 466    if (!tfb)
 467       return NULL;
 468    for (b = 0; b < 4; ++b) {
 469       tfb->stride[b] = pso->stride[b] * 4;
 470       tfb->varying_count[b] = 0;
 471    }
 472    memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
 473
 474    for (i = 0; i < pso->num_outputs; ++i) {
 475       unsigned s = pso->output[i].start_component;
 476       unsigned p = pso->output[i].dst_offset;
 477       b = pso->output[i].output_buffer;
 478
 479       for (c = 0; c < pso->output[i].num_components; ++c)
 480          tfb->varying_index[b][p++] =
 481             info->out[pso->output[i].register_index].slot[s + c];
 482
 483       tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
 484       tfb->stream[b] = pso->output[i].stream;
 485    }
 486    for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
 487       for (c = tfb->varying_count[b]; c & 3; ++c)
 488          tfb->varying_index[b][c] = 0;
 489
 490    return tfb;
 491 }
 492
 493 #ifdef DEBUG
 494 static void
 495 nvc0_program_dump(struct nvc0_program *prog)
 496 {
 497    unsigned pos;
 498
 499    if (prog->type != PIPE_SHADER_COMPUTE) {
 500       for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
 501          debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
 502                       pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
 503    }
 504    debug_printf("shader binary code (0x%x bytes):", prog->code_size);
 505    for (pos = 0; pos < prog->code_size / 4; ++pos) {
 506       if ((pos % 8) == 0)
 507          debug_printf("\n");
 508       debug_printf("%08x ", prog->code[pos]);
 509    }
 510    debug_printf("\n");
 511 }
 512 #endif
 513
 514 bool
 515 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
 516 {
 517    struct nv50_ir_prog_info *info;
 518    int ret;
 519
 520    info = CALLOC_STRUCT(nv50_ir_prog_info);
 521    if (!info)
 522       return false;
 523
 524    info->type = prog->type;
 525    info->target = chipset;
 526    info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
 527    info->bin.source = (void *)prog->pipe.tokens;
 528
 529    info->io.genUserClip = prog->vp.num_ucps;
 530    info->io.ucpBase = 256;
 531    info->io.ucpCBSlot = 15;
 532    info->io.sampleInterp = prog->fp.sample_interp;
 533
 534    if (prog->type == PIPE_SHADER_COMPUTE) {
 535       if (chipset >= NVISA_GK104_CHIPSET) {
 536          info->io.resInfoCBSlot = 0;
 537          info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
 538          info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
 539          info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
 540       }
 541       info->io.msInfoCBSlot = 0;
 542       info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
 543    } else {
 544       if (chipset >= NVISA_GK104_CHIPSET) {
 545          info->io.texBindBase = 0x20;
 546          info->io.suInfoBase = 0; /* TODO */
 547       }
 548       info->io.resInfoCBSlot = 15;
 549       info->io.sampleInfoBase = 256 + 128;
 550       info->io.msInfoCBSlot = 15;
 551       info->io.msInfoBase = 0; /* TODO */
 552    }
 553
 554    info->assignSlots = nvc0_program_assign_varying_slots;
 555
 556 #ifdef DEBUG
 557    info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
 558    info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
 559 #else
 560    info->optLevel = 3;
 561 #endif
 562
 563    ret = nv50_ir_generate_code(info);
 564    if (ret) {
 565       NOUVEAU_ERR("shader translation failed: %i\n", ret);
 566       goto out;
 567    }
 568    if (prog->type != PIPE_SHADER_COMPUTE)
 569       FREE(info->bin.syms);
 570
 571    prog->code = info->bin.code;
 572    prog->code_size = info->bin.codeSize;
 573    prog->immd_data = info->immd.buf;
 574    prog->immd_size = info->immd.bufSize;
 575    prog->relocs = info->bin.relocData;
 576    prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
 577    prog->num_barriers = info->numBarriers;
 578
 579    prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
 580
 581    if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
 582       info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
 583    prog->vp.edgeflag = info->io.edgeFlagIn;
 584
 585    switch (prog->type) {
 586    case PIPE_SHADER_VERTEX:
 587       ret = nvc0_vp_gen_header(prog, info);
 588       break;
 589    case PIPE_SHADER_TESS_CTRL:
 590       ret = nvc0_tcp_gen_header(prog, info);
 591       break;
 592    case PIPE_SHADER_TESS_EVAL:
 593       ret = nvc0_tep_gen_header(prog, info);
 594       break;
 595    case PIPE_SHADER_GEOMETRY:
 596       ret = nvc0_gp_gen_header(prog, info);
 597       break;
 598    case PIPE_SHADER_FRAGMENT:
 599       ret = nvc0_fp_gen_header(prog, info);
 600       break;
 601    case PIPE_SHADER_COMPUTE:
 602       prog->cp.syms = info->bin.syms;
 603       prog->cp.num_syms = info->bin.numSyms;
 604       break;
 605    default:
 606       ret = -1;
 607       NOUVEAU_ERR("unknown program type: %u\n", prog->type);
 608       break;
 609    }
 610    if (ret)
 611       goto out;
 612
 613    if (info->bin.tlsSpace) {
 614       assert(info->bin.tlsSpace < (1 << 24));
 615       prog->hdr[0] |= 1 << 26;
 616       prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
 617       prog->need_tls = true;
 618    }
 619    /* TODO: factor 2 only needed where joinat/precont is used,
 620     *       and we only have to count non-uniform branches
 621     */
 622    /*
 623    if ((info->maxCFDepth * 2) > 16) {
 624       prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
 625       prog->need_tls = true;
 626    }
 627    */
 628    if (info->io.globalAccess)
 629       prog->hdr[0] |= 1 << 16;
 630    if (info->io.fp64)
 631       prog->hdr[0] |= 1 << 27;
 632
 633    if (prog->pipe.stream_output.num_outputs)
 634       prog->tfb = nvc0_program_create_tfb_state(info,
 635                                                 &prog->pipe.stream_output);
 636
 637 out:
 638    FREE(info);
 639    return !ret;
 640 }
 641
 642 bool
 643 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
 644 {
 645    struct nvc0_screen *screen = nvc0->screen;
 646    const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
 647    int ret;
 648    uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
 649    uint32_t lib_pos = screen->lib_code->start;
 650    uint32_t code_pos;
 651
 652    /* c[] bindings need to be aligned to 0x100, but we could use relocations
 653     * to save space. */
 654    if (prog->immd_size) {
 655       prog->immd_base = size;
 656       size = align(size, 0x40);
 657       size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
 658    }
 659    /* On Fermi, SP_START_ID must be aligned to 0x40.
 660     * On Kepler, the first instruction must be aligned to 0x80 because
 661     * latency information is expected only at certain positions.
 662     */
 663    if (screen->base.class_3d >= NVE4_3D_CLASS)
 664       size = size + (is_cp ? 0x40 : 0x70);
 665    size = align(size, 0x40);
 666
 667    ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
 668    if (ret) {
 669       struct nouveau_heap *heap = screen->text_heap;
 670       /* Note that the code library, which is allocated before anything else,
 671        * does not have a priv pointer. We can stop once we hit it.
 672        */
 673       while (heap->next && heap->next->priv) {
 674          struct nvc0_program *evict = heap->next->priv;
 675          nouveau_heap_free(&evict->mem);
 676       }
 677       debug_printf("WARNING: out of code space, evicting all shaders.\n");
 678       ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
 679       if (ret) {
 680          NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
 681          return false;
 682       }
 683       IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
 684    }
 685    prog->code_base = prog->mem->start;
 686    prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
 687    assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
 688                                      prog->mem->start + prog->mem->size));
 689
 690    if (!is_cp) {
 691       if (screen->base.class_3d >= NVE4_3D_CLASS) {
 692          switch (prog->mem->start & 0xff) {
 693          case 0x40: prog->code_base += 0x70; break;
 694          case 0x80: prog->code_base += 0x30; break;
 695          case 0xc0: prog->code_base += 0x70; break;
 696          default:
 697             prog->code_base += 0x30;
 698             assert((prog->mem->start & 0xff) == 0x00);
 699             break;
 700          }
 701       }
 702       code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
 703    } else {
 704       if (screen->base.class_3d >= NVE4_3D_CLASS) {
 705          if (prog->mem->start & 0x40)
 706             prog->code_base += 0x40;
 707          assert((prog->code_base & 0x7f) == 0x00);
 708       }
 709       code_pos = prog->code_base;
 710    }
 711
 712    if (prog->relocs)
 713       nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
 714
 715 #ifdef DEBUG
 716    if (debug_get_bool_option("NV50_PROG_DEBUG", false))
 717       nvc0_program_dump(prog);
 718 #endif
 719
 720    if (!is_cp)
 721       nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
 722                            NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr);
 723    nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
 724                         NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code);
 725    if (prog->immd_size)
 726       nvc0->base.push_data(&nvc0->base,
 727                            screen->text, prog->immd_base, NV_VRAM_DOMAIN(&screen->base),
 728                            prog->immd_size, prog->immd_data);
 729
 730    BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
 731    PUSH_DATA (nvc0->base.pushbuf, 0x1011);
 732
 733    return true;
 734 }
 735
 736 /* Upload code for builtin functions like integer division emulation. */
 737 void
 738 nvc0_program_library_upload(struct nvc0_context *nvc0)
 739 {
 740    struct nvc0_screen *screen = nvc0->screen;
 741    int ret;
 742    uint32_t size;
 743    const uint32_t *code;
 744
 745    if (screen->lib_code)
 746       return;
 747
 748    nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
 749    if (!size)
 750       return;
 751
 752    ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
 753                             &screen->lib_code);
 754    if (ret)
 755       return;
 756
 757    nvc0->base.push_data(&nvc0->base,
 758                         screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
 759                         size, code);
 760    /* no need for a memory barrier, will be emitted with first program */
 761 }
 762
 763 void
 764 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
 765 {
 766    const struct pipe_shader_state pipe = prog->pipe;
 767    const ubyte type = prog->type;
 768
 769    if (prog->mem)
 770       nouveau_heap_free(&prog->mem);
 771    FREE(prog->code); /* may be 0 for hardcoded shaders */
 772    FREE(prog->immd_data);
 773    FREE(prog->relocs);
 774    if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
 775       FREE(prog->cp.syms);
 776    if (prog->tfb) {
 777       if (nvc0->state.tfb == prog->tfb)
 778          nvc0->state.tfb = NULL;
 779       FREE(prog->tfb);
 780    }
 781
 782    memset(prog, 0, sizeof(*prog));
 783
 784    prog->pipe = pipe;
 785    prog->type = type;
 786 }
 787
 788 uint32_t
 789 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
 790 {
 791    const struct nv50_ir_prog_symbol *syms =
 792       (const struct nv50_ir_prog_symbol *)prog->cp.syms;
 793    unsigned base = 0;
 794    unsigned i;
 795    if (prog->type != PIPE_SHADER_COMPUTE)
 796       base = NVC0_SHADER_HEADER_SIZE;
 797    for (i = 0; i < prog->cp.num_syms; ++i)
 798       if (syms[i].label == label)
 799          return prog->code_base + base + syms[i].offset;
 800    return prog->code_base; /* no symbols or symbol not found */
 801 }