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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "tgsi/tgsi_ureg.h"
26
27 #include "nvc0/nvc0_context.h"
28
29 #include "codegen/nv50_ir_driver.h"
30 #include "nvc0/nve4_compute.h"
31
32 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
33 * 124 scalar varying values.
34 */
35 static uint32_t
36 nvc0_shader_input_address(unsigned sn, unsigned si)
37 {
38 switch (sn) {
39 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
40 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
41 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
42 case TGSI_SEMANTIC_PRIMID: return 0x060;
43 case TGSI_SEMANTIC_LAYER: return 0x064;
44 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
45 case TGSI_SEMANTIC_PSIZE: return 0x06c;
46 case TGSI_SEMANTIC_POSITION: return 0x070;
47 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
48 case TGSI_SEMANTIC_FOG: return 0x2e8;
49 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
50 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
51 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
52 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
53 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
54 case TGSI_SEMANTIC_TESSCOORD: return 0x2f0;
55 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
56 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
57 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
58 case TGSI_SEMANTIC_FACE: return 0x3fc;
59 default:
60 assert(!"invalid TGSI input semantic");
61 return ~0;
62 }
63 }
64
65 static uint32_t
66 nvc0_shader_output_address(unsigned sn, unsigned si)
67 {
68 switch (sn) {
69 case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
70 case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
71 case TGSI_SEMANTIC_PATCH: return 0x020 + si * 0x10;
72 case TGSI_SEMANTIC_PRIMID: return 0x060;
73 case TGSI_SEMANTIC_LAYER: return 0x064;
74 case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
75 case TGSI_SEMANTIC_PSIZE: return 0x06c;
76 case TGSI_SEMANTIC_POSITION: return 0x070;
77 case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
78 case TGSI_SEMANTIC_FOG: return 0x2e8;
79 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
80 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
81 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
82 case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
83 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
84 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
85 default:
86 assert(!"invalid TGSI output semantic");
87 return ~0;
88 }
89 }
90
91 static int
92 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
93 {
94 unsigned i, c, n;
95
96 for (n = 0, i = 0; i < info->numInputs; ++i) {
97 switch (info->in[i].sn) {
98 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
99 case TGSI_SEMANTIC_VERTEXID:
100 info->in[i].mask = 0x1;
101 info->in[i].slot[0] =
102 nvc0_shader_input_address(info->in[i].sn, 0) / 4;
103 continue;
104 default:
105 break;
106 }
107 for (c = 0; c < 4; ++c)
108 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
109 ++n;
110 }
111
112 return 0;
113 }
114
115 static int
116 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
117 {
118 unsigned offset;
119 unsigned i, c;
120
121 for (i = 0; i < info->numInputs; ++i) {
122 offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
123
124 for (c = 0; c < 4; ++c)
125 info->in[i].slot[c] = (offset + c * 0x4) / 4;
126 }
127
128 return 0;
129 }
130
131 static int
132 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
133 {
134 unsigned count = info->prop.fp.numColourResults * 4;
135 unsigned i, c;
136
137 for (i = 0; i < info->numOutputs; ++i)
138 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
139 for (c = 0; c < 4; ++c)
140 info->out[i].slot[c] = info->out[i].si * 4 + c;
141
142 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
143 info->out[info->io.sampleMask].slot[0] = count++;
144 else
145 if (info->target >= 0xe0)
146 count++; /* on Kepler, depth is always last colour reg + 2 */
147
148 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
149 info->out[info->io.fragDepth].slot[2] = count;
150
151 return 0;
152 }
153
154 static int
155 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
156 {
157 unsigned offset;
158 unsigned i, c;
159
160 for (i = 0; i < info->numOutputs; ++i) {
161 offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
162
163 for (c = 0; c < 4; ++c)
164 info->out[i].slot[c] = (offset + c * 0x4) / 4;
165 }
166
167 return 0;
168 }
169
170 static int
171 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
172 {
173 int ret;
174
175 if (info->type == PIPE_SHADER_VERTEX)
176 ret = nvc0_vp_assign_input_slots(info);
177 else
178 ret = nvc0_sp_assign_input_slots(info);
179 if (ret)
180 return ret;
181
182 if (info->type == PIPE_SHADER_FRAGMENT)
183 ret = nvc0_fp_assign_output_slots(info);
184 else
185 ret = nvc0_sp_assign_output_slots(info);
186 return ret;
187 }
188
189 static inline void
190 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
191 {
192 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
193 uint8_t max = (vp->hdr[4] >> 24);
194
195 min = MIN2(min, slot);
196 max = MAX2(max, slot);
197
198 vp->hdr[4] = (max << 24) | (min << 12);
199 }
200
201 /* Common part of header generation for VP, TCP, TEP and GP. */
202 static int
203 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
204 {
205 unsigned i, c, a;
206
207 for (i = 0; i < info->numInputs; ++i) {
208 if (info->in[i].patch)
209 continue;
210 for (c = 0; c < 4; ++c) {
211 a = info->in[i].slot[c];
212 if (info->in[i].mask & (1 << c))
213 vp->hdr[5 + a / 32] |= 1 << (a % 32);
214 }
215 }
216
217 for (i = 0; i < info->numOutputs; ++i) {
218 if (info->out[i].patch)
219 continue;
220 for (c = 0; c < 4; ++c) {
221 if (!(info->out[i].mask & (1 << c)))
222 continue;
223 assert(info->out[i].slot[c] >= 0x40 / 4);
224 a = info->out[i].slot[c] - 0x40 / 4;
225 vp->hdr[13 + a / 32] |= 1 << (a % 32);
226 if (info->out[i].oread)
227 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
228 }
229 }
230
231 for (i = 0; i < info->numSysVals; ++i) {
232 switch (info->sv[i].sn) {
233 case TGSI_SEMANTIC_PRIMID:
234 vp->hdr[5] |= 1 << 24;
235 break;
236 case TGSI_SEMANTIC_INSTANCEID:
237 vp->hdr[10] |= 1 << 30;
238 break;
239 case TGSI_SEMANTIC_VERTEXID:
240 vp->hdr[10] |= 1 << 31;
241 break;
242 case TGSI_SEMANTIC_TESSCOORD:
243 /* We don't have the mask, nor the slots populated. While this could
244 * be achieved, the vast majority of the time if either of the coords
245 * are read, then both will be read.
246 */
247 nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
248 nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
249 break;
250 default:
251 break;
252 }
253 }
254
255 vp->vp.clip_enable =
256 (1 << (info->io.clipDistances + info->io.cullDistances)) - 1;
257 for (i = 0; i < info->io.cullDistances; ++i)
258 vp->vp.clip_mode |= 1 << ((info->io.clipDistances + i) * 4);
259
260 if (info->io.genUserClip < 0)
261 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
262
263 return 0;
264 }
265
266 static int
267 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
268 {
269 vp->hdr[0] = 0x20061 | (1 << 10);
270 vp->hdr[4] = 0xff000;
271
272 return nvc0_vtgp_gen_header(vp, info);
273 }
274
275 static void
276 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
277 {
278 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
279 tp->tp.tess_mode = ~0;
280 return;
281 }
282 switch (info->prop.tp.domain) {
283 case PIPE_PRIM_LINES:
284 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
285 break;
286 case PIPE_PRIM_TRIANGLES:
287 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
288 if (info->prop.tp.winding > 0)
289 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
290 break;
291 case PIPE_PRIM_QUADS:
292 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
293 break;
294 default:
295 tp->tp.tess_mode = ~0;
296 return;
297 }
298 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
299 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
300
301 switch (info->prop.tp.partitioning) {
302 case PIPE_TESS_SPACING_EQUAL:
303 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
304 break;
305 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
306 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
307 break;
308 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
309 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
310 break;
311 default:
312 assert(!"invalid tessellator partitioning");
313 break;
314 }
315 }
316
317 static int
318 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
319 {
320 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
321
322 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
323
324 if (info->numPatchConstants)
325 opcs = 8 + info->numPatchConstants * 4;
326
327 tcp->hdr[0] = 0x20061 | (2 << 10);
328
329 tcp->hdr[1] = opcs << 24;
330 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
331
332 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
333
334 nvc0_vtgp_gen_header(tcp, info);
335
336 nvc0_tp_get_tess_mode(tcp, info);
337
338 return 0;
339 }
340
341 static int
342 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
343 {
344 tep->tp.input_patch_size = ~0;
345
346 tep->hdr[0] = 0x20061 | (3 << 10);
347 tep->hdr[4] = 0xff000;
348
349 nvc0_vtgp_gen_header(tep, info);
350
351 nvc0_tp_get_tess_mode(tep, info);
352
353 tep->hdr[18] |= 0x3 << 12; /* ? */
354
355 return 0;
356 }
357
358 static int
359 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
360 {
361 gp->hdr[0] = 0x20061 | (4 << 10);
362
363 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
364
365 switch (info->prop.gp.outputPrim) {
366 case PIPE_PRIM_POINTS:
367 gp->hdr[3] = 0x01000000;
368 gp->hdr[0] |= 0xf0000000;
369 break;
370 case PIPE_PRIM_LINE_STRIP:
371 gp->hdr[3] = 0x06000000;
372 gp->hdr[0] |= 0x10000000;
373 break;
374 case PIPE_PRIM_TRIANGLE_STRIP:
375 gp->hdr[3] = 0x07000000;
376 gp->hdr[0] |= 0x10000000;
377 break;
378 default:
379 assert(0);
380 break;
381 }
382
383 gp->hdr[4] = MIN2(info->prop.gp.maxVertices, 1024);
384
385 return nvc0_vtgp_gen_header(gp, info);
386 }
387
388 #define NVC0_INTERP_FLAT (1 << 0)
389 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
390 #define NVC0_INTERP_LINEAR (3 << 0)
391 #define NVC0_INTERP_CENTROID (1 << 2)
392
393 static uint8_t
394 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
395 {
396 if (var->linear)
397 return NVC0_INTERP_LINEAR;
398 if (var->flat)
399 return NVC0_INTERP_FLAT;
400 return NVC0_INTERP_PERSPECTIVE;
401 }
402
403 static int
404 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
405 {
406 unsigned i, c, a, m;
407
408 /* just 00062 on Kepler */
409 fp->hdr[0] = 0x20062 | (5 << 10);
410 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
411
412 if (info->prop.fp.usesDiscard)
413 fp->hdr[0] |= 0x8000;
414 if (info->prop.fp.numColourResults > 1)
415 fp->hdr[0] |= 0x4000;
416 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
417 fp->hdr[19] |= 0x1;
418 if (info->prop.fp.writesDepth) {
419 fp->hdr[19] |= 0x2;
420 fp->flags[0] = 0x11; /* deactivate ZCULL */
421 }
422
423 for (i = 0; i < info->numInputs; ++i) {
424 m = nvc0_hdr_interp_mode(&info->in[i]);
425 if (info->in[i].sn == TGSI_SEMANTIC_COLOR) {
426 fp->fp.colors |= 1 << info->in[i].si;
427 if (info->in[i].sc)
428 fp->fp.color_interp[info->in[i].si] = m | (info->in[i].mask << 4);
429 }
430 for (c = 0; c < 4; ++c) {
431 if (!(info->in[i].mask & (1 << c)))
432 continue;
433 a = info->in[i].slot[c];
434 if (info->in[i].slot[0] >= (0x060 / 4) &&
435 info->in[i].slot[0] <= (0x07c / 4)) {
436 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
437 } else
438 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
439 info->in[i].slot[0] <= (0x2fc / 4)) {
440 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
441 } else {
442 if (info->in[i].slot[c] < (0x040 / 4) ||
443 info->in[i].slot[c] > (0x380 / 4))
444 continue;
445 a *= 2;
446 if (info->in[i].slot[0] >= (0x300 / 4))
447 a -= 32;
448 fp->hdr[4 + a / 32] |= m << (a % 32);
449 }
450 }
451 }
452
453 for (i = 0; i < info->numOutputs; ++i) {
454 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
455 fp->hdr[18] |= 0xf << info->out[i].slot[0];
456 }
457
458 fp->fp.early_z = info->prop.fp.earlyFragTests;
459
460 return 0;
461 }
462
463 static struct nvc0_transform_feedback_state *
464 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
465 const struct pipe_stream_output_info *pso)
466 {
467 struct nvc0_transform_feedback_state *tfb;
468 unsigned b, i, c;
469
470 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
471 if (!tfb)
472 return NULL;
473 for (b = 0; b < 4; ++b) {
474 tfb->stride[b] = pso->stride[b] * 4;
475 tfb->varying_count[b] = 0;
476 }
477 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
478
479 for (i = 0; i < pso->num_outputs; ++i) {
480 unsigned s = pso->output[i].start_component;
481 unsigned p = pso->output[i].dst_offset;
482 b = pso->output[i].output_buffer;
483
484 for (c = 0; c < pso->output[i].num_components; ++c)
485 tfb->varying_index[b][p++] =
486 info->out[pso->output[i].register_index].slot[s + c];
487
488 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
489 tfb->stream[b] = pso->output[i].stream;
490 }
491 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
492 for (c = tfb->varying_count[b]; c & 3; ++c)
493 tfb->varying_index[b][c] = 0;
494
495 return tfb;
496 }
497
498 #ifdef DEBUG
499 static void
500 nvc0_program_dump(struct nvc0_program *prog)
501 {
502 unsigned pos;
503
504 if (prog->type != PIPE_SHADER_COMPUTE) {
505 for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
506 debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
507 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
508 }
509 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
510 for (pos = 0; pos < prog->code_size / 4; ++pos) {
511 if ((pos % 8) == 0)
512 debug_printf("\n");
513 debug_printf("%08x ", prog->code[pos]);
514 }
515 debug_printf("\n");
516 }
517 #endif
518
519 bool
520 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
521 struct pipe_debug_callback *debug)
522 {
523 struct nv50_ir_prog_info *info;
524 int ret;
525
526 info = CALLOC_STRUCT(nv50_ir_prog_info);
527 if (!info)
528 return false;
529
530 info->type = prog->type;
531 info->target = chipset;
532 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
533 info->bin.source = (void *)prog->pipe.tokens;
534
535 info->io.genUserClip = prog->vp.num_ucps;
536 info->io.ucpBase = 256;
537 info->io.ucpCBSlot = 15;
538
539 if (prog->type == PIPE_SHADER_COMPUTE) {
540 if (chipset >= NVISA_GK104_CHIPSET) {
541 info->io.resInfoCBSlot = 0;
542 info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
543 info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
544 info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
545 }
546 info->io.msInfoCBSlot = 0;
547 info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
548 } else {
549 if (chipset >= NVISA_GK104_CHIPSET) {
550 info->io.texBindBase = 0x20;
551 info->io.suInfoBase = 0; /* TODO */
552 }
553 info->io.resInfoCBSlot = 15;
554 info->io.sampleInfoBase = 256 + 128;
555 info->io.msInfoCBSlot = 15;
556 info->io.msInfoBase = 0; /* TODO */
557 }
558
559 info->assignSlots = nvc0_program_assign_varying_slots;
560
561 #ifdef DEBUG
562 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
563 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
564 #else
565 info->optLevel = 3;
566 #endif
567
568 ret = nv50_ir_generate_code(info);
569 if (ret) {
570 NOUVEAU_ERR("shader translation failed: %i\n", ret);
571 goto out;
572 }
573 if (prog->type != PIPE_SHADER_COMPUTE)
574 FREE(info->bin.syms);
575
576 prog->code = info->bin.code;
577 prog->code_size = info->bin.codeSize;
578 prog->immd_data = info->immd.buf;
579 prog->immd_size = info->immd.bufSize;
580 prog->relocs = info->bin.relocData;
581 prog->interps = info->bin.interpData;
582 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
583 prog->num_barriers = info->numBarriers;
584
585 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
586
587 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
588 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
589 prog->vp.edgeflag = info->io.edgeFlagIn;
590
591 switch (prog->type) {
592 case PIPE_SHADER_VERTEX:
593 ret = nvc0_vp_gen_header(prog, info);
594 break;
595 case PIPE_SHADER_TESS_CTRL:
596 ret = nvc0_tcp_gen_header(prog, info);
597 break;
598 case PIPE_SHADER_TESS_EVAL:
599 ret = nvc0_tep_gen_header(prog, info);
600 break;
601 case PIPE_SHADER_GEOMETRY:
602 ret = nvc0_gp_gen_header(prog, info);
603 break;
604 case PIPE_SHADER_FRAGMENT:
605 ret = nvc0_fp_gen_header(prog, info);
606 break;
607 case PIPE_SHADER_COMPUTE:
608 prog->cp.syms = info->bin.syms;
609 prog->cp.num_syms = info->bin.numSyms;
610 break;
611 default:
612 ret = -1;
613 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
614 break;
615 }
616 if (ret)
617 goto out;
618
619 if (info->bin.tlsSpace) {
620 assert(info->bin.tlsSpace < (1 << 24));
621 prog->hdr[0] |= 1 << 26;
622 prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
623 prog->need_tls = true;
624 }
625 /* TODO: factor 2 only needed where joinat/precont is used,
626 * and we only have to count non-uniform branches
627 */
628 /*
629 if ((info->maxCFDepth * 2) > 16) {
630 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
631 prog->need_tls = true;
632 }
633 */
634 if (info->io.globalAccess)
635 prog->hdr[0] |= 1 << 16;
636 if (info->io.fp64)
637 prog->hdr[0] |= 1 << 27;
638
639 if (prog->pipe.stream_output.num_outputs)
640 prog->tfb = nvc0_program_create_tfb_state(info,
641 &prog->pipe.stream_output);
642
643 pipe_debug_message(debug, SHADER_INFO,
644 "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
645 prog->type, info->bin.tlsSpace, prog->num_gprs,
646 info->bin.instructions, info->bin.codeSize);
647
648 out:
649 FREE(info);
650 return !ret;
651 }
652
653 bool
654 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
655 {
656 struct nvc0_screen *screen = nvc0->screen;
657 const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
658 int ret;
659 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
660 uint32_t lib_pos = screen->lib_code->start;
661 uint32_t code_pos;
662
663 /* c[] bindings need to be aligned to 0x100, but we could use relocations
664 * to save space. */
665 if (prog->immd_size) {
666 prog->immd_base = size;
667 size = align(size, 0x40);
668 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
669 }
670 /* On Fermi, SP_START_ID must be aligned to 0x40.
671 * On Kepler, the first instruction must be aligned to 0x80 because
672 * latency information is expected only at certain positions.
673 */
674 if (screen->base.class_3d >= NVE4_3D_CLASS)
675 size = size + (is_cp ? 0x40 : 0x70);
676 size = align(size, 0x40);
677
678 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
679 if (ret) {
680 struct nouveau_heap *heap = screen->text_heap;
681 /* Note that the code library, which is allocated before anything else,
682 * does not have a priv pointer. We can stop once we hit it.
683 */
684 while (heap->next && heap->next->priv) {
685 struct nvc0_program *evict = heap->next->priv;
686 nouveau_heap_free(&evict->mem);
687 }
688 debug_printf("WARNING: out of code space, evicting all shaders.\n");
689 ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
690 if (ret) {
691 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
692 return false;
693 }
694 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
695 }
696 prog->code_base = prog->mem->start;
697 prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
698 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
699 prog->mem->start + prog->mem->size));
700
701 if (!is_cp) {
702 if (screen->base.class_3d >= NVE4_3D_CLASS) {
703 switch (prog->mem->start & 0xff) {
704 case 0x40: prog->code_base += 0x70; break;
705 case 0x80: prog->code_base += 0x30; break;
706 case 0xc0: prog->code_base += 0x70; break;
707 default:
708 prog->code_base += 0x30;
709 assert((prog->mem->start & 0xff) == 0x00);
710 break;
711 }
712 }
713 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
714 } else {
715 if (screen->base.class_3d >= NVE4_3D_CLASS) {
716 if (prog->mem->start & 0x40)
717 prog->code_base += 0x40;
718 assert((prog->code_base & 0x7f) == 0x00);
719 }
720 code_pos = prog->code_base;
721 }
722
723 if (prog->relocs)
724 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
725 if (prog->interps) {
726 nv50_ir_change_interp(prog->interps, prog->code,
727 prog->fp.force_persample_interp,
728 prog->fp.flatshade);
729 for (int i = 0; i < 2; i++) {
730 unsigned mask = prog->fp.color_interp[i] >> 4;
731 unsigned interp = prog->fp.color_interp[i] & 3;
732 if (!mask)
733 continue;
734 prog->hdr[14] &= ~(0xff << (8 * i));
735 if (prog->fp.flatshade)
736 interp = NVC0_INTERP_FLAT;
737 for (int c = 0; c < 4; c++)
738 if (mask & (1 << c))
739 prog->hdr[14] |= interp << (2 * (4 * i + c));
740 }
741 }
742
743 #ifdef DEBUG
744 if (debug_get_bool_option("NV50_PROG_DEBUG", false))
745 nvc0_program_dump(prog);
746 #endif
747
748 if (!is_cp)
749 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
750 NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr);
751 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
752 NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code);
753 if (prog->immd_size)
754 nvc0->base.push_data(&nvc0->base,
755 screen->text, prog->immd_base, NV_VRAM_DOMAIN(&screen->base),
756 prog->immd_size, prog->immd_data);
757
758 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
759 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
760
761 return true;
762 }
763
764 /* Upload code for builtin functions like integer division emulation. */
765 void
766 nvc0_program_library_upload(struct nvc0_context *nvc0)
767 {
768 struct nvc0_screen *screen = nvc0->screen;
769 int ret;
770 uint32_t size;
771 const uint32_t *code;
772
773 if (screen->lib_code)
774 return;
775
776 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
777 if (!size)
778 return;
779
780 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
781 &screen->lib_code);
782 if (ret)
783 return;
784
785 nvc0->base.push_data(&nvc0->base,
786 screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
787 size, code);
788 /* no need for a memory barrier, will be emitted with first program */
789 }
790
791 void
792 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
793 {
794 const struct pipe_shader_state pipe = prog->pipe;
795 const ubyte type = prog->type;
796
797 if (prog->mem)
798 nouveau_heap_free(&prog->mem);
799 FREE(prog->code); /* may be 0 for hardcoded shaders */
800 FREE(prog->immd_data);
801 FREE(prog->relocs);
802 FREE(prog->interps);
803 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
804 FREE(prog->cp.syms);
805 if (prog->tfb) {
806 if (nvc0->state.tfb == prog->tfb)
807 nvc0->state.tfb = NULL;
808 FREE(prog->tfb);
809 }
810
811 memset(prog, 0, sizeof(*prog));
812
813 prog->pipe = pipe;
814 prog->type = type;
815 }
816
817 uint32_t
818 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
819 {
820 const struct nv50_ir_prog_symbol *syms =
821 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
822 unsigned base = 0;
823 unsigned i;
824 if (prog->type != PIPE_SHADER_COMPUTE)
825 base = NVC0_SHADER_HEADER_SIZE;
826 for (i = 0; i < prog->cp.num_syms; ++i)
827 if (syms[i].label == label)
828 return prog->code_base + base + syms[i].offset;
829 return prog->code_base; /* no symbols or symbol not found */
830 }
831
832 void
833 nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
834 {
835 struct ureg_program *ureg;
836
837 ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
838 if (!ureg)
839 return;
840
841 ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
842 ureg_END(ureg);
843
844 nvc0->tcp_empty = ureg_create_shader_and_destroy(ureg, &nvc0->base.pipe);
845 }