src/gallium/drivers/nouveau/nvc0/nvc0_program.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_defines.h"
  24
  25 #include "nvc0/nvc0_context.h"
  26
  27 #include "codegen/nv50_ir_driver.h"
  28 #include "nvc0/nve4_compute.h"
  29
  30 /* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
  31  * 124 scalar varying values.
  32  */
  33 static uint32_t
  34 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
  35 {
  36    switch (sn) {
  37    case TGSI_SEMANTIC_TESSOUTER:    return 0x000 + si * 0x4;
  38    case TGSI_SEMANTIC_TESSINNER:    return 0x010 + si * 0x4;
  39    case TGSI_SEMANTIC_PATCH:        return 0x020 + si * 0x10;
  40    case TGSI_SEMANTIC_PRIMID:       return 0x060;
  41    case TGSI_SEMANTIC_LAYER:        return 0x064;
  42    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
  43    case TGSI_SEMANTIC_PSIZE:        return 0x06c;
  44    case TGSI_SEMANTIC_POSITION:     return 0x070;
  45    case TGSI_SEMANTIC_GENERIC:      return ubase + si * 0x10;
  46    case TGSI_SEMANTIC_FOG:          return 0x2e8;
  47    case TGSI_SEMANTIC_COLOR:        return 0x280 + si * 0x10;
  48    case TGSI_SEMANTIC_BCOLOR:       return 0x2a0 + si * 0x10;
  49    case TGSI_SEMANTIC_CLIPDIST:     return 0x2c0 + si * 0x10;
  50    case TGSI_SEMANTIC_CLIPVERTEX:   return 0x270;
  51    case TGSI_SEMANTIC_PCOORD:       return 0x2e0;
  52    case TGSI_SEMANTIC_TESSCOORD:    return 0x2f0;
  53    case TGSI_SEMANTIC_INSTANCEID:   return 0x2f8;
  54    case TGSI_SEMANTIC_VERTEXID:     return 0x2fc;
  55    case TGSI_SEMANTIC_TEXCOORD:     return 0x300 + si * 0x10;
  56    case TGSI_SEMANTIC_FACE:         return 0x3fc;
  57    default:
  58       assert(!"invalid TGSI input semantic");
  59       return ~0;
  60    }
  61 }
  62
  63 static uint32_t
  64 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
  65 {
  66    switch (sn) {
  67    case TGSI_SEMANTIC_TESSOUTER:     return 0x000 + si * 0x4;
  68    case TGSI_SEMANTIC_TESSINNER:     return 0x010 + si * 0x4;
  69    case TGSI_SEMANTIC_PATCH:         return 0x020 + si * 0x10;
  70    case TGSI_SEMANTIC_PRIMID:        return 0x060;
  71    case TGSI_SEMANTIC_LAYER:         return 0x064;
  72    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
  73    case TGSI_SEMANTIC_PSIZE:         return 0x06c;
  74    case TGSI_SEMANTIC_POSITION:      return 0x070;
  75    case TGSI_SEMANTIC_GENERIC:       return ubase + si * 0x10;
  76    case TGSI_SEMANTIC_FOG:           return 0x2e8;
  77    case TGSI_SEMANTIC_COLOR:         return 0x280 + si * 0x10;
  78    case TGSI_SEMANTIC_BCOLOR:        return 0x2a0 + si * 0x10;
  79    case TGSI_SEMANTIC_CLIPDIST:      return 0x2c0 + si * 0x10;
  80    case TGSI_SEMANTIC_CLIPVERTEX:    return 0x270;
  81    case TGSI_SEMANTIC_TEXCOORD:      return 0x300 + si * 0x10;
  82    case TGSI_SEMANTIC_EDGEFLAG:      return ~0;
  83    default:
  84       assert(!"invalid TGSI output semantic");
  85       return ~0;
  86    }
  87 }
  88
  89 static int
  90 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
  91 {
  92    unsigned i, c, n;
  93
  94    for (n = 0, i = 0; i < info->numInputs; ++i) {
  95       switch (info->in[i].sn) {
  96       case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
  97       case TGSI_SEMANTIC_VERTEXID:
  98          info->in[i].mask = 0x1;
  99          info->in[i].slot[0] =
 100             nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
 101          continue;
 102       default:
 103          break;
 104       }
 105       for (c = 0; c < 4; ++c)
 106          info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
 107       ++n;
 108    }
 109
 110    return 0;
 111 }
 112
 113 static int
 114 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
 115 {
 116    unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
 117    unsigned offset;
 118    unsigned i, c;
 119
 120    for (i = 0; i < info->numInputs; ++i) {
 121       offset = nvc0_shader_input_address(info->in[i].sn,
 122                                          info->in[i].si, ubase);
 123
 124       for (c = 0; c < 4; ++c)
 125          info->in[i].slot[c] = (offset + c * 0x4) / 4;
 126    }
 127
 128    return 0;
 129 }
 130
 131 static int
 132 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
 133 {
 134    unsigned count = info->prop.fp.numColourResults * 4;
 135    unsigned i, c;
 136
 137    for (i = 0; i < info->numOutputs; ++i)
 138       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
 139          for (c = 0; c < 4; ++c)
 140             info->out[i].slot[c] = info->out[i].si * 4 + c;
 141
 142    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 143       info->out[info->io.sampleMask].slot[0] = count++;
 144    else
 145    if (info->target >= 0xe0)
 146       count++; /* on Kepler, depth is always last colour reg + 2 */
 147
 148    if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
 149       info->out[info->io.fragDepth].slot[2] = count;
 150
 151    return 0;
 152 }
 153
 154 static int
 155 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
 156 {
 157    unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
 158    unsigned offset;
 159    unsigned i, c;
 160
 161    for (i = 0; i < info->numOutputs; ++i) {
 162       offset = nvc0_shader_output_address(info->out[i].sn,
 163                                           info->out[i].si, ubase);
 164
 165       for (c = 0; c < 4; ++c)
 166          info->out[i].slot[c] = (offset + c * 0x4) / 4;
 167    }
 168
 169    return 0;
 170 }
 171
 172 static int
 173 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
 174 {
 175    int ret;
 176
 177    if (info->type == PIPE_SHADER_VERTEX)
 178       ret = nvc0_vp_assign_input_slots(info);
 179    else
 180       ret = nvc0_sp_assign_input_slots(info);
 181    if (ret)
 182       return ret;
 183
 184    if (info->type == PIPE_SHADER_FRAGMENT)
 185       ret = nvc0_fp_assign_output_slots(info);
 186    else
 187       ret = nvc0_sp_assign_output_slots(info);
 188    return ret;
 189 }
 190
 191 static inline void
 192 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
 193 {
 194    uint8_t min = (vp->hdr[4] >> 12) & 0xff;
 195    uint8_t max = (vp->hdr[4] >> 24);
 196
 197    min = MIN2(min, slot);
 198    max = MAX2(max, slot);
 199
 200    vp->hdr[4] = (max << 24) | (min << 12);
 201 }
 202
 203 /* Common part of header generation for VP, TCP, TEP and GP. */
 204 static int
 205 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
 206 {
 207    unsigned i, c, a;
 208
 209    for (i = 0; i < info->numInputs; ++i) {
 210       if (info->in[i].patch)
 211          continue;
 212       for (c = 0; c < 4; ++c) {
 213          a = info->in[i].slot[c];
 214          if (info->in[i].mask & (1 << c))
 215             vp->hdr[5 + a / 32] |= 1 << (a % 32);
 216       }
 217    }
 218
 219    for (i = 0; i < info->numOutputs; ++i) {
 220       if (info->out[i].patch)
 221          continue;
 222       for (c = 0; c < 4; ++c) {
 223          if (!(info->out[i].mask & (1 << c)))
 224             continue;
 225          assert(info->out[i].slot[c] >= 0x40 / 4);
 226          a = info->out[i].slot[c] - 0x40 / 4;
 227          vp->hdr[13 + a / 32] |= 1 << (a % 32);
 228          if (info->out[i].oread)
 229             nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
 230       }
 231    }
 232
 233    for (i = 0; i < info->numSysVals; ++i) {
 234       switch (info->sv[i].sn) {
 235       case TGSI_SEMANTIC_PRIMID:
 236          vp->hdr[5] |= 1 << 24;
 237          break;
 238       case TGSI_SEMANTIC_INSTANCEID:
 239          vp->hdr[10] |= 1 << 30;
 240          break;
 241       case TGSI_SEMANTIC_VERTEXID:
 242          vp->hdr[10] |= 1 << 31;
 243          break;
 244       case TGSI_SEMANTIC_TESSCOORD:
 245          /* We don't have the mask, nor the slots populated. While this could
 246           * be achieved, the vast majority of the time if either of the coords
 247           * are read, then both will be read.
 248           */
 249          nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
 250          nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
 251          break;
 252       default:
 253          break;
 254       }
 255    }
 256
 257    vp->vp.clip_enable = info->io.clipDistanceMask;
 258    for (i = 0; i < 8; ++i)
 259       if (info->io.cullDistanceMask & (1 << i))
 260          vp->vp.clip_mode |= 1 << (i * 4);
 261
 262    if (info->io.genUserClip < 0)
 263       vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
 264
 265    return 0;
 266 }
 267
 268 static int
 269 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
 270 {
 271    vp->hdr[0] = 0x20061 | (1 << 10);
 272    vp->hdr[4] = 0xff000;
 273
 274    vp->hdr[18] = info->io.clipDistanceMask;
 275
 276    return nvc0_vtgp_gen_header(vp, info);
 277 }
 278
 279 static void
 280 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
 281 {
 282    if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
 283       tp->tp.tess_mode = ~0;
 284       return;
 285    }
 286    switch (info->prop.tp.domain) {
 287    case PIPE_PRIM_LINES:
 288       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
 289       break;
 290    case PIPE_PRIM_TRIANGLES:
 291       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
 292       if (info->prop.tp.winding > 0)
 293          tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
 294       break;
 295    case PIPE_PRIM_QUADS:
 296       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
 297       break;
 298    default:
 299       tp->tp.tess_mode = ~0;
 300       return;
 301    }
 302    if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
 303       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
 304
 305    switch (info->prop.tp.partitioning) {
 306    case PIPE_TESS_SPACING_EQUAL:
 307       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
 308       break;
 309    case PIPE_TESS_SPACING_FRACTIONAL_ODD:
 310       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
 311       break;
 312    case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
 313       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
 314       break;
 315    default:
 316       assert(!"invalid tessellator partitioning");
 317       break;
 318    }
 319 }
 320
 321 static int
 322 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
 323 {
 324    unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
 325
 326    tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
 327
 328    if (info->numPatchConstants)
 329       opcs = 8 + info->numPatchConstants * 4;
 330
 331    tcp->hdr[0] = 0x20061 | (2 << 10);
 332
 333    tcp->hdr[1] = opcs << 24;
 334    tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
 335
 336    tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
 337
 338    nvc0_vtgp_gen_header(tcp, info);
 339
 340    nvc0_tp_get_tess_mode(tcp, info);
 341
 342    return 0;
 343 }
 344
 345 static int
 346 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
 347 {
 348    tep->tp.input_patch_size = ~0;
 349
 350    tep->hdr[0] = 0x20061 | (3 << 10);
 351    tep->hdr[4] = 0xff000;
 352
 353    nvc0_vtgp_gen_header(tep, info);
 354
 355    nvc0_tp_get_tess_mode(tep, info);
 356
 357    tep->hdr[18] |= 0x3 << 12; /* ? */
 358
 359    return 0;
 360 }
 361
 362 static int
 363 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
 364 {
 365    gp->hdr[0] = 0x20061 | (4 << 10);
 366
 367    gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
 368
 369    switch (info->prop.gp.outputPrim) {
 370    case PIPE_PRIM_POINTS:
 371       gp->hdr[3] = 0x01000000;
 372       gp->hdr[0] |= 0xf0000000;
 373       break;
 374    case PIPE_PRIM_LINE_STRIP:
 375       gp->hdr[3] = 0x06000000;
 376       gp->hdr[0] |= 0x10000000;
 377       break;
 378    case PIPE_PRIM_TRIANGLE_STRIP:
 379       gp->hdr[3] = 0x07000000;
 380       gp->hdr[0] |= 0x10000000;
 381       break;
 382    default:
 383       assert(0);
 384       break;
 385    }
 386
 387    gp->hdr[4] = MIN2(info->prop.gp.maxVertices, 1024);
 388
 389    return nvc0_vtgp_gen_header(gp, info);
 390 }
 391
 392 #define NVC0_INTERP_FLAT          (1 << 0)
 393 #define NVC0_INTERP_PERSPECTIVE   (2 << 0)
 394 #define NVC0_INTERP_LINEAR        (3 << 0)
 395 #define NVC0_INTERP_CENTROID      (1 << 2)
 396
 397 static uint8_t
 398 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
 399 {
 400    if (var->linear)
 401       return NVC0_INTERP_LINEAR;
 402    if (var->flat)
 403       return NVC0_INTERP_FLAT;
 404    return NVC0_INTERP_PERSPECTIVE;
 405 }
 406
 407 static int
 408 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
 409 {
 410    unsigned i, c, a, m;
 411
 412    /* just 00062 on Kepler */
 413    fp->hdr[0] = 0x20062 | (5 << 10);
 414    fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
 415
 416    if (info->prop.fp.usesDiscard)
 417       fp->hdr[0] |= 0x8000;
 418    if (info->prop.fp.numColourResults > 1)
 419       fp->hdr[0] |= 0x4000;
 420    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 421       fp->hdr[19] |= 0x1;
 422    if (info->prop.fp.writesDepth) {
 423       fp->hdr[19] |= 0x2;
 424       fp->flags[0] = 0x11; /* deactivate ZCULL */
 425    }
 426
 427    for (i = 0; i < info->numInputs; ++i) {
 428       m = nvc0_hdr_interp_mode(&info->in[i]);
 429       for (c = 0; c < 4; ++c) {
 430          if (!(info->in[i].mask & (1 << c)))
 431             continue;
 432          a = info->in[i].slot[c];
 433          if (info->in[i].slot[0] >= (0x060 / 4) &&
 434              info->in[i].slot[0] <= (0x07c / 4)) {
 435             fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
 436          } else
 437          if (info->in[i].slot[0] >= (0x2c0 / 4) &&
 438              info->in[i].slot[0] <= (0x2fc / 4)) {
 439             fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x07ff0000;
 440          } else {
 441             if (info->in[i].slot[c] < (0x040 / 4) ||
 442                 info->in[i].slot[c] > (0x380 / 4))
 443                continue;
 444             a *= 2;
 445             if (info->in[i].slot[0] >= (0x300 / 4))
 446                a -= 32;
 447             fp->hdr[4 + a / 32] |= m << (a % 32);
 448          }
 449       }
 450    }
 451
 452    for (i = 0; i < info->numOutputs; ++i) {
 453       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
 454          fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
 455    }
 456
 457    fp->fp.early_z = info->prop.fp.earlyFragTests;
 458
 459    return 0;
 460 }
 461
 462 static struct nvc0_transform_feedback_state *
 463 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
 464                               const struct pipe_stream_output_info *pso)
 465 {
 466    struct nvc0_transform_feedback_state *tfb;
 467    unsigned b, i, c;
 468
 469    tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
 470    if (!tfb)
 471       return NULL;
 472    for (b = 0; b < 4; ++b) {
 473       tfb->stride[b] = pso->stride[b] * 4;
 474       tfb->varying_count[b] = 0;
 475    }
 476    memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
 477
 478    for (i = 0; i < pso->num_outputs; ++i) {
 479       unsigned s = pso->output[i].start_component;
 480       unsigned p = pso->output[i].dst_offset;
 481       b = pso->output[i].output_buffer;
 482
 483       for (c = 0; c < pso->output[i].num_components; ++c)
 484          tfb->varying_index[b][p++] =
 485             info->out[pso->output[i].register_index].slot[s + c];
 486
 487       tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
 488       tfb->stream[b] = pso->output[i].stream;
 489    }
 490    for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
 491       for (c = tfb->varying_count[b]; c & 3; ++c)
 492          tfb->varying_index[b][c] = 0;
 493
 494    return tfb;
 495 }
 496
 497 #ifdef DEBUG
 498 static void
 499 nvc0_program_dump(struct nvc0_program *prog)
 500 {
 501    unsigned pos;
 502
 503    if (prog->type != PIPE_SHADER_COMPUTE) {
 504       for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
 505          debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
 506                       pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
 507    }
 508    debug_printf("shader binary code (0x%x bytes):", prog->code_size);
 509    for (pos = 0; pos < prog->code_size / 4; ++pos) {
 510       if ((pos % 8) == 0)
 511          debug_printf("\n");
 512       debug_printf("%08x ", prog->code[pos]);
 513    }
 514    debug_printf("\n");
 515 }
 516 #endif
 517
 518 bool
 519 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
 520 {
 521    struct nv50_ir_prog_info *info;
 522    int ret;
 523
 524    info = CALLOC_STRUCT(nv50_ir_prog_info);
 525    if (!info)
 526       return false;
 527
 528    info->type = prog->type;
 529    info->target = chipset;
 530    info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
 531    info->bin.source = (void *)prog->pipe.tokens;
 532
 533    info->io.genUserClip = prog->vp.num_ucps;
 534    info->io.ucpBase = 256;
 535    info->io.ucpCBSlot = 15;
 536    info->io.sampleInterp = prog->fp.sample_interp;
 537
 538    if (prog->type == PIPE_SHADER_COMPUTE) {
 539       if (chipset >= NVISA_GK104_CHIPSET) {
 540          info->io.resInfoCBSlot = 0;
 541          info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
 542          info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
 543          info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
 544       }
 545       info->io.msInfoCBSlot = 0;
 546       info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
 547    } else {
 548       if (chipset >= NVISA_GK104_CHIPSET) {
 549          info->io.texBindBase = 0x20;
 550          info->io.suInfoBase = 0; /* TODO */
 551       }
 552       info->io.resInfoCBSlot = 15;
 553       info->io.sampleInfoBase = 256 + 128;
 554       info->io.msInfoCBSlot = 15;
 555       info->io.msInfoBase = 0; /* TODO */
 556    }
 557
 558    info->assignSlots = nvc0_program_assign_varying_slots;
 559
 560 #ifdef DEBUG
 561    info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
 562    info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
 563 #else
 564    info->optLevel = 3;
 565 #endif
 566
 567    ret = nv50_ir_generate_code(info);
 568    if (ret) {
 569       NOUVEAU_ERR("shader translation failed: %i\n", ret);
 570       goto out;
 571    }
 572    if (prog->type != PIPE_SHADER_COMPUTE)
 573       FREE(info->bin.syms);
 574
 575    prog->code = info->bin.code;
 576    prog->code_size = info->bin.codeSize;
 577    prog->immd_data = info->immd.buf;
 578    prog->immd_size = info->immd.bufSize;
 579    prog->relocs = info->bin.relocData;
 580    prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
 581    prog->num_barriers = info->numBarriers;
 582
 583    prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
 584
 585    if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
 586       info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
 587    prog->vp.edgeflag = info->io.edgeFlagIn;
 588
 589    switch (prog->type) {
 590    case PIPE_SHADER_VERTEX:
 591       ret = nvc0_vp_gen_header(prog, info);
 592       break;
 593    case PIPE_SHADER_TESS_CTRL:
 594       ret = nvc0_tcp_gen_header(prog, info);
 595       break;
 596    case PIPE_SHADER_TESS_EVAL:
 597       ret = nvc0_tep_gen_header(prog, info);
 598       break;
 599    case PIPE_SHADER_GEOMETRY:
 600       ret = nvc0_gp_gen_header(prog, info);
 601       break;
 602    case PIPE_SHADER_FRAGMENT:
 603       ret = nvc0_fp_gen_header(prog, info);
 604       break;
 605    case PIPE_SHADER_COMPUTE:
 606       prog->cp.syms = info->bin.syms;
 607       prog->cp.num_syms = info->bin.numSyms;
 608       break;
 609    default:
 610       ret = -1;
 611       NOUVEAU_ERR("unknown program type: %u\n", prog->type);
 612       break;
 613    }
 614    if (ret)
 615       goto out;
 616
 617    if (info->bin.tlsSpace) {
 618       assert(info->bin.tlsSpace < (1 << 24));
 619       prog->hdr[0] |= 1 << 26;
 620       prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
 621       prog->need_tls = true;
 622    }
 623    /* TODO: factor 2 only needed where joinat/precont is used,
 624     *       and we only have to count non-uniform branches
 625     */
 626    /*
 627    if ((info->maxCFDepth * 2) > 16) {
 628       prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
 629       prog->need_tls = true;
 630    }
 631    */
 632    if (info->io.globalAccess)
 633       prog->hdr[0] |= 1 << 16;
 634    if (info->io.fp64)
 635       prog->hdr[0] |= 1 << 27;
 636
 637    if (prog->pipe.stream_output.num_outputs)
 638       prog->tfb = nvc0_program_create_tfb_state(info,
 639                                                 &prog->pipe.stream_output);
 640
 641 out:
 642    FREE(info);
 643    return !ret;
 644 }
 645
 646 bool
 647 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
 648 {
 649    struct nvc0_screen *screen = nvc0->screen;
 650    const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
 651    int ret;
 652    uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
 653    uint32_t lib_pos = screen->lib_code->start;
 654    uint32_t code_pos;
 655
 656    /* c[] bindings need to be aligned to 0x100, but we could use relocations
 657     * to save space. */
 658    if (prog->immd_size) {
 659       prog->immd_base = size;
 660       size = align(size, 0x40);
 661       size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
 662    }
 663    /* On Fermi, SP_START_ID must be aligned to 0x40.
 664     * On Kepler, the first instruction must be aligned to 0x80 because
 665     * latency information is expected only at certain positions.
 666     */
 667    if (screen->base.class_3d >= NVE4_3D_CLASS)
 668       size = size + (is_cp ? 0x40 : 0x70);
 669    size = align(size, 0x40);
 670
 671    ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
 672    if (ret) {
 673       struct nouveau_heap *heap = screen->text_heap;
 674       /* Note that the code library, which is allocated before anything else,
 675        * does not have a priv pointer. We can stop once we hit it.
 676        */
 677       while (heap->next && heap->next->priv) {
 678          struct nvc0_program *evict = heap->next->priv;
 679          nouveau_heap_free(&evict->mem);
 680       }
 681       debug_printf("WARNING: out of code space, evicting all shaders.\n");
 682       ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
 683       if (ret) {
 684          NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
 685          return false;
 686       }
 687       IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
 688    }
 689    prog->code_base = prog->mem->start;
 690    prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
 691    assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
 692                                      prog->mem->start + prog->mem->size));
 693
 694    if (!is_cp) {
 695       if (screen->base.class_3d >= NVE4_3D_CLASS) {
 696          switch (prog->mem->start & 0xff) {
 697          case 0x40: prog->code_base += 0x70; break;
 698          case 0x80: prog->code_base += 0x30; break;
 699          case 0xc0: prog->code_base += 0x70; break;
 700          default:
 701             prog->code_base += 0x30;
 702             assert((prog->mem->start & 0xff) == 0x00);
 703             break;
 704          }
 705       }
 706       code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
 707    } else {
 708       if (screen->base.class_3d >= NVE4_3D_CLASS) {
 709          if (prog->mem->start & 0x40)
 710             prog->code_base += 0x40;
 711          assert((prog->code_base & 0x7f) == 0x00);
 712       }
 713       code_pos = prog->code_base;
 714    }
 715
 716    if (prog->relocs)
 717       nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
 718
 719 #ifdef DEBUG
 720    if (debug_get_bool_option("NV50_PROG_DEBUG", false))
 721       nvc0_program_dump(prog);
 722 #endif
 723
 724    if (!is_cp)
 725       nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
 726                            NV_VRAM_DOMAIN(&screen->base), NVC0_SHADER_HEADER_SIZE, prog->hdr);
 727    nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
 728                         NV_VRAM_DOMAIN(&screen->base), prog->code_size, prog->code);
 729    if (prog->immd_size)
 730       nvc0->base.push_data(&nvc0->base,
 731                            screen->text, prog->immd_base, NV_VRAM_DOMAIN(&screen->base),
 732                            prog->immd_size, prog->immd_data);
 733
 734    BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
 735    PUSH_DATA (nvc0->base.pushbuf, 0x1011);
 736
 737    return true;
 738 }
 739
 740 /* Upload code for builtin functions like integer division emulation. */
 741 void
 742 nvc0_program_library_upload(struct nvc0_context *nvc0)
 743 {
 744    struct nvc0_screen *screen = nvc0->screen;
 745    int ret;
 746    uint32_t size;
 747    const uint32_t *code;
 748
 749    if (screen->lib_code)
 750       return;
 751
 752    nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
 753    if (!size)
 754       return;
 755
 756    ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
 757                             &screen->lib_code);
 758    if (ret)
 759       return;
 760
 761    nvc0->base.push_data(&nvc0->base,
 762                         screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
 763                         size, code);
 764    /* no need for a memory barrier, will be emitted with first program */
 765 }
 766
 767 void
 768 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
 769 {
 770    const struct pipe_shader_state pipe = prog->pipe;
 771    const ubyte type = prog->type;
 772
 773    if (prog->mem)
 774       nouveau_heap_free(&prog->mem);
 775    FREE(prog->code); /* may be 0 for hardcoded shaders */
 776    FREE(prog->immd_data);
 777    FREE(prog->relocs);
 778    if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
 779       FREE(prog->cp.syms);
 780    if (prog->tfb) {
 781       if (nvc0->state.tfb == prog->tfb)
 782          nvc0->state.tfb = NULL;
 783       FREE(prog->tfb);
 784    }
 785
 786    memset(prog, 0, sizeof(*prog));
 787
 788    prog->pipe = pipe;
 789    prog->type = type;
 790 }
 791
 792 uint32_t
 793 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
 794 {
 795    const struct nv50_ir_prog_symbol *syms =
 796       (const struct nv50_ir_prog_symbol *)prog->cp.syms;
 797    unsigned base = 0;
 798    unsigned i;
 799    if (prog->type != PIPE_SHADER_COMPUTE)
 800       base = NVC0_SHADER_HEADER_SIZE;
 801    for (i = 0; i < prog->cp.num_syms; ++i)
 802       if (syms[i].label == label)
 803          return prog->code_base + base + syms[i].offset;
 804    return prog->code_base; /* no symbols or symbol not found */
 805 }