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nvc0: allocate more space before a counter is configured
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_query.c
1 /*
2 * Copyright 2011 Nouveau Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christoph Bumiller
23 */
24
25 #define NVC0_PUSH_EXPLICIT_SPACE_CHECKING
26
27 #include "nvc0/nvc0_context.h"
28 #include "nv_object.xml.h"
29 #include "nvc0/nve4_compute.xml.h"
30 #include "nvc0/nvc0_compute.xml.h"
31
32 #define NVC0_QUERY_STATE_READY 0
33 #define NVC0_QUERY_STATE_ACTIVE 1
34 #define NVC0_QUERY_STATE_ENDED 2
35 #define NVC0_QUERY_STATE_FLUSHED 3
36
37 struct nvc0_query {
38 uint32_t *data;
39 uint16_t type;
40 uint16_t index;
41 int8_t ctr[4];
42 uint32_t sequence;
43 struct nouveau_bo *bo;
44 uint32_t base;
45 uint32_t offset; /* base + i * rotate */
46 uint8_t state;
47 boolean is64bit;
48 uint8_t rotate;
49 int nesting; /* only used for occlusion queries */
50 union {
51 struct nouveau_mm_allocation *mm;
52 uint64_t value;
53 } u;
54 struct nouveau_fence *fence;
55 };
56
57 #define NVC0_QUERY_ALLOC_SPACE 256
58
59 static void nvc0_mp_pm_query_begin(struct nvc0_context *, struct nvc0_query *);
60 static void nvc0_mp_pm_query_end(struct nvc0_context *, struct nvc0_query *);
61 static boolean nvc0_mp_pm_query_result(struct nvc0_context *,
62 struct nvc0_query *, void *, boolean);
63
64 static INLINE struct nvc0_query *
65 nvc0_query(struct pipe_query *pipe)
66 {
67 return (struct nvc0_query *)pipe;
68 }
69
70 static boolean
71 nvc0_query_allocate(struct nvc0_context *nvc0, struct nvc0_query *q, int size)
72 {
73 struct nvc0_screen *screen = nvc0->screen;
74 int ret;
75
76 if (q->bo) {
77 nouveau_bo_ref(NULL, &q->bo);
78 if (q->u.mm) {
79 if (q->state == NVC0_QUERY_STATE_READY)
80 nouveau_mm_free(q->u.mm);
81 else
82 nouveau_fence_work(screen->base.fence.current,
83 nouveau_mm_free_work, q->u.mm);
84 }
85 }
86 if (size) {
87 q->u.mm = nouveau_mm_allocate(screen->base.mm_GART, size, &q->bo, &q->base);
88 if (!q->bo)
89 return FALSE;
90 q->offset = q->base;
91
92 ret = nouveau_bo_map(q->bo, 0, screen->base.client);
93 if (ret) {
94 nvc0_query_allocate(nvc0, q, 0);
95 return FALSE;
96 }
97 q->data = (uint32_t *)((uint8_t *)q->bo->map + q->base);
98 }
99 return TRUE;
100 }
101
102 static void
103 nvc0_query_destroy(struct pipe_context *pipe, struct pipe_query *pq)
104 {
105 nvc0_query_allocate(nvc0_context(pipe), nvc0_query(pq), 0);
106 nouveau_fence_ref(NULL, &nvc0_query(pq)->fence);
107 FREE(nvc0_query(pq));
108 }
109
110 static struct pipe_query *
111 nvc0_query_create(struct pipe_context *pipe, unsigned type, unsigned index)
112 {
113 struct nvc0_context *nvc0 = nvc0_context(pipe);
114 struct nvc0_query *q;
115 unsigned space = NVC0_QUERY_ALLOC_SPACE;
116
117 q = CALLOC_STRUCT(nvc0_query);
118 if (!q)
119 return NULL;
120
121 switch (type) {
122 case PIPE_QUERY_OCCLUSION_COUNTER:
123 case PIPE_QUERY_OCCLUSION_PREDICATE:
124 q->rotate = 32;
125 space = NVC0_QUERY_ALLOC_SPACE;
126 break;
127 case PIPE_QUERY_PIPELINE_STATISTICS:
128 q->is64bit = TRUE;
129 space = 512;
130 break;
131 case PIPE_QUERY_SO_STATISTICS:
132 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
133 q->is64bit = TRUE;
134 space = 64;
135 break;
136 case PIPE_QUERY_PRIMITIVES_GENERATED:
137 case PIPE_QUERY_PRIMITIVES_EMITTED:
138 q->is64bit = TRUE;
139 q->index = index;
140 space = 32;
141 break;
142 case PIPE_QUERY_TIME_ELAPSED:
143 case PIPE_QUERY_TIMESTAMP:
144 case PIPE_QUERY_TIMESTAMP_DISJOINT:
145 case PIPE_QUERY_GPU_FINISHED:
146 space = 32;
147 break;
148 case NVC0_QUERY_TFB_BUFFER_OFFSET:
149 space = 16;
150 break;
151 default:
152 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
153 if (type >= NVC0_QUERY_DRV_STAT(0) && type <= NVC0_QUERY_DRV_STAT_LAST) {
154 space = 0;
155 q->is64bit = true;
156 q->index = type - NVC0_QUERY_DRV_STAT(0);
157 break;
158 } else
159 #endif
160 if (nvc0->screen->base.device->drm_version >= 0x01000101) {
161 if (type >= NVE4_PM_QUERY(0) && type <= NVE4_PM_QUERY_LAST) {
162 /* for each MP:
163 * [00] = WS0.C0
164 * [04] = WS0.C1
165 * [08] = WS0.C2
166 * [0c] = WS0.C3
167 * [10] = WS1.C0
168 * [14] = WS1.C1
169 * [18] = WS1.C2
170 * [1c] = WS1.C3
171 * [20] = WS2.C0
172 * [24] = WS2.C1
173 * [28] = WS2.C2
174 * [2c] = WS2.C3
175 * [30] = WS3.C0
176 * [34] = WS3.C1
177 * [38] = WS3.C2
178 * [3c] = WS3.C3
179 * [40] = MP.C4
180 * [44] = MP.C5
181 * [48] = MP.C6
182 * [4c] = MP.C7
183 * [50] = WS0.sequence
184 * [54] = WS1.sequence
185 * [58] = WS2.sequence
186 * [5c] = WS3.sequence
187 */
188 space = (4 * 4 + 4 + 4) * nvc0->screen->mp_count * sizeof(uint32_t);
189 break;
190 } else
191 if (type >= NVC0_PM_QUERY(0) && type <= NVC0_PM_QUERY_LAST) {
192 /* for each MP:
193 * [00] = MP.C0
194 * [04] = MP.C1
195 * [08] = MP.C2
196 * [0c] = MP.C3
197 * [10] = MP.C4
198 * [14] = MP.C5
199 * [18] = MP.C6
200 * [1c] = MP.C7
201 * [20] = MP.sequence
202 */
203 space = (8 + 1) * nvc0->screen->mp_count * sizeof(uint32_t);
204 break;
205 }
206 }
207 debug_printf("invalid query type: %u\n", type);
208 FREE(q);
209 return NULL;
210 }
211 if (!nvc0_query_allocate(nvc0, q, space)) {
212 FREE(q);
213 return NULL;
214 }
215
216 q->type = type;
217
218 if (q->rotate) {
219 /* we advance before query_begin ! */
220 q->offset -= q->rotate;
221 q->data -= q->rotate / sizeof(*q->data);
222 } else
223 if (!q->is64bit)
224 q->data[0] = 0; /* initialize sequence */
225
226 return (struct pipe_query *)q;
227 }
228
229 static void
230 nvc0_query_get(struct nouveau_pushbuf *push, struct nvc0_query *q,
231 unsigned offset, uint32_t get)
232 {
233 offset += q->offset;
234
235 PUSH_SPACE(push, 5);
236 PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR);
237 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
238 PUSH_DATAh(push, q->bo->offset + offset);
239 PUSH_DATA (push, q->bo->offset + offset);
240 PUSH_DATA (push, q->sequence);
241 PUSH_DATA (push, get);
242 }
243
244 static void
245 nvc0_query_rotate(struct nvc0_context *nvc0, struct nvc0_query *q)
246 {
247 q->offset += q->rotate;
248 q->data += q->rotate / sizeof(*q->data);
249 if (q->offset - q->base == NVC0_QUERY_ALLOC_SPACE)
250 nvc0_query_allocate(nvc0, q, NVC0_QUERY_ALLOC_SPACE);
251 }
252
253 static void
254 nvc0_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
255 {
256 struct nvc0_context *nvc0 = nvc0_context(pipe);
257 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
258 struct nvc0_query *q = nvc0_query(pq);
259
260 /* For occlusion queries we have to change the storage, because a previous
261 * query might set the initial render conition to FALSE even *after* we re-
262 * initialized it to TRUE.
263 */
264 if (q->rotate) {
265 nvc0_query_rotate(nvc0, q);
266
267 /* XXX: can we do this with the GPU, and sync with respect to a previous
268 * query ?
269 */
270 q->data[0] = q->sequence; /* initialize sequence */
271 q->data[1] = 1; /* initial render condition = TRUE */
272 q->data[4] = q->sequence + 1; /* for comparison COND_MODE */
273 q->data[5] = 0;
274 }
275 q->sequence++;
276
277 switch (q->type) {
278 case PIPE_QUERY_OCCLUSION_COUNTER:
279 case PIPE_QUERY_OCCLUSION_PREDICATE:
280 q->nesting = nvc0->screen->num_occlusion_queries_active++;
281 if (q->nesting) {
282 nvc0_query_get(push, q, 0x10, 0x0100f002);
283 } else {
284 PUSH_SPACE(push, 3);
285 BEGIN_NVC0(push, NVC0_3D(COUNTER_RESET), 1);
286 PUSH_DATA (push, NVC0_3D_COUNTER_RESET_SAMPLECNT);
287 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1);
288 }
289 break;
290 case PIPE_QUERY_PRIMITIVES_GENERATED:
291 nvc0_query_get(push, q, 0x10, 0x09005002 | (q->index << 5));
292 break;
293 case PIPE_QUERY_PRIMITIVES_EMITTED:
294 nvc0_query_get(push, q, 0x10, 0x05805002 | (q->index << 5));
295 break;
296 case PIPE_QUERY_SO_STATISTICS:
297 nvc0_query_get(push, q, 0x20, 0x05805002 | (q->index << 5));
298 nvc0_query_get(push, q, 0x30, 0x06805002 | (q->index << 5));
299 break;
300 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
301 nvc0_query_get(push, q, 0x10, 0x03005002 | (q->index << 5));
302 break;
303 case PIPE_QUERY_TIME_ELAPSED:
304 nvc0_query_get(push, q, 0x10, 0x00005002);
305 break;
306 case PIPE_QUERY_PIPELINE_STATISTICS:
307 nvc0_query_get(push, q, 0xc0 + 0x00, 0x00801002); /* VFETCH, VERTICES */
308 nvc0_query_get(push, q, 0xc0 + 0x10, 0x01801002); /* VFETCH, PRIMS */
309 nvc0_query_get(push, q, 0xc0 + 0x20, 0x02802002); /* VP, LAUNCHES */
310 nvc0_query_get(push, q, 0xc0 + 0x30, 0x03806002); /* GP, LAUNCHES */
311 nvc0_query_get(push, q, 0xc0 + 0x40, 0x04806002); /* GP, PRIMS_OUT */
312 nvc0_query_get(push, q, 0xc0 + 0x50, 0x07804002); /* RAST, PRIMS_IN */
313 nvc0_query_get(push, q, 0xc0 + 0x60, 0x08804002); /* RAST, PRIMS_OUT */
314 nvc0_query_get(push, q, 0xc0 + 0x70, 0x0980a002); /* ROP, PIXELS */
315 nvc0_query_get(push, q, 0xc0 + 0x80, 0x0d808002); /* TCP, LAUNCHES */
316 nvc0_query_get(push, q, 0xc0 + 0x90, 0x0e809002); /* TEP, LAUNCHES */
317 break;
318 default:
319 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
320 if (q->type >= NVC0_QUERY_DRV_STAT(0) &&
321 q->type <= NVC0_QUERY_DRV_STAT_LAST) {
322 if (q->index >= 5)
323 q->u.value = nvc0->screen->base.stats.v[q->index];
324 else
325 q->u.value = 0;
326 } else
327 #endif
328 if ((q->type >= NVE4_PM_QUERY(0) && q->type <= NVE4_PM_QUERY_LAST) ||
329 (q->type >= NVC0_PM_QUERY(0) && q->type <= NVC0_PM_QUERY_LAST)) {
330 nvc0_mp_pm_query_begin(nvc0, q);
331 }
332 break;
333 }
334 q->state = NVC0_QUERY_STATE_ACTIVE;
335 }
336
337 static void
338 nvc0_query_end(struct pipe_context *pipe, struct pipe_query *pq)
339 {
340 struct nvc0_context *nvc0 = nvc0_context(pipe);
341 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
342 struct nvc0_query *q = nvc0_query(pq);
343
344 if (q->state != NVC0_QUERY_STATE_ACTIVE) {
345 /* some queries don't require 'begin' to be called (e.g. GPU_FINISHED) */
346 if (q->rotate)
347 nvc0_query_rotate(nvc0, q);
348 q->sequence++;
349 }
350 q->state = NVC0_QUERY_STATE_ENDED;
351
352 switch (q->type) {
353 case PIPE_QUERY_OCCLUSION_COUNTER:
354 case PIPE_QUERY_OCCLUSION_PREDICATE:
355 nvc0_query_get(push, q, 0, 0x0100f002);
356 if (--nvc0->screen->num_occlusion_queries_active == 0) {
357 PUSH_SPACE(push, 1);
358 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 0);
359 }
360 break;
361 case PIPE_QUERY_PRIMITIVES_GENERATED:
362 nvc0_query_get(push, q, 0, 0x09005002 | (q->index << 5));
363 break;
364 case PIPE_QUERY_PRIMITIVES_EMITTED:
365 nvc0_query_get(push, q, 0, 0x05805002 | (q->index << 5));
366 break;
367 case PIPE_QUERY_SO_STATISTICS:
368 nvc0_query_get(push, q, 0x00, 0x05805002 | (q->index << 5));
369 nvc0_query_get(push, q, 0x10, 0x06805002 | (q->index << 5));
370 break;
371 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
372 /* TODO: How do we sum over all streams for render condition ? */
373 /* PRIMS_DROPPED doesn't write sequence, use a ZERO query to sync on */
374 nvc0_query_get(push, q, 0x00, 0x03005002 | (q->index << 5));
375 nvc0_query_get(push, q, 0x20, 0x00005002);
376 break;
377 case PIPE_QUERY_TIMESTAMP:
378 case PIPE_QUERY_TIME_ELAPSED:
379 nvc0_query_get(push, q, 0, 0x00005002);
380 break;
381 case PIPE_QUERY_GPU_FINISHED:
382 nvc0_query_get(push, q, 0, 0x1000f010);
383 break;
384 case PIPE_QUERY_PIPELINE_STATISTICS:
385 nvc0_query_get(push, q, 0x00, 0x00801002); /* VFETCH, VERTICES */
386 nvc0_query_get(push, q, 0x10, 0x01801002); /* VFETCH, PRIMS */
387 nvc0_query_get(push, q, 0x20, 0x02802002); /* VP, LAUNCHES */
388 nvc0_query_get(push, q, 0x30, 0x03806002); /* GP, LAUNCHES */
389 nvc0_query_get(push, q, 0x40, 0x04806002); /* GP, PRIMS_OUT */
390 nvc0_query_get(push, q, 0x50, 0x07804002); /* RAST, PRIMS_IN */
391 nvc0_query_get(push, q, 0x60, 0x08804002); /* RAST, PRIMS_OUT */
392 nvc0_query_get(push, q, 0x70, 0x0980a002); /* ROP, PIXELS */
393 nvc0_query_get(push, q, 0x80, 0x0d808002); /* TCP, LAUNCHES */
394 nvc0_query_get(push, q, 0x90, 0x0e809002); /* TEP, LAUNCHES */
395 break;
396 case NVC0_QUERY_TFB_BUFFER_OFFSET:
397 /* indexed by TFB buffer instead of by vertex stream */
398 nvc0_query_get(push, q, 0x00, 0x0d005002 | (q->index << 5));
399 break;
400 default:
401 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
402 if (q->type >= NVC0_QUERY_DRV_STAT(0) &&
403 q->type <= NVC0_QUERY_DRV_STAT_LAST) {
404 q->u.value = nvc0->screen->base.stats.v[q->index] - q->u.value;
405 return;
406 } else
407 #endif
408 if ((q->type >= NVE4_PM_QUERY(0) && q->type <= NVE4_PM_QUERY_LAST) ||
409 (q->type >= NVC0_PM_QUERY(0) && q->type <= NVC0_PM_QUERY_LAST)) {
410 nvc0_mp_pm_query_end(nvc0, q);
411 }
412 break;
413 }
414 if (q->is64bit)
415 nouveau_fence_ref(nvc0->screen->base.fence.current, &q->fence);
416 }
417
418 static INLINE void
419 nvc0_query_update(struct nouveau_client *cli, struct nvc0_query *q)
420 {
421 if (q->is64bit) {
422 if (nouveau_fence_signalled(q->fence))
423 q->state = NVC0_QUERY_STATE_READY;
424 } else {
425 if (q->data[0] == q->sequence)
426 q->state = NVC0_QUERY_STATE_READY;
427 }
428 }
429
430 static boolean
431 nvc0_query_result(struct pipe_context *pipe, struct pipe_query *pq,
432 boolean wait, union pipe_query_result *result)
433 {
434 struct nvc0_context *nvc0 = nvc0_context(pipe);
435 struct nvc0_query *q = nvc0_query(pq);
436 uint64_t *res64 = (uint64_t*)result;
437 uint32_t *res32 = (uint32_t*)result;
438 boolean *res8 = (boolean*)result;
439 uint64_t *data64 = (uint64_t *)q->data;
440 unsigned i;
441
442 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
443 if (q->type >= NVC0_QUERY_DRV_STAT(0) &&
444 q->type <= NVC0_QUERY_DRV_STAT_LAST) {
445 res64[0] = q->u.value;
446 return TRUE;
447 } else
448 #endif
449 if ((q->type >= NVE4_PM_QUERY(0) && q->type <= NVE4_PM_QUERY_LAST) ||
450 (q->type >= NVC0_PM_QUERY(0) && q->type <= NVC0_PM_QUERY_LAST)) {
451 return nvc0_mp_pm_query_result(nvc0, q, result, wait);
452 }
453
454 if (q->state != NVC0_QUERY_STATE_READY)
455 nvc0_query_update(nvc0->screen->base.client, q);
456
457 if (q->state != NVC0_QUERY_STATE_READY) {
458 if (!wait) {
459 if (q->state != NVC0_QUERY_STATE_FLUSHED) {
460 q->state = NVC0_QUERY_STATE_FLUSHED;
461 /* flush for silly apps that spin on GL_QUERY_RESULT_AVAILABLE */
462 PUSH_KICK(nvc0->base.pushbuf);
463 }
464 return FALSE;
465 }
466 if (nouveau_bo_wait(q->bo, NOUVEAU_BO_RD, nvc0->screen->base.client))
467 return FALSE;
468 NOUVEAU_DRV_STAT(&nvc0->screen->base, query_sync_count, 1);
469 }
470 q->state = NVC0_QUERY_STATE_READY;
471
472 switch (q->type) {
473 case PIPE_QUERY_GPU_FINISHED:
474 res8[0] = TRUE;
475 break;
476 case PIPE_QUERY_OCCLUSION_COUNTER: /* u32 sequence, u32 count, u64 time */
477 res64[0] = q->data[1] - q->data[5];
478 break;
479 case PIPE_QUERY_OCCLUSION_PREDICATE:
480 res8[0] = q->data[1] != q->data[5];
481 break;
482 case PIPE_QUERY_PRIMITIVES_GENERATED: /* u64 count, u64 time */
483 case PIPE_QUERY_PRIMITIVES_EMITTED: /* u64 count, u64 time */
484 res64[0] = data64[0] - data64[2];
485 break;
486 case PIPE_QUERY_SO_STATISTICS:
487 res64[0] = data64[0] - data64[4];
488 res64[1] = data64[2] - data64[6];
489 break;
490 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
491 res8[0] = data64[0] != data64[2];
492 break;
493 case PIPE_QUERY_TIMESTAMP:
494 res64[0] = data64[1];
495 break;
496 case PIPE_QUERY_TIMESTAMP_DISJOINT:
497 res64[0] = 1000000000;
498 res8[8] = FALSE;
499 break;
500 case PIPE_QUERY_TIME_ELAPSED:
501 res64[0] = data64[1] - data64[3];
502 break;
503 case PIPE_QUERY_PIPELINE_STATISTICS:
504 for (i = 0; i < 10; ++i)
505 res64[i] = data64[i * 2] - data64[24 + i * 2];
506 break;
507 case NVC0_QUERY_TFB_BUFFER_OFFSET:
508 res32[0] = q->data[1];
509 break;
510 default:
511 assert(0); /* can't happen, we don't create queries with invalid type */
512 return FALSE;
513 }
514
515 return TRUE;
516 }
517
518 void
519 nvc0_query_fifo_wait(struct nouveau_pushbuf *push, struct pipe_query *pq)
520 {
521 struct nvc0_query *q = nvc0_query(pq);
522 unsigned offset = q->offset;
523
524 if (q->type == PIPE_QUERY_SO_OVERFLOW_PREDICATE) offset += 0x20;
525
526 PUSH_SPACE(push, 5);
527 PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
528 BEGIN_NVC0(push, SUBC_3D(NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH), 4);
529 PUSH_DATAh(push, q->bo->offset + offset);
530 PUSH_DATA (push, q->bo->offset + offset);
531 PUSH_DATA (push, q->sequence);
532 PUSH_DATA (push, (1 << 12) |
533 NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
534 }
535
536 static void
537 nvc0_render_condition(struct pipe_context *pipe,
538 struct pipe_query *pq,
539 boolean condition, uint mode)
540 {
541 struct nvc0_context *nvc0 = nvc0_context(pipe);
542 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
543 struct nvc0_query *q;
544 uint32_t cond;
545 boolean negated = FALSE;
546 boolean wait =
547 mode != PIPE_RENDER_COND_NO_WAIT &&
548 mode != PIPE_RENDER_COND_BY_REGION_NO_WAIT;
549
550 nvc0->cond_query = pq;
551 nvc0->cond_cond = condition;
552 nvc0->cond_mode = mode;
553
554 if (!pq) {
555 PUSH_SPACE(push, 1);
556 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
557 return;
558 }
559 q = nvc0_query(pq);
560
561 /* NOTE: comparison of 2 queries only works if both have completed */
562 switch (q->type) {
563 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
564 cond = negated ? NVC0_3D_COND_MODE_EQUAL :
565 NVC0_3D_COND_MODE_NOT_EQUAL;
566 wait = TRUE;
567 break;
568 case PIPE_QUERY_OCCLUSION_COUNTER:
569 case PIPE_QUERY_OCCLUSION_PREDICATE:
570 if (likely(!negated)) {
571 if (unlikely(q->nesting))
572 cond = wait ? NVC0_3D_COND_MODE_NOT_EQUAL :
573 NVC0_3D_COND_MODE_ALWAYS;
574 else
575 cond = NVC0_3D_COND_MODE_RES_NON_ZERO;
576 } else {
577 cond = wait ? NVC0_3D_COND_MODE_EQUAL : NVC0_3D_COND_MODE_ALWAYS;
578 }
579 break;
580 default:
581 assert(!"render condition query not a predicate");
582 mode = NVC0_3D_COND_MODE_ALWAYS;
583 break;
584 }
585
586 if (wait)
587 nvc0_query_fifo_wait(push, pq);
588
589 PUSH_SPACE(push, 7);
590 PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
591 BEGIN_NVC0(push, NVC0_3D(COND_ADDRESS_HIGH), 3);
592 PUSH_DATAh(push, q->bo->offset + q->offset);
593 PUSH_DATA (push, q->bo->offset + q->offset);
594 PUSH_DATA (push, cond);
595 BEGIN_NVC0(push, NVC0_2D(COND_ADDRESS_HIGH), 2);
596 PUSH_DATAh(push, q->bo->offset + q->offset);
597 PUSH_DATA (push, q->bo->offset + q->offset);
598 }
599
600 void
601 nvc0_query_pushbuf_submit(struct nouveau_pushbuf *push,
602 struct pipe_query *pq, unsigned result_offset)
603 {
604 struct nvc0_query *q = nvc0_query(pq);
605
606 #define NVC0_IB_ENTRY_1_NO_PREFETCH (1 << (31 - 8))
607
608 nouveau_pushbuf_space(push, 0, 0, 1);
609 nouveau_pushbuf_data(push, q->bo, q->offset + result_offset, 4 |
610 NVC0_IB_ENTRY_1_NO_PREFETCH);
611 }
612
613 void
614 nvc0_so_target_save_offset(struct pipe_context *pipe,
615 struct pipe_stream_output_target *ptarg,
616 unsigned index, boolean *serialize)
617 {
618 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
619
620 if (*serialize) {
621 *serialize = FALSE;
622 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
623 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
624
625 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
626 }
627
628 nvc0_query(targ->pq)->index = index;
629
630 nvc0_query_end(pipe, targ->pq);
631 }
632
633
634 /* === DRIVER STATISTICS === */
635
636 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
637
638 static const char *nvc0_drv_stat_names[] =
639 {
640 "drv-tex_obj_current_count",
641 "drv-tex_obj_current_bytes",
642 "drv-buf_obj_current_count",
643 "drv-buf_obj_current_bytes_vid",
644 "drv-buf_obj_current_bytes_sys",
645 "drv-tex_transfers_rd",
646 "drv-tex_transfers_wr",
647 "drv-tex_copy_count",
648 "drv-tex_blit_count",
649 "drv-tex_cache_flush_count",
650 "drv-buf_transfers_rd",
651 "drv-buf_transfers_wr",
652 "drv-buf_read_bytes_staging_vid",
653 "drv-buf_write_bytes_direct",
654 "drv-buf_write_bytes_staging_vid",
655 "drv-buf_write_bytes_staging_sys",
656 "drv-buf_copy_bytes",
657 "drv-buf_non_kernel_fence_sync_count",
658 "drv-any_non_kernel_fence_sync_count",
659 "drv-query_sync_count",
660 "drv-gpu_serialize_count",
661 "drv-draw_calls_array",
662 "drv-draw_calls_indexed",
663 "drv-draw_calls_fallback_count",
664 "drv-user_buffer_upload_bytes",
665 "drv-constbuf_upload_count",
666 "drv-constbuf_upload_bytes",
667 "drv-pushbuf_count",
668 "drv-resource_validate_count"
669 };
670
671 #endif /* NOUVEAU_ENABLE_DRIVER_STATISTICS */
672
673
674 /* === PERFORMANCE MONITORING COUNTERS for NVE4+ === */
675
676 /* Code to read out MP counters: They are accessible via mmio, too, but let's
677 * just avoid mapping registers in userspace. We'd have to know which MPs are
678 * enabled/present, too, and that information is not presently exposed.
679 * We could add a kernel interface for it, but reading the counters like this
680 * has the advantage of being async (if get_result isn't called immediately).
681 */
682 static const uint64_t nve4_read_mp_pm_counters_code[] =
683 {
684 /* sched 0x20 0x20 0x20 0x20 0x20 0x20 0x20
685 * mov b32 $r8 $tidx
686 * mov b32 $r12 $physid
687 * mov b32 $r0 $pm0
688 * mov b32 $r1 $pm1
689 * mov b32 $r2 $pm2
690 * mov b32 $r3 $pm3
691 * mov b32 $r4 $pm4
692 * sched 0x20 0x20 0x23 0x04 0x20 0x04 0x2b
693 * mov b32 $r5 $pm5
694 * mov b32 $r6 $pm6
695 * mov b32 $r7 $pm7
696 * set $p0 0x1 eq u32 $r8 0x0
697 * mov b32 $r10 c0[0x0]
698 * ext u32 $r8 $r12 0x414
699 * mov b32 $r11 c0[0x4]
700 * sched 0x04 0x2e 0x04 0x20 0x20 0x28 0x04
701 * ext u32 $r9 $r12 0x208
702 * (not $p0) exit
703 * set $p1 0x1 eq u32 $r9 0x0
704 * mul $r8 u32 $r8 u32 96
705 * mul $r12 u32 $r9 u32 16
706 * mul $r13 u32 $r9 u32 4
707 * add b32 $r9 $r8 $r13
708 * sched 0x28 0x04 0x2c 0x04 0x2c 0x04 0x2c
709 * add b32 $r8 $r8 $r12
710 * mov b32 $r12 $r10
711 * add b32 $r10 $c $r10 $r8
712 * mov b32 $r13 $r11
713 * add b32 $r11 $r11 0x0 $c
714 * add b32 $r12 $c $r12 $r9
715 * st b128 wt g[$r10d] $r0q
716 * sched 0x4 0x2c 0x20 0x04 0x2e 0x00 0x00
717 * mov b32 $r0 c0[0x8]
718 * add b32 $r13 $r13 0x0 $c
719 * $p1 st b128 wt g[$r12d+0x40] $r4q
720 * st b32 wt g[$r12d+0x50] $r0
721 * exit */
722 0x2202020202020207ULL,
723 0x2c00000084021c04ULL,
724 0x2c0000000c031c04ULL,
725 0x2c00000010001c04ULL,
726 0x2c00000014005c04ULL,
727 0x2c00000018009c04ULL,
728 0x2c0000001c00dc04ULL,
729 0x2c00000020011c04ULL,
730 0x22b0420042320207ULL,
731 0x2c00000024015c04ULL,
732 0x2c00000028019c04ULL,
733 0x2c0000002c01dc04ULL,
734 0x190e0000fc81dc03ULL,
735 0x2800400000029de4ULL,
736 0x7000c01050c21c03ULL,
737 0x280040001002dde4ULL,
738 0x204282020042e047ULL,
739 0x7000c00820c25c03ULL,
740 0x80000000000021e7ULL,
741 0x190e0000fc93dc03ULL,
742 0x1000000180821c02ULL,
743 0x1000000040931c02ULL,
744 0x1000000010935c02ULL,
745 0x4800000034825c03ULL,
746 0x22c042c042c04287ULL,
747 0x4800000030821c03ULL,
748 0x2800000028031de4ULL,
749 0x4801000020a29c03ULL,
750 0x280000002c035de4ULL,
751 0x0800000000b2dc42ULL,
752 0x4801000024c31c03ULL,
753 0x9400000000a01fc5ULL,
754 0x200002e04202c047ULL,
755 0x2800400020001de4ULL,
756 0x0800000000d35c42ULL,
757 0x9400000100c107c5ULL,
758 0x9400000140c01f85ULL,
759 0x8000000000001de7ULL
760 };
761
762 /* NOTE: intentionally using the same names as NV */
763 static const char *nve4_pm_query_names[] =
764 {
765 /* MP counters */
766 "prof_trigger_00",
767 "prof_trigger_01",
768 "prof_trigger_02",
769 "prof_trigger_03",
770 "prof_trigger_04",
771 "prof_trigger_05",
772 "prof_trigger_06",
773 "prof_trigger_07",
774 "warps_launched",
775 "threads_launched",
776 "sm_cta_launched",
777 "inst_issued1",
778 "inst_issued2",
779 "inst_executed",
780 "local_load",
781 "local_store",
782 "shared_load",
783 "shared_store",
784 "l1_local_load_hit",
785 "l1_local_load_miss",
786 "l1_local_store_hit",
787 "l1_local_store_miss",
788 "gld_request",
789 "gst_request",
790 "l1_global_load_hit",
791 "l1_global_load_miss",
792 "uncached_global_load_transaction",
793 "global_store_transaction",
794 "branch",
795 "divergent_branch",
796 "active_warps",
797 "active_cycles",
798 "inst_issued",
799 "atom_count",
800 "gred_count",
801 "shared_load_replay",
802 "shared_store_replay",
803 "local_load_transactions",
804 "local_store_transactions",
805 "l1_shared_load_transactions",
806 "l1_shared_store_transactions",
807 "global_ld_mem_divergence_replays",
808 "global_st_mem_divergence_replays",
809 /* metrics, i.e. functions of the MP counters */
810 "metric-ipc", /* inst_executed, clock */
811 "metric-ipac", /* inst_executed, active_cycles */
812 "metric-ipec", /* inst_executed, (bool)inst_executed */
813 "metric-achieved_occupancy", /* active_warps, active_cycles */
814 "metric-sm_efficiency", /* active_cycles, clock */
815 "metric-inst_replay_overhead" /* inst_issued, inst_executed */
816 };
817
818 /* For simplicity, we will allocate as many group slots as we allocate counter
819 * slots. This means that a single counter which wants to source from 2 groups
820 * will have to be declared as using 2 counter slots. This shouldn't really be
821 * a problem because such queries don't make much sense ... (unless someone is
822 * really creative).
823 */
824 struct nvc0_mp_counter_cfg
825 {
826 uint32_t func : 16; /* mask or 4-bit logic op (depending on mode) */
827 uint32_t mode : 4; /* LOGOP,B6,LOGOP_B6(_PULSE) */
828 uint32_t num_src : 3; /* number of sources (1 - 6, only for NVC0:NVE4) */
829 uint32_t sig_dom : 1; /* if 0, MP_PM_A (per warp-sched), if 1, MP_PM_B */
830 uint32_t sig_sel : 8; /* signal group */
831 uint64_t src_sel; /* signal selection for up to 6 sources (48 bit) */
832 };
833
834 #define NVC0_COUNTER_OPn_SUM 0
835 #define NVC0_COUNTER_OPn_OR 1
836 #define NVC0_COUNTER_OPn_AND 2
837 #define NVC0_COUNTER_OP2_REL_SUM_MM 3 /* (sum(ctr0) - sum(ctr1)) / sum(ctr0) */
838 #define NVC0_COUNTER_OP2_DIV_SUM_M0 4 /* sum(ctr0) / ctr1 of MP[0]) */
839 #define NVC0_COUNTER_OP2_AVG_DIV_MM 5 /* avg(ctr0 / ctr1) */
840 #define NVC0_COUNTER_OP2_AVG_DIV_M0 6 /* avg(ctr0) / ctr1 of MP[0]) */
841
842 struct nvc0_mp_pm_query_cfg
843 {
844 struct nvc0_mp_counter_cfg ctr[4];
845 uint8_t num_counters;
846 uint8_t op;
847 uint8_t norm[2]; /* normalization num,denom */
848 };
849
850 #define _Q1A(n, f, m, g, s, nu, dn) [NVE4_PM_QUERY_##n] = { { { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g, s }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { nu, dn } }
851 #define _Q1B(n, f, m, g, s, nu, dn) [NVE4_PM_QUERY_##n] = { { { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g, s }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { nu, dn } }
852 #define _M2A(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_PM_QUERY_METRIC_##n] = { { \
853 { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g0, s0 }, \
854 { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g1, s1 }, \
855 {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
856 #define _M2B(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_PM_QUERY_METRIC_##n] = { { \
857 { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g0, s0 }, \
858 { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g1, s1 }, \
859 {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
860 #define _M2AB(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_PM_QUERY_METRIC_##n] = { { \
861 { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g0, s0 }, \
862 { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g1, s1 }, \
863 {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
864
865 /* NOTES:
866 * active_warps: bit 0 alternates btw 0 and 1 for odd nr of warps
867 * inst_executed etc.: we only count a single warp scheduler
868 * metric-ipXc: we simply multiply by 4 to account for the 4 warp schedulers;
869 * this is inaccurate !
870 */
871 static const struct nvc0_mp_pm_query_cfg nve4_mp_pm_queries[] =
872 {
873 _Q1A(PROF_TRIGGER_0, 0x0001, B6, USER, 0x00000000, 1, 1),
874 _Q1A(PROF_TRIGGER_1, 0x0001, B6, USER, 0x00000004, 1, 1),
875 _Q1A(PROF_TRIGGER_2, 0x0001, B6, USER, 0x00000008, 1, 1),
876 _Q1A(PROF_TRIGGER_3, 0x0001, B6, USER, 0x0000000c, 1, 1),
877 _Q1A(PROF_TRIGGER_4, 0x0001, B6, USER, 0x00000010, 1, 1),
878 _Q1A(PROF_TRIGGER_5, 0x0001, B6, USER, 0x00000014, 1, 1),
879 _Q1A(PROF_TRIGGER_6, 0x0001, B6, USER, 0x00000018, 1, 1),
880 _Q1A(PROF_TRIGGER_7, 0x0001, B6, USER, 0x0000001c, 1, 1),
881 _Q1A(LAUNCHED_WARPS, 0x0001, B6, LAUNCH, 0x00000004, 1, 1),
882 _Q1A(LAUNCHED_THREADS, 0x003f, B6, LAUNCH, 0x398a4188, 1, 1),
883 _Q1B(LAUNCHED_CTA, 0x0001, B6, WARP, 0x0000001c, 1, 1),
884 _Q1A(INST_ISSUED1, 0x0001, B6, ISSUE, 0x00000004, 1, 1),
885 _Q1A(INST_ISSUED2, 0x0001, B6, ISSUE, 0x00000008, 1, 1),
886 _Q1A(INST_ISSUED, 0x0003, B6, ISSUE, 0x00000104, 1, 1),
887 _Q1A(INST_EXECUTED, 0x0003, B6, EXEC, 0x00000398, 1, 1),
888 _Q1A(LD_SHARED, 0x0001, B6, LDST, 0x00000000, 1, 1),
889 _Q1A(ST_SHARED, 0x0001, B6, LDST, 0x00000004, 1, 1),
890 _Q1A(LD_LOCAL, 0x0001, B6, LDST, 0x00000008, 1, 1),
891 _Q1A(ST_LOCAL, 0x0001, B6, LDST, 0x0000000c, 1, 1),
892 _Q1A(GLD_REQUEST, 0x0001, B6, LDST, 0x00000010, 1, 1),
893 _Q1A(GST_REQUEST, 0x0001, B6, LDST, 0x00000014, 1, 1),
894 _Q1B(L1_LOCAL_LOAD_HIT, 0x0001, B6, L1, 0x00000000, 1, 1),
895 _Q1B(L1_LOCAL_LOAD_MISS, 0x0001, B6, L1, 0x00000004, 1, 1),
896 _Q1B(L1_LOCAL_STORE_HIT, 0x0001, B6, L1, 0x00000008, 1, 1),
897 _Q1B(L1_LOCAL_STORE_MISS, 0x0001, B6, L1, 0x0000000c, 1, 1),
898 _Q1B(L1_GLOBAL_LOAD_HIT, 0x0001, B6, L1, 0x00000010, 1, 1),
899 _Q1B(L1_GLOBAL_LOAD_MISS, 0x0001, B6, L1, 0x00000014, 1, 1),
900 _Q1B(GLD_TRANSACTIONS_UNCACHED, 0x0001, B6, MEM, 0x00000000, 1, 1),
901 _Q1B(GST_TRANSACTIONS, 0x0001, B6, MEM, 0x00000004, 1, 1),
902 _Q1A(BRANCH, 0x0001, B6, BRANCH, 0x0000000c, 1, 1),
903 _Q1A(BRANCH_DIVERGENT, 0x0001, B6, BRANCH, 0x00000010, 1, 1),
904 _Q1B(ACTIVE_WARPS, 0x003f, B6, WARP, 0x31483104, 2, 1),
905 _Q1B(ACTIVE_CYCLES, 0x0001, B6, WARP, 0x00000000, 1, 1),
906 _Q1A(ATOM_COUNT, 0x0001, B6, BRANCH, 0x00000000, 1, 1),
907 _Q1A(GRED_COUNT, 0x0001, B6, BRANCH, 0x00000008, 1, 1),
908 _Q1B(LD_SHARED_REPLAY, 0x0001, B6, REPLAY, 0x00000008, 1, 1),
909 _Q1B(ST_SHARED_REPLAY, 0x0001, B6, REPLAY, 0x0000000c, 1, 1),
910 _Q1B(LD_LOCAL_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000000, 1, 1),
911 _Q1B(ST_LOCAL_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000004, 1, 1),
912 _Q1B(L1_LD_SHARED_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000008, 1, 1),
913 _Q1B(L1_ST_SHARED_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x0000000c, 1, 1),
914 _Q1B(GLD_MEM_DIV_REPLAY, 0x0001, B6, REPLAY, 0x00000010, 1, 1),
915 _Q1B(GST_MEM_DIV_REPLAY, 0x0001, B6, REPLAY, 0x00000014, 1, 1),
916 _M2AB(IPC, 0x3, B6, EXEC, 0x398, 0xffff, LOGOP, WARP, 0x0, DIV_SUM_M0, 10, 1),
917 _M2AB(IPAC, 0x3, B6, EXEC, 0x398, 0x1, B6, WARP, 0x0, AVG_DIV_MM, 10, 1),
918 _M2A(IPEC, 0x3, B6, EXEC, 0x398, 0xe, LOGOP, EXEC, 0x398, AVG_DIV_MM, 10, 1),
919 _M2A(INST_REPLAY_OHEAD, 0x3, B6, ISSUE, 0x104, 0x3, B6, EXEC, 0x398, REL_SUM_MM, 100, 1),
920 _M2B(MP_OCCUPANCY, 0x3f, B6, WARP, 0x31483104, 0x01, B6, WARP, 0x0, AVG_DIV_MM, 200, 64),
921 _M2B(MP_EFFICIENCY, 0x01, B6, WARP, 0x0, 0xffff, LOGOP, WARP, 0x0, AVG_DIV_M0, 100, 1),
922 };
923
924 #undef _Q1A
925 #undef _Q1B
926 #undef _M2A
927 #undef _M2B
928
929 /* === PERFORMANCE MONITORING COUNTERS for NVC0:NVE4 === */
930 static const uint64_t nvc0_read_mp_pm_counters_code[] =
931 {
932 /* mov b32 $r8 $tidx
933 * mov b32 $r9 $physid
934 * mov b32 $r0 $pm0
935 * mov b32 $r1 $pm1
936 * mov b32 $r2 $pm2
937 * mov b32 $r3 $pm3
938 * mov b32 $r4 $pm4
939 * mov b32 $r5 $pm5
940 * mov b32 $r6 $pm6
941 * mov b32 $r7 $pm7
942 * set $p0 0x1 eq u32 $r8 0x0
943 * mov b32 $r10 c0[0x0]
944 * mov b32 $r11 c0[0x4]
945 * ext u32 $r8 $r9 0x414
946 * (not $p0) exit
947 * mul $r8 u32 $r8 u32 36
948 * add b32 $r10 $c $r10 $r8
949 * add b32 $r11 $r11 0x0 $c
950 * mov b32 $r8 c0[0x8]
951 * st b128 wt g[$r10d+0x00] $r0q
952 * st b128 wt g[$r10d+0x10] $r4q
953 * st b32 wt g[$r10d+0x20] $r8
954 * exit */
955 0x2c00000084021c04ULL,
956 0x2c0000000c025c04ULL,
957 0x2c00000010001c04ULL,
958 0x2c00000014005c04ULL,
959 0x2c00000018009c04ULL,
960 0x2c0000001c00dc04ULL,
961 0x2c00000020011c04ULL,
962 0x2c00000024015c04ULL,
963 0x2c00000028019c04ULL,
964 0x2c0000002c01dc04ULL,
965 0x190e0000fc81dc03ULL,
966 0x2800400000029de4ULL,
967 0x280040001002dde4ULL,
968 0x7000c01050921c03ULL,
969 0x80000000000021e7ULL,
970 0x1000000090821c02ULL,
971 0x4801000020a29c03ULL,
972 0x0800000000b2dc42ULL,
973 0x2800400020021de4ULL,
974 0x9400000000a01fc5ULL,
975 0x9400000040a11fc5ULL,
976 0x9400000080a21f85ULL,
977 0x8000000000001de7ULL
978 };
979
980 static const char *nvc0_pm_query_names[] =
981 {
982 /* MP counters */
983 "inst_executed",
984 "branch",
985 "divergent_branch",
986 "active_warps",
987 "active_cycles",
988 "warps_launched",
989 "threads_launched",
990 "shared_load",
991 "shared_store",
992 "local_load",
993 "local_store",
994 "gred_count",
995 "atom_count",
996 "gld_request",
997 "gst_request",
998 "inst_issued1_0",
999 "inst_issued1_1",
1000 "inst_issued2_0",
1001 "inst_issued2_1",
1002 "thread_inst_executed_0",
1003 "thread_inst_executed_1",
1004 "thread_inst_executed_2",
1005 "thread_inst_executed_3",
1006 "prof_trigger_00",
1007 "prof_trigger_01",
1008 "prof_trigger_02",
1009 "prof_trigger_03",
1010 "prof_trigger_04",
1011 "prof_trigger_05",
1012 "prof_trigger_06",
1013 "prof_trigger_07",
1014 };
1015
1016 #define _Q(n, f, m, g, c, s0, s1, s2, s3, s4, s5) [NVC0_PM_QUERY_##n] = { { { f, NVC0_COMPUTE_MP_PM_OP_MODE_##m, c, 0, g, s0|(s1 << 8)|(s2 << 16)|(s3 << 24)|(s4##ULL << 32)|(s5##ULL << 40) }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { 1, 1 } }
1017
1018 static const struct nvc0_mp_pm_query_cfg nvc0_mp_pm_queries[] =
1019 {
1020 _Q(INST_EXECUTED, 0xaaaa, LOGOP, 0x2d, 3, 0x00, 0x11, 0x22, 0x00, 0x00, 0x00),
1021 _Q(BRANCH, 0xaaaa, LOGOP, 0x1a, 2, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00),
1022 _Q(BRANCH_DIVERGENT, 0xaaaa, LOGOP, 0x19, 2, 0x20, 0x31, 0x00, 0x00, 0x00, 0x00),
1023 _Q(ACTIVE_WARPS, 0xaaaa, LOGOP, 0x24, 6, 0x10, 0x21, 0x32, 0x43, 0x54, 0x65),
1024 _Q(ACTIVE_CYCLES, 0xaaaa, LOGOP, 0x11, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
1025 _Q(LAUNCHED_WARPS, 0xaaaa, LOGOP, 0x26, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
1026 _Q(LAUNCHED_THREADS, 0xaaaa, LOGOP, 0x26, 6, 0x10, 0x21, 0x32, 0x43, 0x54, 0x65),
1027 _Q(LD_SHARED, 0xaaaa, LOGOP, 0x64, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
1028 _Q(ST_SHARED, 0xaaaa, LOGOP, 0x64, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
1029 _Q(LD_LOCAL, 0xaaaa, LOGOP, 0x64, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
1030 _Q(ST_LOCAL, 0xaaaa, LOGOP, 0x64, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
1031 _Q(GRED_COUNT, 0xaaaa, LOGOP, 0x63, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
1032 _Q(ATOM_COUNT, 0xaaaa, LOGOP, 0x63, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
1033 _Q(GLD_REQUEST, 0xaaaa, LOGOP, 0x64, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
1034 _Q(GST_REQUEST, 0xaaaa, LOGOP, 0x64, 1, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00),
1035 _Q(INST_ISSUED1_0, 0xaaaa, LOGOP, 0x7e, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
1036 _Q(INST_ISSUED1_1, 0xaaaa, LOGOP, 0x7e, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
1037 _Q(INST_ISSUED2_0, 0xaaaa, LOGOP, 0x7e, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
1038 _Q(INST_ISSUED2_1, 0xaaaa, LOGOP, 0x7e, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
1039 _Q(TH_INST_EXECUTED_0, 0xaaaa, LOGOP, 0xa3, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
1040 _Q(TH_INST_EXECUTED_1, 0xaaaa, LOGOP, 0xa5, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
1041 _Q(TH_INST_EXECUTED_2, 0xaaaa, LOGOP, 0xa4, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
1042 _Q(TH_INST_EXECUTED_3, 0xaaaa, LOGOP, 0xa6, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
1043 _Q(PROF_TRIGGER_0, 0xaaaa, LOGOP, 0x01, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
1044 _Q(PROF_TRIGGER_1, 0xaaaa, LOGOP, 0x01, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
1045 _Q(PROF_TRIGGER_2, 0xaaaa, LOGOP, 0x01, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
1046 _Q(PROF_TRIGGER_3, 0xaaaa, LOGOP, 0x01, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
1047 _Q(PROF_TRIGGER_4, 0xaaaa, LOGOP, 0x01, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
1048 _Q(PROF_TRIGGER_5, 0xaaaa, LOGOP, 0x01, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
1049 _Q(PROF_TRIGGER_6, 0xaaaa, LOGOP, 0x01, 1, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00),
1050 _Q(PROF_TRIGGER_7, 0xaaaa, LOGOP, 0x01, 1, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00),
1051 };
1052
1053 #undef _Q
1054
1055 static const struct nvc0_mp_pm_query_cfg *
1056 nvc0_mp_pm_query_get_cfg(struct nvc0_context *nvc0, struct nvc0_query *q)
1057 {
1058 struct nvc0_screen *screen = nvc0->screen;
1059
1060 if (screen->base.class_3d >= NVE4_3D_CLASS)
1061 return &nve4_mp_pm_queries[q->type - PIPE_QUERY_DRIVER_SPECIFIC];
1062 return &nvc0_mp_pm_queries[q->type - NVC0_PM_QUERY(0)];
1063 }
1064
1065 void
1066 nvc0_mp_pm_query_begin(struct nvc0_context *nvc0, struct nvc0_query *q)
1067 {
1068 struct nvc0_screen *screen = nvc0->screen;
1069 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1070 const boolean is_nve4 = screen->base.class_3d >= NVE4_3D_CLASS;
1071 const struct nvc0_mp_pm_query_cfg *cfg;
1072 unsigned i, c;
1073 unsigned num_ab[2] = { 0, 0 };
1074
1075 cfg = nvc0_mp_pm_query_get_cfg(nvc0, q);
1076
1077 /* check if we have enough free counter slots */
1078 for (i = 0; i < cfg->num_counters; ++i)
1079 num_ab[cfg->ctr[i].sig_dom]++;
1080
1081 if (screen->pm.num_mp_pm_active[0] + num_ab[0] > 4 ||
1082 screen->pm.num_mp_pm_active[1] + num_ab[1] > 4) {
1083 NOUVEAU_ERR("Not enough free MP counter slots !\n");
1084 return;
1085 }
1086
1087 assert(cfg->num_counters <= 4);
1088 PUSH_SPACE(push, 4 * 8 * (is_nve4 ? 1 : 6) + 6);
1089
1090 if (!screen->pm.mp_counters_enabled) {
1091 screen->pm.mp_counters_enabled = TRUE;
1092 BEGIN_NVC0(push, SUBC_SW(0x06ac), 1);
1093 PUSH_DATA (push, 0x1fcb);
1094 }
1095
1096 /* set sequence field to 0 (used to check if result is available) */
1097 for (i = 0; i < screen->mp_count; ++i)
1098 q->data[i * 10 + 10] = 0;
1099
1100 for (i = 0; i < cfg->num_counters; ++i) {
1101 const unsigned d = cfg->ctr[i].sig_dom;
1102
1103 if (!screen->pm.num_mp_pm_active[d]) {
1104 uint32_t m = (1 << 22) | (1 << (7 + (8 * !d)));
1105 if (screen->pm.num_mp_pm_active[!d])
1106 m |= 1 << (7 + (8 * d));
1107 BEGIN_NVC0(push, SUBC_SW(0x0600), 1);
1108 PUSH_DATA (push, m);
1109 }
1110 screen->pm.num_mp_pm_active[d]++;
1111
1112 for (c = d * 4; c < (d * 4 + 4); ++c) {
1113 if (!screen->pm.mp_counter[c]) {
1114 q->ctr[i] = c;
1115 screen->pm.mp_counter[c] = (struct pipe_query *)q;
1116 break;
1117 }
1118 }
1119 assert(c <= (d * 4 + 3)); /* must succeed, already checked for space */
1120
1121 /* configure and reset the counter(s) */
1122 if (is_nve4) {
1123 if (d == 0)
1124 BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_A_SIGSEL(c & 3)), 1);
1125 else
1126 BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_B_SIGSEL(c & 3)), 1);
1127 PUSH_DATA (push, cfg->ctr[i].sig_sel);
1128 BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_SRCSEL(c)), 1);
1129 PUSH_DATA (push, cfg->ctr[i].src_sel + 0x2108421 * (c & 3));
1130 BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(c)), 1);
1131 PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
1132 BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_SET(c)), 1);
1133 PUSH_DATA (push, 0);
1134 } else {
1135 unsigned s;
1136
1137 for (s = 0; s < cfg->ctr[i].num_src; s++) {
1138 BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SIGSEL(s)), 1);
1139 PUSH_DATA (push, cfg->ctr[i].sig_sel);
1140 BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SRCSEL(s)), 1);
1141 PUSH_DATA (push, (cfg->ctr[i].src_sel >> (s * 8)) & 0xff);
1142 BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_OP(s)), 1);
1143 PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
1144 BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SET(s)), 1);
1145 PUSH_DATA (push, 0);
1146 }
1147 }
1148 }
1149 }
1150
1151 static void
1152 nvc0_mp_pm_query_end(struct nvc0_context *nvc0, struct nvc0_query *q)
1153 {
1154 struct nvc0_screen *screen = nvc0->screen;
1155 struct pipe_context *pipe = &nvc0->base.pipe;
1156 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1157 const boolean is_nve4 = screen->base.class_3d >= NVE4_3D_CLASS;
1158 uint32_t mask;
1159 uint32_t input[3];
1160 const uint block[3] = { 32, is_nve4 ? 4 : 1, 1 };
1161 const uint grid[3] = { screen->mp_count, 1, 1 };
1162 unsigned c;
1163 const struct nvc0_mp_pm_query_cfg *cfg;
1164
1165 cfg = nvc0_mp_pm_query_get_cfg(nvc0, q);
1166
1167 if (unlikely(!screen->pm.prog)) {
1168 struct nvc0_program *prog = CALLOC_STRUCT(nvc0_program);
1169 prog->type = PIPE_SHADER_COMPUTE;
1170 prog->translated = TRUE;
1171 prog->num_gprs = 14;
1172 prog->parm_size = 12;
1173 if (is_nve4) {
1174 prog->code = (uint32_t *)nve4_read_mp_pm_counters_code;
1175 prog->code_size = sizeof(nve4_read_mp_pm_counters_code);
1176 } else {
1177 prog->code = (uint32_t *)nvc0_read_mp_pm_counters_code;
1178 prog->code_size = sizeof(nvc0_read_mp_pm_counters_code);
1179 }
1180 screen->pm.prog = prog;
1181 }
1182
1183 /* disable all counting */
1184 PUSH_SPACE(push, 8);
1185 for (c = 0; c < 8; ++c)
1186 if (screen->pm.mp_counter[c]) {
1187 if (is_nve4) {
1188 IMMED_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(c)), 0);
1189 } else {
1190 IMMED_NVC0(push, NVC0_COMPUTE(MP_PM_OP(c)), 0);
1191 }
1192 }
1193 /* release counters for this query */
1194 for (c = 0; c < 8; ++c) {
1195 if (nvc0_query(screen->pm.mp_counter[c]) == q) {
1196 screen->pm.num_mp_pm_active[c / 4]--;
1197 screen->pm.mp_counter[c] = NULL;
1198 }
1199 }
1200
1201 BCTX_REFN_bo(nvc0->bufctx_cp, CP_QUERY, NOUVEAU_BO_GART | NOUVEAU_BO_WR,
1202 q->bo);
1203
1204 PUSH_SPACE(push, 1);
1205 IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0);
1206
1207 pipe->bind_compute_state(pipe, screen->pm.prog);
1208 input[0] = (q->bo->offset + q->base);
1209 input[1] = (q->bo->offset + q->base) >> 32;
1210 input[2] = q->sequence;
1211 pipe->launch_grid(pipe, block, grid, 0, input);
1212
1213 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_QUERY);
1214
1215 /* re-activate other counters */
1216 PUSH_SPACE(push, 16);
1217 mask = 0;
1218 for (c = 0; c < 8; ++c) {
1219 unsigned i;
1220 q = nvc0_query(screen->pm.mp_counter[c]);
1221 if (!q)
1222 continue;
1223 cfg = nvc0_mp_pm_query_get_cfg(nvc0, q);
1224 for (i = 0; i < cfg->num_counters; ++i) {
1225 if (mask & (1 << q->ctr[i]))
1226 break;
1227 mask |= 1 << q->ctr[i];
1228 if (is_nve4) {
1229 BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(q->ctr[i])), 1);
1230 } else {
1231 BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_OP(q->ctr[i])), 1);
1232 }
1233 PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
1234 }
1235 }
1236 }
1237
1238 static INLINE boolean
1239 nvc0_mp_pm_query_read_data(uint32_t count[32][4],
1240 struct nvc0_context *nvc0, boolean wait,
1241 struct nvc0_query *q,
1242 const struct nvc0_mp_pm_query_cfg *cfg,
1243 unsigned mp_count)
1244 {
1245 unsigned p, c;
1246
1247 for (p = 0; p < mp_count; ++p) {
1248 const unsigned b = (0x24 / 4) * p;
1249
1250 for (c = 0; c < cfg->num_counters; ++c) {
1251 if (q->data[b + 8] != q->sequence) {
1252 if (!wait)
1253 return FALSE;
1254 if (nouveau_bo_wait(q->bo, NOUVEAU_BO_RD, nvc0->base.client))
1255 return FALSE;
1256 }
1257 count[p][c] = q->data[b + q->ctr[c]];
1258 }
1259 }
1260 return TRUE;
1261 }
1262
1263 static INLINE boolean
1264 nve4_mp_pm_query_read_data(uint32_t count[32][4],
1265 struct nvc0_context *nvc0, boolean wait,
1266 struct nvc0_query *q,
1267 const struct nvc0_mp_pm_query_cfg *cfg,
1268 unsigned mp_count)
1269 {
1270 unsigned p, c, d;
1271
1272 for (p = 0; p < mp_count; ++p) {
1273 const unsigned b = (0x60 / 4) * p;
1274
1275 for (c = 0; c < cfg->num_counters; ++c) {
1276 count[p][c] = 0;
1277 for (d = 0; d < ((q->ctr[c] & ~3) ? 1 : 4); ++d) {
1278 if (q->data[b + 20 + d] != q->sequence) {
1279 if (!wait)
1280 return FALSE;
1281 if (nouveau_bo_wait(q->bo, NOUVEAU_BO_RD, nvc0->base.client))
1282 return FALSE;
1283 }
1284 if (q->ctr[c] & ~0x3)
1285 count[p][c] = q->data[b + 16 + (q->ctr[c] & 3)];
1286 else
1287 count[p][c] += q->data[b + d * 4 + q->ctr[c]];
1288 }
1289 }
1290 }
1291 return TRUE;
1292 }
1293
1294 /* Metric calculations:
1295 * sum(x) ... sum of x over all MPs
1296 * avg(x) ... average of x over all MPs
1297 *
1298 * IPC : sum(inst_executed) / clock
1299 * INST_REPLAY_OHEAD: (sum(inst_issued) - sum(inst_executed)) / sum(inst_issued)
1300 * MP_OCCUPANCY : avg((active_warps / 64) / active_cycles)
1301 * MP_EFFICIENCY : avg(active_cycles / clock)
1302 *
1303 * NOTE: Interpretation of IPC requires knowledge of MP count.
1304 */
1305 static boolean
1306 nvc0_mp_pm_query_result(struct nvc0_context *nvc0, struct nvc0_query *q,
1307 void *result, boolean wait)
1308 {
1309 uint32_t count[32][4];
1310 uint64_t value = 0;
1311 unsigned mp_count = MIN2(nvc0->screen->mp_count_compute, 32);
1312 unsigned p, c;
1313 const struct nvc0_mp_pm_query_cfg *cfg;
1314 boolean ret;
1315
1316 cfg = nvc0_mp_pm_query_get_cfg(nvc0, q);
1317
1318 if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
1319 ret = nve4_mp_pm_query_read_data(count, nvc0, wait, q, cfg, mp_count);
1320 else
1321 ret = nvc0_mp_pm_query_read_data(count, nvc0, wait, q, cfg, mp_count);
1322 if (!ret)
1323 return FALSE;
1324
1325 if (cfg->op == NVC0_COUNTER_OPn_SUM) {
1326 for (c = 0; c < cfg->num_counters; ++c)
1327 for (p = 0; p < mp_count; ++p)
1328 value += count[p][c];
1329 value = (value * cfg->norm[0]) / cfg->norm[1];
1330 } else
1331 if (cfg->op == NVC0_COUNTER_OPn_OR) {
1332 uint32_t v = 0;
1333 for (c = 0; c < cfg->num_counters; ++c)
1334 for (p = 0; p < mp_count; ++p)
1335 v |= count[p][c];
1336 value = (v * cfg->norm[0]) / cfg->norm[1];
1337 } else
1338 if (cfg->op == NVC0_COUNTER_OPn_AND) {
1339 uint32_t v = ~0;
1340 for (c = 0; c < cfg->num_counters; ++c)
1341 for (p = 0; p < mp_count; ++p)
1342 v &= count[p][c];
1343 value = (v * cfg->norm[0]) / cfg->norm[1];
1344 } else
1345 if (cfg->op == NVC0_COUNTER_OP2_REL_SUM_MM) {
1346 uint64_t v[2] = { 0, 0 };
1347 for (p = 0; p < mp_count; ++p) {
1348 v[0] += count[p][0];
1349 v[1] += count[p][1];
1350 }
1351 if (v[0])
1352 value = ((v[0] - v[1]) * cfg->norm[0]) / (v[0] * cfg->norm[1]);
1353 } else
1354 if (cfg->op == NVC0_COUNTER_OP2_DIV_SUM_M0) {
1355 for (p = 0; p < mp_count; ++p)
1356 value += count[p][0];
1357 if (count[0][1])
1358 value = (value * cfg->norm[0]) / (count[0][1] * cfg->norm[1]);
1359 else
1360 value = 0;
1361 } else
1362 if (cfg->op == NVC0_COUNTER_OP2_AVG_DIV_MM) {
1363 unsigned mp_used = 0;
1364 for (p = 0; p < mp_count; ++p, mp_used += !!count[p][0])
1365 if (count[p][1])
1366 value += (count[p][0] * cfg->norm[0]) / count[p][1];
1367 if (mp_used)
1368 value /= mp_used * cfg->norm[1];
1369 } else
1370 if (cfg->op == NVC0_COUNTER_OP2_AVG_DIV_M0) {
1371 unsigned mp_used = 0;
1372 for (p = 0; p < mp_count; ++p, mp_used += !!count[p][0])
1373 value += count[p][0];
1374 if (count[0][1] && mp_used) {
1375 value *= cfg->norm[0];
1376 value /= count[0][1] * mp_used * cfg->norm[1];
1377 } else {
1378 value = 0;
1379 }
1380 }
1381
1382 *(uint64_t *)result = value;
1383 return TRUE;
1384 }
1385
1386 int
1387 nvc0_screen_get_driver_query_info(struct pipe_screen *pscreen,
1388 unsigned id,
1389 struct pipe_driver_query_info *info)
1390 {
1391 struct nvc0_screen *screen = nvc0_screen(pscreen);
1392 int count = 0;
1393
1394 count += NVC0_QUERY_DRV_STAT_COUNT;
1395
1396 if (screen->base.device->drm_version >= 0x01000101) {
1397 if (screen->base.class_3d >= NVE4_3D_CLASS) {
1398 count += NVE4_PM_QUERY_COUNT;
1399 } else
1400 if (screen->compute) {
1401 count += NVC0_PM_QUERY_COUNT; /* NVC0_COMPUTE is not always enabled */
1402 }
1403 }
1404
1405 if (!info)
1406 return count;
1407
1408 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
1409 if (id < NVC0_QUERY_DRV_STAT_COUNT) {
1410 info->name = nvc0_drv_stat_names[id];
1411 info->query_type = NVC0_QUERY_DRV_STAT(id);
1412 info->max_value = ~0ULL;
1413 info->uses_byte_units = !!strstr(info->name, "bytes");
1414 return 1;
1415 } else
1416 #endif
1417 if (id < count) {
1418 if (screen->base.class_3d >= NVE4_3D_CLASS) {
1419 info->name = nve4_pm_query_names[id - NVC0_QUERY_DRV_STAT_COUNT];
1420 info->query_type = NVE4_PM_QUERY(id - NVC0_QUERY_DRV_STAT_COUNT);
1421 info->max_value = (id < NVE4_PM_QUERY_METRIC_MP_OCCUPANCY) ?
1422 ~0ULL : 100;
1423 info->uses_byte_units = FALSE;
1424 return 1;
1425 } else
1426 if (screen->compute) {
1427 info->name = nvc0_pm_query_names[id - NVC0_QUERY_DRV_STAT_COUNT];
1428 info->query_type = NVC0_PM_QUERY(id - NVC0_QUERY_DRV_STAT_COUNT);
1429 info->max_value = ~0ULL;
1430 info->uses_byte_units = FALSE;
1431 return 1;
1432 }
1433 }
1434 /* user asked for info about non-existing query */
1435 info->name = "this_is_not_the_query_you_are_looking_for";
1436 info->query_type = 0xdeadd01d;
1437 info->max_value = 0;
1438 info->uses_byte_units = FALSE;
1439 return 0;
1440 }
1441
1442 void
1443 nvc0_init_query_functions(struct nvc0_context *nvc0)
1444 {
1445 struct pipe_context *pipe = &nvc0->base.pipe;
1446
1447 pipe->create_query = nvc0_query_create;
1448 pipe->destroy_query = nvc0_query_destroy;
1449 pipe->begin_query = nvc0_query_begin;
1450 pipe->end_query = nvc0_query_end;
1451 pipe->get_query_result = nvc0_query_result;
1452 pipe->render_condition = nvc0_render_condition;
1453 }