2 * Copyright 2011 Nouveau Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christoph Bumiller
25 #define NVC0_PUSH_EXPLICIT_SPACE_CHECKING
27 #include "nvc0/nvc0_context.h"
28 #include "nv_object.xml.h"
29 #include "nvc0/nve4_compute.xml.h"
30 #include "nvc0/nvc0_compute.xml.h"
32 #define NVC0_QUERY_STATE_READY 0
33 #define NVC0_QUERY_STATE_ACTIVE 1
34 #define NVC0_QUERY_STATE_ENDED 2
35 #define NVC0_QUERY_STATE_FLUSHED 3
43 struct nouveau_bo
*bo
;
45 uint32_t offset
; /* base + i * rotate */
49 int nesting
; /* only used for occlusion queries */
51 struct nouveau_mm_allocation
*mm
;
54 struct nouveau_fence
*fence
;
57 #define NVC0_QUERY_ALLOC_SPACE 256
59 static void nvc0_mp_pm_query_begin(struct nvc0_context
*, struct nvc0_query
*);
60 static void nvc0_mp_pm_query_end(struct nvc0_context
*, struct nvc0_query
*);
61 static boolean
nvc0_mp_pm_query_result(struct nvc0_context
*,
62 struct nvc0_query
*, void *, boolean
);
64 static INLINE
struct nvc0_query
*
65 nvc0_query(struct pipe_query
*pipe
)
67 return (struct nvc0_query
*)pipe
;
71 nvc0_query_allocate(struct nvc0_context
*nvc0
, struct nvc0_query
*q
, int size
)
73 struct nvc0_screen
*screen
= nvc0
->screen
;
77 nouveau_bo_ref(NULL
, &q
->bo
);
79 if (q
->state
== NVC0_QUERY_STATE_READY
)
80 nouveau_mm_free(q
->u
.mm
);
82 nouveau_fence_work(screen
->base
.fence
.current
,
83 nouveau_mm_free_work
, q
->u
.mm
);
87 q
->u
.mm
= nouveau_mm_allocate(screen
->base
.mm_GART
, size
, &q
->bo
, &q
->base
);
92 ret
= nouveau_bo_map(q
->bo
, 0, screen
->base
.client
);
94 nvc0_query_allocate(nvc0
, q
, 0);
97 q
->data
= (uint32_t *)((uint8_t *)q
->bo
->map
+ q
->base
);
103 nvc0_query_destroy(struct pipe_context
*pipe
, struct pipe_query
*pq
)
105 nvc0_query_allocate(nvc0_context(pipe
), nvc0_query(pq
), 0);
106 nouveau_fence_ref(NULL
, &nvc0_query(pq
)->fence
);
107 FREE(nvc0_query(pq
));
110 static struct pipe_query
*
111 nvc0_query_create(struct pipe_context
*pipe
, unsigned type
, unsigned index
)
113 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
114 struct nvc0_query
*q
;
115 unsigned space
= NVC0_QUERY_ALLOC_SPACE
;
117 q
= CALLOC_STRUCT(nvc0_query
);
122 case PIPE_QUERY_OCCLUSION_COUNTER
:
123 case PIPE_QUERY_OCCLUSION_PREDICATE
:
125 space
= NVC0_QUERY_ALLOC_SPACE
;
127 case PIPE_QUERY_PIPELINE_STATISTICS
:
131 case PIPE_QUERY_SO_STATISTICS
:
132 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
136 case PIPE_QUERY_PRIMITIVES_GENERATED
:
137 case PIPE_QUERY_PRIMITIVES_EMITTED
:
142 case PIPE_QUERY_TIME_ELAPSED
:
143 case PIPE_QUERY_TIMESTAMP
:
144 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
145 case PIPE_QUERY_GPU_FINISHED
:
148 case NVC0_QUERY_TFB_BUFFER_OFFSET
:
152 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
153 if (type
>= NVC0_QUERY_DRV_STAT(0) && type
<= NVC0_QUERY_DRV_STAT_LAST
) {
156 q
->index
= type
- NVC0_QUERY_DRV_STAT(0);
160 if (nvc0
->screen
->base
.device
->drm_version
>= 0x01000101) {
161 if (type
>= NVE4_PM_QUERY(0) && type
<= NVE4_PM_QUERY_LAST
) {
183 * [50] = WS0.sequence
184 * [54] = WS1.sequence
185 * [58] = WS2.sequence
186 * [5c] = WS3.sequence
188 space
= (4 * 4 + 4 + 4) * nvc0
->screen
->mp_count
* sizeof(uint32_t);
191 if (type
>= NVC0_PM_QUERY(0) && type
<= NVC0_PM_QUERY_LAST
) {
203 space
= (8 + 1) * nvc0
->screen
->mp_count
* sizeof(uint32_t);
207 debug_printf("invalid query type: %u\n", type
);
211 if (!nvc0_query_allocate(nvc0
, q
, space
)) {
219 /* we advance before query_begin ! */
220 q
->offset
-= q
->rotate
;
221 q
->data
-= q
->rotate
/ sizeof(*q
->data
);
224 q
->data
[0] = 0; /* initialize sequence */
226 return (struct pipe_query
*)q
;
230 nvc0_query_get(struct nouveau_pushbuf
*push
, struct nvc0_query
*q
,
231 unsigned offset
, uint32_t get
)
236 PUSH_REFN (push
, q
->bo
, NOUVEAU_BO_GART
| NOUVEAU_BO_WR
);
237 BEGIN_NVC0(push
, NVC0_3D(QUERY_ADDRESS_HIGH
), 4);
238 PUSH_DATAh(push
, q
->bo
->offset
+ offset
);
239 PUSH_DATA (push
, q
->bo
->offset
+ offset
);
240 PUSH_DATA (push
, q
->sequence
);
241 PUSH_DATA (push
, get
);
245 nvc0_query_rotate(struct nvc0_context
*nvc0
, struct nvc0_query
*q
)
247 q
->offset
+= q
->rotate
;
248 q
->data
+= q
->rotate
/ sizeof(*q
->data
);
249 if (q
->offset
- q
->base
== NVC0_QUERY_ALLOC_SPACE
)
250 nvc0_query_allocate(nvc0
, q
, NVC0_QUERY_ALLOC_SPACE
);
254 nvc0_query_begin(struct pipe_context
*pipe
, struct pipe_query
*pq
)
256 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
257 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
258 struct nvc0_query
*q
= nvc0_query(pq
);
260 /* For occlusion queries we have to change the storage, because a previous
261 * query might set the initial render conition to FALSE even *after* we re-
262 * initialized it to TRUE.
265 nvc0_query_rotate(nvc0
, q
);
267 /* XXX: can we do this with the GPU, and sync with respect to a previous
270 q
->data
[0] = q
->sequence
; /* initialize sequence */
271 q
->data
[1] = 1; /* initial render condition = TRUE */
272 q
->data
[4] = q
->sequence
+ 1; /* for comparison COND_MODE */
278 case PIPE_QUERY_OCCLUSION_COUNTER
:
279 case PIPE_QUERY_OCCLUSION_PREDICATE
:
280 q
->nesting
= nvc0
->screen
->num_occlusion_queries_active
++;
282 nvc0_query_get(push
, q
, 0x10, 0x0100f002);
285 BEGIN_NVC0(push
, NVC0_3D(COUNTER_RESET
), 1);
286 PUSH_DATA (push
, NVC0_3D_COUNTER_RESET_SAMPLECNT
);
287 IMMED_NVC0(push
, NVC0_3D(SAMPLECNT_ENABLE
), 1);
290 case PIPE_QUERY_PRIMITIVES_GENERATED
:
291 nvc0_query_get(push
, q
, 0x10, 0x09005002 | (q
->index
<< 5));
293 case PIPE_QUERY_PRIMITIVES_EMITTED
:
294 nvc0_query_get(push
, q
, 0x10, 0x05805002 | (q
->index
<< 5));
296 case PIPE_QUERY_SO_STATISTICS
:
297 nvc0_query_get(push
, q
, 0x20, 0x05805002 | (q
->index
<< 5));
298 nvc0_query_get(push
, q
, 0x30, 0x06805002 | (q
->index
<< 5));
300 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
301 nvc0_query_get(push
, q
, 0x10, 0x03005002 | (q
->index
<< 5));
303 case PIPE_QUERY_TIME_ELAPSED
:
304 nvc0_query_get(push
, q
, 0x10, 0x00005002);
306 case PIPE_QUERY_PIPELINE_STATISTICS
:
307 nvc0_query_get(push
, q
, 0xc0 + 0x00, 0x00801002); /* VFETCH, VERTICES */
308 nvc0_query_get(push
, q
, 0xc0 + 0x10, 0x01801002); /* VFETCH, PRIMS */
309 nvc0_query_get(push
, q
, 0xc0 + 0x20, 0x02802002); /* VP, LAUNCHES */
310 nvc0_query_get(push
, q
, 0xc0 + 0x30, 0x03806002); /* GP, LAUNCHES */
311 nvc0_query_get(push
, q
, 0xc0 + 0x40, 0x04806002); /* GP, PRIMS_OUT */
312 nvc0_query_get(push
, q
, 0xc0 + 0x50, 0x07804002); /* RAST, PRIMS_IN */
313 nvc0_query_get(push
, q
, 0xc0 + 0x60, 0x08804002); /* RAST, PRIMS_OUT */
314 nvc0_query_get(push
, q
, 0xc0 + 0x70, 0x0980a002); /* ROP, PIXELS */
315 nvc0_query_get(push
, q
, 0xc0 + 0x80, 0x0d808002); /* TCP, LAUNCHES */
316 nvc0_query_get(push
, q
, 0xc0 + 0x90, 0x0e809002); /* TEP, LAUNCHES */
319 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
320 if (q
->type
>= NVC0_QUERY_DRV_STAT(0) &&
321 q
->type
<= NVC0_QUERY_DRV_STAT_LAST
) {
323 q
->u
.value
= nvc0
->screen
->base
.stats
.v
[q
->index
];
328 if ((q
->type
>= NVE4_PM_QUERY(0) && q
->type
<= NVE4_PM_QUERY_LAST
) ||
329 (q
->type
>= NVC0_PM_QUERY(0) && q
->type
<= NVC0_PM_QUERY_LAST
)) {
330 nvc0_mp_pm_query_begin(nvc0
, q
);
334 q
->state
= NVC0_QUERY_STATE_ACTIVE
;
338 nvc0_query_end(struct pipe_context
*pipe
, struct pipe_query
*pq
)
340 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
341 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
342 struct nvc0_query
*q
= nvc0_query(pq
);
344 if (q
->state
!= NVC0_QUERY_STATE_ACTIVE
) {
345 /* some queries don't require 'begin' to be called (e.g. GPU_FINISHED) */
347 nvc0_query_rotate(nvc0
, q
);
350 q
->state
= NVC0_QUERY_STATE_ENDED
;
353 case PIPE_QUERY_OCCLUSION_COUNTER
:
354 case PIPE_QUERY_OCCLUSION_PREDICATE
:
355 nvc0_query_get(push
, q
, 0, 0x0100f002);
356 if (--nvc0
->screen
->num_occlusion_queries_active
== 0) {
358 IMMED_NVC0(push
, NVC0_3D(SAMPLECNT_ENABLE
), 0);
361 case PIPE_QUERY_PRIMITIVES_GENERATED
:
362 nvc0_query_get(push
, q
, 0, 0x09005002 | (q
->index
<< 5));
364 case PIPE_QUERY_PRIMITIVES_EMITTED
:
365 nvc0_query_get(push
, q
, 0, 0x05805002 | (q
->index
<< 5));
367 case PIPE_QUERY_SO_STATISTICS
:
368 nvc0_query_get(push
, q
, 0x00, 0x05805002 | (q
->index
<< 5));
369 nvc0_query_get(push
, q
, 0x10, 0x06805002 | (q
->index
<< 5));
371 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
372 /* TODO: How do we sum over all streams for render condition ? */
373 /* PRIMS_DROPPED doesn't write sequence, use a ZERO query to sync on */
374 nvc0_query_get(push
, q
, 0x00, 0x03005002 | (q
->index
<< 5));
375 nvc0_query_get(push
, q
, 0x20, 0x00005002);
377 case PIPE_QUERY_TIMESTAMP
:
378 case PIPE_QUERY_TIME_ELAPSED
:
379 nvc0_query_get(push
, q
, 0, 0x00005002);
381 case PIPE_QUERY_GPU_FINISHED
:
382 nvc0_query_get(push
, q
, 0, 0x1000f010);
384 case PIPE_QUERY_PIPELINE_STATISTICS
:
385 nvc0_query_get(push
, q
, 0x00, 0x00801002); /* VFETCH, VERTICES */
386 nvc0_query_get(push
, q
, 0x10, 0x01801002); /* VFETCH, PRIMS */
387 nvc0_query_get(push
, q
, 0x20, 0x02802002); /* VP, LAUNCHES */
388 nvc0_query_get(push
, q
, 0x30, 0x03806002); /* GP, LAUNCHES */
389 nvc0_query_get(push
, q
, 0x40, 0x04806002); /* GP, PRIMS_OUT */
390 nvc0_query_get(push
, q
, 0x50, 0x07804002); /* RAST, PRIMS_IN */
391 nvc0_query_get(push
, q
, 0x60, 0x08804002); /* RAST, PRIMS_OUT */
392 nvc0_query_get(push
, q
, 0x70, 0x0980a002); /* ROP, PIXELS */
393 nvc0_query_get(push
, q
, 0x80, 0x0d808002); /* TCP, LAUNCHES */
394 nvc0_query_get(push
, q
, 0x90, 0x0e809002); /* TEP, LAUNCHES */
396 case NVC0_QUERY_TFB_BUFFER_OFFSET
:
397 /* indexed by TFB buffer instead of by vertex stream */
398 nvc0_query_get(push
, q
, 0x00, 0x0d005002 | (q
->index
<< 5));
401 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
402 if (q
->type
>= NVC0_QUERY_DRV_STAT(0) &&
403 q
->type
<= NVC0_QUERY_DRV_STAT_LAST
) {
404 q
->u
.value
= nvc0
->screen
->base
.stats
.v
[q
->index
] - q
->u
.value
;
408 if ((q
->type
>= NVE4_PM_QUERY(0) && q
->type
<= NVE4_PM_QUERY_LAST
) ||
409 (q
->type
>= NVC0_PM_QUERY(0) && q
->type
<= NVC0_PM_QUERY_LAST
)) {
410 nvc0_mp_pm_query_end(nvc0
, q
);
415 nouveau_fence_ref(nvc0
->screen
->base
.fence
.current
, &q
->fence
);
419 nvc0_query_update(struct nouveau_client
*cli
, struct nvc0_query
*q
)
422 if (nouveau_fence_signalled(q
->fence
))
423 q
->state
= NVC0_QUERY_STATE_READY
;
425 if (q
->data
[0] == q
->sequence
)
426 q
->state
= NVC0_QUERY_STATE_READY
;
431 nvc0_query_result(struct pipe_context
*pipe
, struct pipe_query
*pq
,
432 boolean wait
, union pipe_query_result
*result
)
434 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
435 struct nvc0_query
*q
= nvc0_query(pq
);
436 uint64_t *res64
= (uint64_t*)result
;
437 uint32_t *res32
= (uint32_t*)result
;
438 boolean
*res8
= (boolean
*)result
;
439 uint64_t *data64
= (uint64_t *)q
->data
;
442 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
443 if (q
->type
>= NVC0_QUERY_DRV_STAT(0) &&
444 q
->type
<= NVC0_QUERY_DRV_STAT_LAST
) {
445 res64
[0] = q
->u
.value
;
449 if ((q
->type
>= NVE4_PM_QUERY(0) && q
->type
<= NVE4_PM_QUERY_LAST
) ||
450 (q
->type
>= NVC0_PM_QUERY(0) && q
->type
<= NVC0_PM_QUERY_LAST
)) {
451 return nvc0_mp_pm_query_result(nvc0
, q
, result
, wait
);
454 if (q
->state
!= NVC0_QUERY_STATE_READY
)
455 nvc0_query_update(nvc0
->screen
->base
.client
, q
);
457 if (q
->state
!= NVC0_QUERY_STATE_READY
) {
459 if (q
->state
!= NVC0_QUERY_STATE_FLUSHED
) {
460 q
->state
= NVC0_QUERY_STATE_FLUSHED
;
461 /* flush for silly apps that spin on GL_QUERY_RESULT_AVAILABLE */
462 PUSH_KICK(nvc0
->base
.pushbuf
);
466 if (nouveau_bo_wait(q
->bo
, NOUVEAU_BO_RD
, nvc0
->screen
->base
.client
))
468 NOUVEAU_DRV_STAT(&nvc0
->screen
->base
, query_sync_count
, 1);
470 q
->state
= NVC0_QUERY_STATE_READY
;
473 case PIPE_QUERY_GPU_FINISHED
:
476 case PIPE_QUERY_OCCLUSION_COUNTER
: /* u32 sequence, u32 count, u64 time */
477 res64
[0] = q
->data
[1] - q
->data
[5];
479 case PIPE_QUERY_OCCLUSION_PREDICATE
:
480 res8
[0] = q
->data
[1] != q
->data
[5];
482 case PIPE_QUERY_PRIMITIVES_GENERATED
: /* u64 count, u64 time */
483 case PIPE_QUERY_PRIMITIVES_EMITTED
: /* u64 count, u64 time */
484 res64
[0] = data64
[0] - data64
[2];
486 case PIPE_QUERY_SO_STATISTICS
:
487 res64
[0] = data64
[0] - data64
[4];
488 res64
[1] = data64
[2] - data64
[6];
490 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
491 res8
[0] = data64
[0] != data64
[2];
493 case PIPE_QUERY_TIMESTAMP
:
494 res64
[0] = data64
[1];
496 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
497 res64
[0] = 1000000000;
500 case PIPE_QUERY_TIME_ELAPSED
:
501 res64
[0] = data64
[1] - data64
[3];
503 case PIPE_QUERY_PIPELINE_STATISTICS
:
504 for (i
= 0; i
< 10; ++i
)
505 res64
[i
] = data64
[i
* 2] - data64
[24 + i
* 2];
507 case NVC0_QUERY_TFB_BUFFER_OFFSET
:
508 res32
[0] = q
->data
[1];
511 assert(0); /* can't happen, we don't create queries with invalid type */
519 nvc0_query_fifo_wait(struct nouveau_pushbuf
*push
, struct pipe_query
*pq
)
521 struct nvc0_query
*q
= nvc0_query(pq
);
522 unsigned offset
= q
->offset
;
524 if (q
->type
== PIPE_QUERY_SO_OVERFLOW_PREDICATE
) offset
+= 0x20;
527 PUSH_REFN (push
, q
->bo
, NOUVEAU_BO_GART
| NOUVEAU_BO_RD
);
528 BEGIN_NVC0(push
, SUBC_3D(NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
), 4);
529 PUSH_DATAh(push
, q
->bo
->offset
+ offset
);
530 PUSH_DATA (push
, q
->bo
->offset
+ offset
);
531 PUSH_DATA (push
, q
->sequence
);
532 PUSH_DATA (push
, (1 << 12) |
533 NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL
);
537 nvc0_render_condition(struct pipe_context
*pipe
,
538 struct pipe_query
*pq
,
539 boolean condition
, uint mode
)
541 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
542 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
543 struct nvc0_query
*q
;
545 boolean negated
= FALSE
;
547 mode
!= PIPE_RENDER_COND_NO_WAIT
&&
548 mode
!= PIPE_RENDER_COND_BY_REGION_NO_WAIT
;
550 nvc0
->cond_query
= pq
;
551 nvc0
->cond_cond
= condition
;
552 nvc0
->cond_mode
= mode
;
556 IMMED_NVC0(push
, NVC0_3D(COND_MODE
), NVC0_3D_COND_MODE_ALWAYS
);
561 /* NOTE: comparison of 2 queries only works if both have completed */
563 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
564 cond
= negated
? NVC0_3D_COND_MODE_EQUAL
:
565 NVC0_3D_COND_MODE_NOT_EQUAL
;
568 case PIPE_QUERY_OCCLUSION_COUNTER
:
569 case PIPE_QUERY_OCCLUSION_PREDICATE
:
570 if (likely(!negated
)) {
571 if (unlikely(q
->nesting
))
572 cond
= wait
? NVC0_3D_COND_MODE_NOT_EQUAL
:
573 NVC0_3D_COND_MODE_ALWAYS
;
575 cond
= NVC0_3D_COND_MODE_RES_NON_ZERO
;
577 cond
= wait
? NVC0_3D_COND_MODE_EQUAL
: NVC0_3D_COND_MODE_ALWAYS
;
581 assert(!"render condition query not a predicate");
582 mode
= NVC0_3D_COND_MODE_ALWAYS
;
587 nvc0_query_fifo_wait(push
, pq
);
590 PUSH_REFN (push
, q
->bo
, NOUVEAU_BO_GART
| NOUVEAU_BO_RD
);
591 BEGIN_NVC0(push
, NVC0_3D(COND_ADDRESS_HIGH
), 3);
592 PUSH_DATAh(push
, q
->bo
->offset
+ q
->offset
);
593 PUSH_DATA (push
, q
->bo
->offset
+ q
->offset
);
594 PUSH_DATA (push
, cond
);
595 BEGIN_NVC0(push
, NVC0_2D(COND_ADDRESS_HIGH
), 2);
596 PUSH_DATAh(push
, q
->bo
->offset
+ q
->offset
);
597 PUSH_DATA (push
, q
->bo
->offset
+ q
->offset
);
601 nvc0_query_pushbuf_submit(struct nouveau_pushbuf
*push
,
602 struct pipe_query
*pq
, unsigned result_offset
)
604 struct nvc0_query
*q
= nvc0_query(pq
);
606 #define NVC0_IB_ENTRY_1_NO_PREFETCH (1 << (31 - 8))
608 nouveau_pushbuf_space(push
, 0, 0, 1);
609 nouveau_pushbuf_data(push
, q
->bo
, q
->offset
+ result_offset
, 4 |
610 NVC0_IB_ENTRY_1_NO_PREFETCH
);
614 nvc0_so_target_save_offset(struct pipe_context
*pipe
,
615 struct pipe_stream_output_target
*ptarg
,
616 unsigned index
, boolean
*serialize
)
618 struct nvc0_so_target
*targ
= nvc0_so_target(ptarg
);
622 PUSH_SPACE(nvc0_context(pipe
)->base
.pushbuf
, 1);
623 IMMED_NVC0(nvc0_context(pipe
)->base
.pushbuf
, NVC0_3D(SERIALIZE
), 0);
625 NOUVEAU_DRV_STAT(nouveau_screen(pipe
->screen
), gpu_serialize_count
, 1);
628 nvc0_query(targ
->pq
)->index
= index
;
630 nvc0_query_end(pipe
, targ
->pq
);
634 /* === DRIVER STATISTICS === */
636 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
638 static const char *nvc0_drv_stat_names
[] =
640 "drv-tex_obj_current_count",
641 "drv-tex_obj_current_bytes",
642 "drv-buf_obj_current_count",
643 "drv-buf_obj_current_bytes_vid",
644 "drv-buf_obj_current_bytes_sys",
645 "drv-tex_transfers_rd",
646 "drv-tex_transfers_wr",
647 "drv-tex_copy_count",
648 "drv-tex_blit_count",
649 "drv-tex_cache_flush_count",
650 "drv-buf_transfers_rd",
651 "drv-buf_transfers_wr",
652 "drv-buf_read_bytes_staging_vid",
653 "drv-buf_write_bytes_direct",
654 "drv-buf_write_bytes_staging_vid",
655 "drv-buf_write_bytes_staging_sys",
656 "drv-buf_copy_bytes",
657 "drv-buf_non_kernel_fence_sync_count",
658 "drv-any_non_kernel_fence_sync_count",
659 "drv-query_sync_count",
660 "drv-gpu_serialize_count",
661 "drv-draw_calls_array",
662 "drv-draw_calls_indexed",
663 "drv-draw_calls_fallback_count",
664 "drv-user_buffer_upload_bytes",
665 "drv-constbuf_upload_count",
666 "drv-constbuf_upload_bytes",
668 "drv-resource_validate_count"
671 #endif /* NOUVEAU_ENABLE_DRIVER_STATISTICS */
674 /* === PERFORMANCE MONITORING COUNTERS for NVE4+ === */
676 /* Code to read out MP counters: They are accessible via mmio, too, but let's
677 * just avoid mapping registers in userspace. We'd have to know which MPs are
678 * enabled/present, too, and that information is not presently exposed.
679 * We could add a kernel interface for it, but reading the counters like this
680 * has the advantage of being async (if get_result isn't called immediately).
682 static const uint64_t nve4_read_mp_pm_counters_code
[] =
684 /* sched 0x20 0x20 0x20 0x20 0x20 0x20 0x20
686 * mov b32 $r12 $physid
692 * sched 0x20 0x20 0x23 0x04 0x20 0x04 0x2b
696 * set $p0 0x1 eq u32 $r8 0x0
697 * mov b32 $r10 c0[0x0]
698 * ext u32 $r8 $r12 0x414
699 * mov b32 $r11 c0[0x4]
700 * sched 0x04 0x2e 0x04 0x20 0x20 0x28 0x04
701 * ext u32 $r9 $r12 0x208
703 * set $p1 0x1 eq u32 $r9 0x0
704 * mul $r8 u32 $r8 u32 96
705 * mul $r12 u32 $r9 u32 16
706 * mul $r13 u32 $r9 u32 4
707 * add b32 $r9 $r8 $r13
708 * sched 0x28 0x04 0x2c 0x04 0x2c 0x04 0x2c
709 * add b32 $r8 $r8 $r12
711 * add b32 $r10 $c $r10 $r8
713 * add b32 $r11 $r11 0x0 $c
714 * add b32 $r12 $c $r12 $r9
715 * st b128 wt g[$r10d] $r0q
716 * sched 0x4 0x2c 0x20 0x04 0x2e 0x00 0x00
717 * mov b32 $r0 c0[0x8]
718 * add b32 $r13 $r13 0x0 $c
719 * $p1 st b128 wt g[$r12d+0x40] $r4q
720 * st b32 wt g[$r12d+0x50] $r0
722 0x2202020202020207ULL
,
723 0x2c00000084021c04ULL
,
724 0x2c0000000c031c04ULL
,
725 0x2c00000010001c04ULL
,
726 0x2c00000014005c04ULL
,
727 0x2c00000018009c04ULL
,
728 0x2c0000001c00dc04ULL
,
729 0x2c00000020011c04ULL
,
730 0x22b0420042320207ULL
,
731 0x2c00000024015c04ULL
,
732 0x2c00000028019c04ULL
,
733 0x2c0000002c01dc04ULL
,
734 0x190e0000fc81dc03ULL
,
735 0x2800400000029de4ULL
,
736 0x7000c01050c21c03ULL
,
737 0x280040001002dde4ULL
,
738 0x204282020042e047ULL
,
739 0x7000c00820c25c03ULL
,
740 0x80000000000021e7ULL
,
741 0x190e0000fc93dc03ULL
,
742 0x1000000180821c02ULL
,
743 0x1000000040931c02ULL
,
744 0x1000000010935c02ULL
,
745 0x4800000034825c03ULL
,
746 0x22c042c042c04287ULL
,
747 0x4800000030821c03ULL
,
748 0x2800000028031de4ULL
,
749 0x4801000020a29c03ULL
,
750 0x280000002c035de4ULL
,
751 0x0800000000b2dc42ULL
,
752 0x4801000024c31c03ULL
,
753 0x9400000000a01fc5ULL
,
754 0x200002e04202c047ULL
,
755 0x2800400020001de4ULL
,
756 0x0800000000d35c42ULL
,
757 0x9400000100c107c5ULL
,
758 0x9400000140c01f85ULL
,
759 0x8000000000001de7ULL
762 /* NOTE: intentionally using the same names as NV */
763 static const char *nve4_pm_query_names
[] =
785 "l1_local_load_miss",
786 "l1_local_store_hit",
787 "l1_local_store_miss",
790 "l1_global_load_hit",
791 "l1_global_load_miss",
792 "uncached_global_load_transaction",
793 "global_store_transaction",
801 "shared_load_replay",
802 "shared_store_replay",
803 "local_load_transactions",
804 "local_store_transactions",
805 "l1_shared_load_transactions",
806 "l1_shared_store_transactions",
807 "global_ld_mem_divergence_replays",
808 "global_st_mem_divergence_replays",
809 /* metrics, i.e. functions of the MP counters */
810 "metric-ipc", /* inst_executed, clock */
811 "metric-ipac", /* inst_executed, active_cycles */
812 "metric-ipec", /* inst_executed, (bool)inst_executed */
813 "metric-achieved_occupancy", /* active_warps, active_cycles */
814 "metric-sm_efficiency", /* active_cycles, clock */
815 "metric-inst_replay_overhead" /* inst_issued, inst_executed */
818 /* For simplicity, we will allocate as many group slots as we allocate counter
819 * slots. This means that a single counter which wants to source from 2 groups
820 * will have to be declared as using 2 counter slots. This shouldn't really be
821 * a problem because such queries don't make much sense ... (unless someone is
824 struct nvc0_mp_counter_cfg
826 uint32_t func
: 16; /* mask or 4-bit logic op (depending on mode) */
827 uint32_t mode
: 4; /* LOGOP,B6,LOGOP_B6(_PULSE) */
828 uint32_t num_src
: 3; /* number of sources (1 - 6, only for NVC0:NVE4) */
829 uint32_t sig_dom
: 1; /* if 0, MP_PM_A (per warp-sched), if 1, MP_PM_B */
830 uint32_t sig_sel
: 8; /* signal group */
831 uint64_t src_sel
; /* signal selection for up to 6 sources (48 bit) */
834 #define NVC0_COUNTER_OPn_SUM 0
835 #define NVC0_COUNTER_OPn_OR 1
836 #define NVC0_COUNTER_OPn_AND 2
837 #define NVC0_COUNTER_OP2_REL_SUM_MM 3 /* (sum(ctr0) - sum(ctr1)) / sum(ctr0) */
838 #define NVC0_COUNTER_OP2_DIV_SUM_M0 4 /* sum(ctr0) / ctr1 of MP[0]) */
839 #define NVC0_COUNTER_OP2_AVG_DIV_MM 5 /* avg(ctr0 / ctr1) */
840 #define NVC0_COUNTER_OP2_AVG_DIV_M0 6 /* avg(ctr0) / ctr1 of MP[0]) */
842 struct nvc0_mp_pm_query_cfg
844 struct nvc0_mp_counter_cfg ctr
[4];
845 uint8_t num_counters
;
847 uint8_t norm
[2]; /* normalization num,denom */
850 #define _Q1A(n, f, m, g, s, nu, dn) [NVE4_PM_QUERY_##n] = { { { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g, s }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { nu, dn } }
851 #define _Q1B(n, f, m, g, s, nu, dn) [NVE4_PM_QUERY_##n] = { { { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g, s }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { nu, dn } }
852 #define _M2A(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_PM_QUERY_METRIC_##n] = { { \
853 { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g0, s0 }, \
854 { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g1, s1 }, \
855 {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
856 #define _M2B(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_PM_QUERY_METRIC_##n] = { { \
857 { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g0, s0 }, \
858 { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g1, s1 }, \
859 {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
860 #define _M2AB(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_PM_QUERY_METRIC_##n] = { { \
861 { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g0, s0 }, \
862 { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g1, s1 }, \
863 {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
866 * active_warps: bit 0 alternates btw 0 and 1 for odd nr of warps
867 * inst_executed etc.: we only count a single warp scheduler
868 * metric-ipXc: we simply multiply by 4 to account for the 4 warp schedulers;
869 * this is inaccurate !
871 static const struct nvc0_mp_pm_query_cfg nve4_mp_pm_queries
[] =
873 _Q1A(PROF_TRIGGER_0
, 0x0001, B6
, USER
, 0x00000000, 1, 1),
874 _Q1A(PROF_TRIGGER_1
, 0x0001, B6
, USER
, 0x00000004, 1, 1),
875 _Q1A(PROF_TRIGGER_2
, 0x0001, B6
, USER
, 0x00000008, 1, 1),
876 _Q1A(PROF_TRIGGER_3
, 0x0001, B6
, USER
, 0x0000000c, 1, 1),
877 _Q1A(PROF_TRIGGER_4
, 0x0001, B6
, USER
, 0x00000010, 1, 1),
878 _Q1A(PROF_TRIGGER_5
, 0x0001, B6
, USER
, 0x00000014, 1, 1),
879 _Q1A(PROF_TRIGGER_6
, 0x0001, B6
, USER
, 0x00000018, 1, 1),
880 _Q1A(PROF_TRIGGER_7
, 0x0001, B6
, USER
, 0x0000001c, 1, 1),
881 _Q1A(LAUNCHED_WARPS
, 0x0001, B6
, LAUNCH
, 0x00000004, 1, 1),
882 _Q1A(LAUNCHED_THREADS
, 0x003f, B6
, LAUNCH
, 0x398a4188, 1, 1),
883 _Q1B(LAUNCHED_CTA
, 0x0001, B6
, WARP
, 0x0000001c, 1, 1),
884 _Q1A(INST_ISSUED1
, 0x0001, B6
, ISSUE
, 0x00000004, 1, 1),
885 _Q1A(INST_ISSUED2
, 0x0001, B6
, ISSUE
, 0x00000008, 1, 1),
886 _Q1A(INST_ISSUED
, 0x0003, B6
, ISSUE
, 0x00000104, 1, 1),
887 _Q1A(INST_EXECUTED
, 0x0003, B6
, EXEC
, 0x00000398, 1, 1),
888 _Q1A(LD_SHARED
, 0x0001, B6
, LDST
, 0x00000000, 1, 1),
889 _Q1A(ST_SHARED
, 0x0001, B6
, LDST
, 0x00000004, 1, 1),
890 _Q1A(LD_LOCAL
, 0x0001, B6
, LDST
, 0x00000008, 1, 1),
891 _Q1A(ST_LOCAL
, 0x0001, B6
, LDST
, 0x0000000c, 1, 1),
892 _Q1A(GLD_REQUEST
, 0x0001, B6
, LDST
, 0x00000010, 1, 1),
893 _Q1A(GST_REQUEST
, 0x0001, B6
, LDST
, 0x00000014, 1, 1),
894 _Q1B(L1_LOCAL_LOAD_HIT
, 0x0001, B6
, L1
, 0x00000000, 1, 1),
895 _Q1B(L1_LOCAL_LOAD_MISS
, 0x0001, B6
, L1
, 0x00000004, 1, 1),
896 _Q1B(L1_LOCAL_STORE_HIT
, 0x0001, B6
, L1
, 0x00000008, 1, 1),
897 _Q1B(L1_LOCAL_STORE_MISS
, 0x0001, B6
, L1
, 0x0000000c, 1, 1),
898 _Q1B(L1_GLOBAL_LOAD_HIT
, 0x0001, B6
, L1
, 0x00000010, 1, 1),
899 _Q1B(L1_GLOBAL_LOAD_MISS
, 0x0001, B6
, L1
, 0x00000014, 1, 1),
900 _Q1B(GLD_TRANSACTIONS_UNCACHED
, 0x0001, B6
, MEM
, 0x00000000, 1, 1),
901 _Q1B(GST_TRANSACTIONS
, 0x0001, B6
, MEM
, 0x00000004, 1, 1),
902 _Q1A(BRANCH
, 0x0001, B6
, BRANCH
, 0x0000000c, 1, 1),
903 _Q1A(BRANCH_DIVERGENT
, 0x0001, B6
, BRANCH
, 0x00000010, 1, 1),
904 _Q1B(ACTIVE_WARPS
, 0x003f, B6
, WARP
, 0x31483104, 2, 1),
905 _Q1B(ACTIVE_CYCLES
, 0x0001, B6
, WARP
, 0x00000000, 1, 1),
906 _Q1A(ATOM_COUNT
, 0x0001, B6
, BRANCH
, 0x00000000, 1, 1),
907 _Q1A(GRED_COUNT
, 0x0001, B6
, BRANCH
, 0x00000008, 1, 1),
908 _Q1B(LD_SHARED_REPLAY
, 0x0001, B6
, REPLAY
, 0x00000008, 1, 1),
909 _Q1B(ST_SHARED_REPLAY
, 0x0001, B6
, REPLAY
, 0x0000000c, 1, 1),
910 _Q1B(LD_LOCAL_TRANSACTIONS
, 0x0001, B6
, TRANSACTION
, 0x00000000, 1, 1),
911 _Q1B(ST_LOCAL_TRANSACTIONS
, 0x0001, B6
, TRANSACTION
, 0x00000004, 1, 1),
912 _Q1B(L1_LD_SHARED_TRANSACTIONS
, 0x0001, B6
, TRANSACTION
, 0x00000008, 1, 1),
913 _Q1B(L1_ST_SHARED_TRANSACTIONS
, 0x0001, B6
, TRANSACTION
, 0x0000000c, 1, 1),
914 _Q1B(GLD_MEM_DIV_REPLAY
, 0x0001, B6
, REPLAY
, 0x00000010, 1, 1),
915 _Q1B(GST_MEM_DIV_REPLAY
, 0x0001, B6
, REPLAY
, 0x00000014, 1, 1),
916 _M2AB(IPC
, 0x3, B6
, EXEC
, 0x398, 0xffff, LOGOP
, WARP
, 0x0, DIV_SUM_M0
, 10, 1),
917 _M2AB(IPAC
, 0x3, B6
, EXEC
, 0x398, 0x1, B6
, WARP
, 0x0, AVG_DIV_MM
, 10, 1),
918 _M2A(IPEC
, 0x3, B6
, EXEC
, 0x398, 0xe, LOGOP
, EXEC
, 0x398, AVG_DIV_MM
, 10, 1),
919 _M2A(INST_REPLAY_OHEAD
, 0x3, B6
, ISSUE
, 0x104, 0x3, B6
, EXEC
, 0x398, REL_SUM_MM
, 100, 1),
920 _M2B(MP_OCCUPANCY
, 0x3f, B6
, WARP
, 0x31483104, 0x01, B6
, WARP
, 0x0, AVG_DIV_MM
, 200, 64),
921 _M2B(MP_EFFICIENCY
, 0x01, B6
, WARP
, 0x0, 0xffff, LOGOP
, WARP
, 0x0, AVG_DIV_M0
, 100, 1),
929 /* === PERFORMANCE MONITORING COUNTERS for NVC0:NVE4 === */
930 static const uint64_t nvc0_read_mp_pm_counters_code
[] =
933 * mov b32 $r9 $physid
942 * set $p0 0x1 eq u32 $r8 0x0
943 * mov b32 $r10 c0[0x0]
944 * mov b32 $r11 c0[0x4]
945 * ext u32 $r8 $r9 0x414
947 * mul $r8 u32 $r8 u32 36
948 * add b32 $r10 $c $r10 $r8
949 * add b32 $r11 $r11 0x0 $c
950 * mov b32 $r8 c0[0x8]
951 * st b128 wt g[$r10d+0x00] $r0q
952 * st b128 wt g[$r10d+0x10] $r4q
953 * st b32 wt g[$r10d+0x20] $r8
955 0x2c00000084021c04ULL
,
956 0x2c0000000c025c04ULL
,
957 0x2c00000010001c04ULL
,
958 0x2c00000014005c04ULL
,
959 0x2c00000018009c04ULL
,
960 0x2c0000001c00dc04ULL
,
961 0x2c00000020011c04ULL
,
962 0x2c00000024015c04ULL
,
963 0x2c00000028019c04ULL
,
964 0x2c0000002c01dc04ULL
,
965 0x190e0000fc81dc03ULL
,
966 0x2800400000029de4ULL
,
967 0x280040001002dde4ULL
,
968 0x7000c01050921c03ULL
,
969 0x80000000000021e7ULL
,
970 0x1000000090821c02ULL
,
971 0x4801000020a29c03ULL
,
972 0x0800000000b2dc42ULL
,
973 0x2800400020021de4ULL
,
974 0x9400000000a01fc5ULL
,
975 0x9400000040a11fc5ULL
,
976 0x9400000080a21f85ULL
,
977 0x8000000000001de7ULL
980 static const char *nvc0_pm_query_names
[] =
1002 "thread_inst_executed_0",
1003 "thread_inst_executed_1",
1004 "thread_inst_executed_2",
1005 "thread_inst_executed_3",
1016 #define _Q(n, f, m, g, c, s0, s1, s2, s3, s4, s5) [NVC0_PM_QUERY_##n] = { { { f, NVC0_COMPUTE_MP_PM_OP_MODE_##m, c, 0, g, s0|(s1 << 8)|(s2 << 16)|(s3 << 24)|(s4##ULL << 32)|(s5##ULL << 40) }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { 1, 1 } }
1018 static const struct nvc0_mp_pm_query_cfg nvc0_mp_pm_queries
[] =
1020 _Q(INST_EXECUTED
, 0xaaaa, LOGOP
, 0x2d, 3, 0x00, 0x11, 0x22, 0x00, 0x00, 0x00),
1021 _Q(BRANCH
, 0xaaaa, LOGOP
, 0x1a, 2, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00),
1022 _Q(BRANCH_DIVERGENT
, 0xaaaa, LOGOP
, 0x19, 2, 0x20, 0x31, 0x00, 0x00, 0x00, 0x00),
1023 _Q(ACTIVE_WARPS
, 0xaaaa, LOGOP
, 0x24, 6, 0x10, 0x21, 0x32, 0x43, 0x54, 0x65),
1024 _Q(ACTIVE_CYCLES
, 0xaaaa, LOGOP
, 0x11, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
1025 _Q(LAUNCHED_WARPS
, 0xaaaa, LOGOP
, 0x26, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
1026 _Q(LAUNCHED_THREADS
, 0xaaaa, LOGOP
, 0x26, 6, 0x10, 0x21, 0x32, 0x43, 0x54, 0x65),
1027 _Q(LD_SHARED
, 0xaaaa, LOGOP
, 0x64, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
1028 _Q(ST_SHARED
, 0xaaaa, LOGOP
, 0x64, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
1029 _Q(LD_LOCAL
, 0xaaaa, LOGOP
, 0x64, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
1030 _Q(ST_LOCAL
, 0xaaaa, LOGOP
, 0x64, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
1031 _Q(GRED_COUNT
, 0xaaaa, LOGOP
, 0x63, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
1032 _Q(ATOM_COUNT
, 0xaaaa, LOGOP
, 0x63, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
1033 _Q(GLD_REQUEST
, 0xaaaa, LOGOP
, 0x64, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
1034 _Q(GST_REQUEST
, 0xaaaa, LOGOP
, 0x64, 1, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00),
1035 _Q(INST_ISSUED1_0
, 0xaaaa, LOGOP
, 0x7e, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
1036 _Q(INST_ISSUED1_1
, 0xaaaa, LOGOP
, 0x7e, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
1037 _Q(INST_ISSUED2_0
, 0xaaaa, LOGOP
, 0x7e, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
1038 _Q(INST_ISSUED2_1
, 0xaaaa, LOGOP
, 0x7e, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
1039 _Q(TH_INST_EXECUTED_0
, 0xaaaa, LOGOP
, 0xa3, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
1040 _Q(TH_INST_EXECUTED_1
, 0xaaaa, LOGOP
, 0xa5, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
1041 _Q(TH_INST_EXECUTED_2
, 0xaaaa, LOGOP
, 0xa4, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
1042 _Q(TH_INST_EXECUTED_3
, 0xaaaa, LOGOP
, 0xa6, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
1043 _Q(PROF_TRIGGER_0
, 0xaaaa, LOGOP
, 0x01, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
1044 _Q(PROF_TRIGGER_1
, 0xaaaa, LOGOP
, 0x01, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
1045 _Q(PROF_TRIGGER_2
, 0xaaaa, LOGOP
, 0x01, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
1046 _Q(PROF_TRIGGER_3
, 0xaaaa, LOGOP
, 0x01, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
1047 _Q(PROF_TRIGGER_4
, 0xaaaa, LOGOP
, 0x01, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
1048 _Q(PROF_TRIGGER_5
, 0xaaaa, LOGOP
, 0x01, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
1049 _Q(PROF_TRIGGER_6
, 0xaaaa, LOGOP
, 0x01, 1, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00),
1050 _Q(PROF_TRIGGER_7
, 0xaaaa, LOGOP
, 0x01, 1, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00),
1055 static const struct nvc0_mp_pm_query_cfg
*
1056 nvc0_mp_pm_query_get_cfg(struct nvc0_context
*nvc0
, struct nvc0_query
*q
)
1058 struct nvc0_screen
*screen
= nvc0
->screen
;
1060 if (screen
->base
.class_3d
>= NVE4_3D_CLASS
)
1061 return &nve4_mp_pm_queries
[q
->type
- PIPE_QUERY_DRIVER_SPECIFIC
];
1062 return &nvc0_mp_pm_queries
[q
->type
- NVC0_PM_QUERY(0)];
1066 nvc0_mp_pm_query_begin(struct nvc0_context
*nvc0
, struct nvc0_query
*q
)
1068 struct nvc0_screen
*screen
= nvc0
->screen
;
1069 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
1070 const struct nvc0_mp_pm_query_cfg
*cfg
;
1072 unsigned num_ab
[2] = { 0, 0 };
1074 cfg
= nvc0_mp_pm_query_get_cfg(nvc0
, q
);
1076 /* check if we have enough free counter slots */
1077 for (i
= 0; i
< cfg
->num_counters
; ++i
)
1078 num_ab
[cfg
->ctr
[i
].sig_dom
]++;
1080 if (screen
->pm
.num_mp_pm_active
[0] + num_ab
[0] > 4 ||
1081 screen
->pm
.num_mp_pm_active
[1] + num_ab
[1] > 4) {
1082 NOUVEAU_ERR("Not enough free MP counter slots !\n");
1086 assert(cfg
->num_counters
<= 4);
1087 PUSH_SPACE(push
, 4 * 8 + 6);
1089 if (!screen
->pm
.mp_counters_enabled
) {
1090 screen
->pm
.mp_counters_enabled
= TRUE
;
1091 BEGIN_NVC0(push
, SUBC_SW(0x06ac), 1);
1092 PUSH_DATA (push
, 0x1fcb);
1095 /* set sequence field to 0 (used to check if result is available) */
1096 for (i
= 0; i
< screen
->mp_count
; ++i
)
1097 q
->data
[i
* 10 + 10] = 0;
1099 for (i
= 0; i
< cfg
->num_counters
; ++i
) {
1100 const unsigned d
= cfg
->ctr
[i
].sig_dom
;
1102 if (!screen
->pm
.num_mp_pm_active
[d
]) {
1103 uint32_t m
= (1 << 22) | (1 << (7 + (8 * !d
)));
1104 if (screen
->pm
.num_mp_pm_active
[!d
])
1105 m
|= 1 << (7 + (8 * d
));
1106 BEGIN_NVC0(push
, SUBC_SW(0x0600), 1);
1107 PUSH_DATA (push
, m
);
1109 screen
->pm
.num_mp_pm_active
[d
]++;
1111 for (c
= d
* 4; c
< (d
* 4 + 4); ++c
) {
1112 if (!screen
->pm
.mp_counter
[c
]) {
1114 screen
->pm
.mp_counter
[c
] = (struct pipe_query
*)q
;
1118 assert(c
<= (d
* 4 + 3)); /* must succeed, already checked for space */
1120 /* configure and reset the counter(s) */
1121 if (screen
->base
.class_3d
>= NVE4_3D_CLASS
) {
1123 BEGIN_NVC0(push
, NVE4_COMPUTE(MP_PM_A_SIGSEL(c
& 3)), 1);
1125 BEGIN_NVC0(push
, NVE4_COMPUTE(MP_PM_B_SIGSEL(c
& 3)), 1);
1126 PUSH_DATA (push
, cfg
->ctr
[i
].sig_sel
);
1127 BEGIN_NVC0(push
, NVE4_COMPUTE(MP_PM_SRCSEL(c
)), 1);
1128 PUSH_DATA (push
, cfg
->ctr
[i
].src_sel
+ 0x2108421 * (c
& 3));
1129 BEGIN_NVC0(push
, NVE4_COMPUTE(MP_PM_FUNC(c
)), 1);
1130 PUSH_DATA (push
, (cfg
->ctr
[i
].func
<< 4) | cfg
->ctr
[i
].mode
);
1131 BEGIN_NVC0(push
, NVE4_COMPUTE(MP_PM_SET(c
)), 1);
1132 PUSH_DATA (push
, 0);
1136 for (s
= 0; s
< cfg
->ctr
[i
].num_src
; s
++) {
1137 BEGIN_NVC0(push
, NVC0_COMPUTE(MP_PM_SIGSEL(s
)), 1);
1138 PUSH_DATA (push
, cfg
->ctr
[i
].sig_sel
);
1139 BEGIN_NVC0(push
, NVC0_COMPUTE(MP_PM_SRCSEL(s
)), 1);
1140 PUSH_DATA (push
, (cfg
->ctr
[i
].src_sel
>> (s
* 8)) & 0xff);
1141 BEGIN_NVC0(push
, NVC0_COMPUTE(MP_PM_OP(s
)), 1);
1142 PUSH_DATA (push
, (cfg
->ctr
[i
].func
<< 4) | cfg
->ctr
[i
].mode
);
1143 BEGIN_NVC0(push
, NVC0_COMPUTE(MP_PM_SET(s
)), 1);
1144 PUSH_DATA (push
, 0);
1151 nvc0_mp_pm_query_end(struct nvc0_context
*nvc0
, struct nvc0_query
*q
)
1153 struct nvc0_screen
*screen
= nvc0
->screen
;
1154 struct pipe_context
*pipe
= &nvc0
->base
.pipe
;
1155 struct nouveau_pushbuf
*push
= nvc0
->base
.pushbuf
;
1156 const boolean is_nve4
= screen
->base
.class_3d
>= NVE4_3D_CLASS
;
1159 const uint block
[3] = { 32, is_nve4
? 4 : 1, 1 };
1160 const uint grid
[3] = { screen
->mp_count
, 1, 1 };
1162 const struct nvc0_mp_pm_query_cfg
*cfg
;
1164 cfg
= nvc0_mp_pm_query_get_cfg(nvc0
, q
);
1166 if (unlikely(!screen
->pm
.prog
)) {
1167 struct nvc0_program
*prog
= CALLOC_STRUCT(nvc0_program
);
1168 prog
->type
= PIPE_SHADER_COMPUTE
;
1169 prog
->translated
= TRUE
;
1170 prog
->num_gprs
= 14;
1171 prog
->parm_size
= 12;
1173 prog
->code
= (uint32_t *)nve4_read_mp_pm_counters_code
;
1174 prog
->code_size
= sizeof(nve4_read_mp_pm_counters_code
);
1176 prog
->code
= (uint32_t *)nvc0_read_mp_pm_counters_code
;
1177 prog
->code_size
= sizeof(nvc0_read_mp_pm_counters_code
);
1179 screen
->pm
.prog
= prog
;
1182 /* disable all counting */
1183 PUSH_SPACE(push
, 8);
1184 for (c
= 0; c
< 8; ++c
)
1185 if (screen
->pm
.mp_counter
[c
]) {
1187 IMMED_NVC0(push
, NVE4_COMPUTE(MP_PM_FUNC(c
)), 0);
1189 IMMED_NVC0(push
, NVC0_COMPUTE(MP_PM_OP(c
)), 0);
1192 /* release counters for this query */
1193 for (c
= 0; c
< 8; ++c
) {
1194 if (nvc0_query(screen
->pm
.mp_counter
[c
]) == q
) {
1195 screen
->pm
.num_mp_pm_active
[c
/ 4]--;
1196 screen
->pm
.mp_counter
[c
] = NULL
;
1200 BCTX_REFN_bo(nvc0
->bufctx_cp
, CP_QUERY
, NOUVEAU_BO_GART
| NOUVEAU_BO_WR
,
1203 PUSH_SPACE(push
, 1);
1204 IMMED_NVC0(push
, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE
), 0);
1206 pipe
->bind_compute_state(pipe
, screen
->pm
.prog
);
1207 input
[0] = (q
->bo
->offset
+ q
->base
);
1208 input
[1] = (q
->bo
->offset
+ q
->base
) >> 32;
1209 input
[2] = q
->sequence
;
1210 pipe
->launch_grid(pipe
, block
, grid
, 0, input
);
1212 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_QUERY
);
1214 /* re-activate other counters */
1215 PUSH_SPACE(push
, 16);
1217 for (c
= 0; c
< 8; ++c
) {
1219 q
= nvc0_query(screen
->pm
.mp_counter
[c
]);
1222 cfg
= nvc0_mp_pm_query_get_cfg(nvc0
, q
);
1223 for (i
= 0; i
< cfg
->num_counters
; ++i
) {
1224 if (mask
& (1 << q
->ctr
[i
]))
1226 mask
|= 1 << q
->ctr
[i
];
1228 BEGIN_NVC0(push
, NVE4_COMPUTE(MP_PM_FUNC(q
->ctr
[i
])), 1);
1230 BEGIN_NVC0(push
, NVC0_COMPUTE(MP_PM_OP(q
->ctr
[i
])), 1);
1232 PUSH_DATA (push
, (cfg
->ctr
[i
].func
<< 4) | cfg
->ctr
[i
].mode
);
1237 static INLINE boolean
1238 nvc0_mp_pm_query_read_data(uint32_t count
[32][4],
1239 struct nvc0_context
*nvc0
, boolean wait
,
1240 struct nvc0_query
*q
,
1241 const struct nvc0_mp_pm_query_cfg
*cfg
,
1246 for (p
= 0; p
< mp_count
; ++p
) {
1247 const unsigned b
= (0x24 / 4) * p
;
1249 for (c
= 0; c
< cfg
->num_counters
; ++c
) {
1250 if (q
->data
[b
+ 8] != q
->sequence
) {
1253 if (nouveau_bo_wait(q
->bo
, NOUVEAU_BO_RD
, nvc0
->base
.client
))
1256 count
[p
][c
] = q
->data
[b
+ q
->ctr
[c
]];
1262 static INLINE boolean
1263 nve4_mp_pm_query_read_data(uint32_t count
[32][4],
1264 struct nvc0_context
*nvc0
, boolean wait
,
1265 struct nvc0_query
*q
,
1266 const struct nvc0_mp_pm_query_cfg
*cfg
,
1271 for (p
= 0; p
< mp_count
; ++p
) {
1272 const unsigned b
= (0x60 / 4) * p
;
1274 for (c
= 0; c
< cfg
->num_counters
; ++c
) {
1276 for (d
= 0; d
< ((q
->ctr
[c
] & ~3) ? 1 : 4); ++d
) {
1277 if (q
->data
[b
+ 20 + d
] != q
->sequence
) {
1280 if (nouveau_bo_wait(q
->bo
, NOUVEAU_BO_RD
, nvc0
->base
.client
))
1283 if (q
->ctr
[c
] & ~0x3)
1284 count
[p
][c
] = q
->data
[b
+ 16 + (q
->ctr
[c
] & 3)];
1286 count
[p
][c
] += q
->data
[b
+ d
* 4 + q
->ctr
[c
]];
1293 /* Metric calculations:
1294 * sum(x) ... sum of x over all MPs
1295 * avg(x) ... average of x over all MPs
1297 * IPC : sum(inst_executed) / clock
1298 * INST_REPLAY_OHEAD: (sum(inst_issued) - sum(inst_executed)) / sum(inst_issued)
1299 * MP_OCCUPANCY : avg((active_warps / 64) / active_cycles)
1300 * MP_EFFICIENCY : avg(active_cycles / clock)
1302 * NOTE: Interpretation of IPC requires knowledge of MP count.
1305 nvc0_mp_pm_query_result(struct nvc0_context
*nvc0
, struct nvc0_query
*q
,
1306 void *result
, boolean wait
)
1308 uint32_t count
[32][4];
1310 unsigned mp_count
= MIN2(nvc0
->screen
->mp_count_compute
, 32);
1312 const struct nvc0_mp_pm_query_cfg
*cfg
;
1315 cfg
= nvc0_mp_pm_query_get_cfg(nvc0
, q
);
1317 if (nvc0
->screen
->base
.class_3d
>= NVE4_3D_CLASS
)
1318 ret
= nve4_mp_pm_query_read_data(count
, nvc0
, wait
, q
, cfg
, mp_count
);
1320 ret
= nvc0_mp_pm_query_read_data(count
, nvc0
, wait
, q
, cfg
, mp_count
);
1324 if (cfg
->op
== NVC0_COUNTER_OPn_SUM
) {
1325 for (c
= 0; c
< cfg
->num_counters
; ++c
)
1326 for (p
= 0; p
< mp_count
; ++p
)
1327 value
+= count
[p
][c
];
1328 value
= (value
* cfg
->norm
[0]) / cfg
->norm
[1];
1330 if (cfg
->op
== NVC0_COUNTER_OPn_OR
) {
1332 for (c
= 0; c
< cfg
->num_counters
; ++c
)
1333 for (p
= 0; p
< mp_count
; ++p
)
1335 value
= (v
* cfg
->norm
[0]) / cfg
->norm
[1];
1337 if (cfg
->op
== NVC0_COUNTER_OPn_AND
) {
1339 for (c
= 0; c
< cfg
->num_counters
; ++c
)
1340 for (p
= 0; p
< mp_count
; ++p
)
1342 value
= (v
* cfg
->norm
[0]) / cfg
->norm
[1];
1344 if (cfg
->op
== NVC0_COUNTER_OP2_REL_SUM_MM
) {
1345 uint64_t v
[2] = { 0, 0 };
1346 for (p
= 0; p
< mp_count
; ++p
) {
1347 v
[0] += count
[p
][0];
1348 v
[1] += count
[p
][1];
1351 value
= ((v
[0] - v
[1]) * cfg
->norm
[0]) / (v
[0] * cfg
->norm
[1]);
1353 if (cfg
->op
== NVC0_COUNTER_OP2_DIV_SUM_M0
) {
1354 for (p
= 0; p
< mp_count
; ++p
)
1355 value
+= count
[p
][0];
1357 value
= (value
* cfg
->norm
[0]) / (count
[0][1] * cfg
->norm
[1]);
1361 if (cfg
->op
== NVC0_COUNTER_OP2_AVG_DIV_MM
) {
1362 unsigned mp_used
= 0;
1363 for (p
= 0; p
< mp_count
; ++p
, mp_used
+= !!count
[p
][0])
1365 value
+= (count
[p
][0] * cfg
->norm
[0]) / count
[p
][1];
1367 value
/= mp_used
* cfg
->norm
[1];
1369 if (cfg
->op
== NVC0_COUNTER_OP2_AVG_DIV_M0
) {
1370 unsigned mp_used
= 0;
1371 for (p
= 0; p
< mp_count
; ++p
, mp_used
+= !!count
[p
][0])
1372 value
+= count
[p
][0];
1373 if (count
[0][1] && mp_used
) {
1374 value
*= cfg
->norm
[0];
1375 value
/= count
[0][1] * mp_used
* cfg
->norm
[1];
1381 *(uint64_t *)result
= value
;
1386 nvc0_screen_get_driver_query_info(struct pipe_screen
*pscreen
,
1388 struct pipe_driver_query_info
*info
)
1390 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
1393 count
+= NVC0_QUERY_DRV_STAT_COUNT
;
1395 if (screen
->base
.device
->drm_version
>= 0x01000101) {
1396 if (screen
->base
.class_3d
>= NVE4_3D_CLASS
) {
1397 count
+= NVE4_PM_QUERY_COUNT
;
1399 if (screen
->compute
) {
1400 count
+= NVC0_PM_QUERY_COUNT
; /* NVC0_COMPUTE is not always enabled */
1407 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
1408 if (id
< NVC0_QUERY_DRV_STAT_COUNT
) {
1409 info
->name
= nvc0_drv_stat_names
[id
];
1410 info
->query_type
= NVC0_QUERY_DRV_STAT(id
);
1411 info
->max_value
= ~0ULL;
1412 info
->uses_byte_units
= !!strstr(info
->name
, "bytes");
1417 if (screen
->base
.class_3d
>= NVE4_3D_CLASS
) {
1418 info
->name
= nve4_pm_query_names
[id
- NVC0_QUERY_DRV_STAT_COUNT
];
1419 info
->query_type
= NVE4_PM_QUERY(id
- NVC0_QUERY_DRV_STAT_COUNT
);
1420 info
->max_value
= (id
< NVE4_PM_QUERY_METRIC_MP_OCCUPANCY
) ?
1422 info
->uses_byte_units
= FALSE
;
1425 if (screen
->compute
) {
1426 info
->name
= nvc0_pm_query_names
[id
- NVC0_QUERY_DRV_STAT_COUNT
];
1427 info
->query_type
= NVC0_PM_QUERY(id
- NVC0_QUERY_DRV_STAT_COUNT
);
1428 info
->max_value
= ~0ULL;
1429 info
->uses_byte_units
= FALSE
;
1433 /* user asked for info about non-existing query */
1434 info
->name
= "this_is_not_the_query_you_are_looking_for";
1435 info
->query_type
= 0xdeadd01d;
1436 info
->max_value
= 0;
1437 info
->uses_byte_units
= FALSE
;
1442 nvc0_init_query_functions(struct nvc0_context
*nvc0
)
1444 struct pipe_context
*pipe
= &nvc0
->base
.pipe
;
1446 pipe
->create_query
= nvc0_query_create
;
1447 pipe
->destroy_query
= nvc0_query_destroy
;
1448 pipe
->begin_query
= nvc0_query_begin
;
1449 pipe
->end_query
= nvc0_query_end
;
1450 pipe
->get_query_result
= nvc0_query_result
;
1451 pipe
->render_condition
= nvc0_render_condition
;