0ad8a91ee6d168730b6f48fee56caff1d7ef0980
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_query_hw_sm.h
1 #ifndef __NVC0_QUERY_HW_SM_H__
2 #define __NVC0_QUERY_HW_SM_H__
3
4 #include "nvc0_query_hw.h"
5
6 struct nvc0_hw_sm_query {
7 struct nvc0_hw_query base;
8 uint8_t ctr[8];
9 };
10
11 static inline struct nvc0_hw_sm_query *
12 nvc0_hw_sm_query(struct nvc0_hw_query *hq)
13 {
14 return (struct nvc0_hw_sm_query *)hq;
15 }
16
17 /*
18 * Performance counter queries:
19 */
20 #define NVE4_HW_SM_QUERY(i) (PIPE_QUERY_DRIVER_SPECIFIC + (i))
21 #define NVE4_HW_SM_QUERY_LAST NVE4_HW_SM_QUERY(NVE4_HW_SM_QUERY_COUNT - 1)
22 enum nve4_hw_sm_queries
23 {
24 NVE4_HW_SM_QUERY_ACTIVE_CYCLES = 0,
25 NVE4_HW_SM_QUERY_ACTIVE_WARPS,
26 NVE4_HW_SM_QUERY_ATOM_COUNT,
27 NVE4_HW_SM_QUERY_BRANCH,
28 NVE4_HW_SM_QUERY_DIVERGENT_BRANCH,
29 NVE4_HW_SM_QUERY_GLD_REQUEST,
30 NVE4_HW_SM_QUERY_GLD_MEM_DIV_REPLAY,
31 NVE4_HW_SM_QUERY_GST_TRANSACTIONS,
32 NVE4_HW_SM_QUERY_GST_MEM_DIV_REPLAY,
33 NVE4_HW_SM_QUERY_GRED_COUNT,
34 NVE4_HW_SM_QUERY_GST_REQUEST,
35 NVE4_HW_SM_QUERY_INST_EXECUTED,
36 NVE4_HW_SM_QUERY_INST_ISSUED,
37 NVE4_HW_SM_QUERY_INST_ISSUED1,
38 NVE4_HW_SM_QUERY_INST_ISSUED2,
39 NVE4_HW_SM_QUERY_L1_GLD_HIT,
40 NVE4_HW_SM_QUERY_L1_GLD_MISS,
41 NVE4_HW_SM_QUERY_L1_LOCAL_LD_HIT,
42 NVE4_HW_SM_QUERY_L1_LOCAL_LD_MISS,
43 NVE4_HW_SM_QUERY_L1_LOCAL_ST_HIT,
44 NVE4_HW_SM_QUERY_L1_LOCAL_ST_MISS,
45 NVE4_HW_SM_QUERY_L1_SHARED_LD_TRANSACTIONS,
46 NVE4_HW_SM_QUERY_L1_SHARED_ST_TRANSACTIONS,
47 NVE4_HW_SM_QUERY_LOCAL_LD,
48 NVE4_HW_SM_QUERY_LOCAL_LD_TRANSACTIONS,
49 NVE4_HW_SM_QUERY_LOCAL_ST,
50 NVE4_HW_SM_QUERY_LOCAL_ST_TRANSACTIONS,
51 NVE4_HW_SM_QUERY_PROF_TRIGGER_0,
52 NVE4_HW_SM_QUERY_PROF_TRIGGER_1,
53 NVE4_HW_SM_QUERY_PROF_TRIGGER_2,
54 NVE4_HW_SM_QUERY_PROF_TRIGGER_3,
55 NVE4_HW_SM_QUERY_PROF_TRIGGER_4,
56 NVE4_HW_SM_QUERY_PROF_TRIGGER_5,
57 NVE4_HW_SM_QUERY_PROF_TRIGGER_6,
58 NVE4_HW_SM_QUERY_PROF_TRIGGER_7,
59 NVE4_HW_SM_QUERY_SHARED_LD,
60 NVE4_HW_SM_QUERY_SHARED_LD_REPLAY,
61 NVE4_HW_SM_QUERY_SHARED_ST,
62 NVE4_HW_SM_QUERY_SHARED_ST_REPLAY,
63 NVE4_HW_SM_QUERY_SM_CTA_LAUNCHED,
64 NVE4_HW_SM_QUERY_THREADS_LAUNCHED,
65 NVE4_HW_SM_QUERY_UNCACHED_GLD_TRANSACTIONS,
66 NVE4_HW_SM_QUERY_WARPS_LAUNCHED,
67 NVE4_HW_SM_QUERY_METRIC_IPC,
68 NVE4_HW_SM_QUERY_METRIC_IPAC,
69 NVE4_HW_SM_QUERY_METRIC_IPEC,
70 NVE4_HW_SM_QUERY_METRIC_MP_OCCUPANCY,
71 NVE4_HW_SM_QUERY_METRIC_MP_EFFICIENCY,
72 NVE4_HW_SM_QUERY_METRIC_INST_REPLAY_OHEAD,
73 NVE4_HW_SM_QUERY_COUNT
74 };
75
76 #define NVC0_HW_SM_QUERY(i) (PIPE_QUERY_DRIVER_SPECIFIC + 2048 + (i))
77 #define NVC0_HW_SM_QUERY_LAST NVC0_HW_SM_QUERY(NVC0_HW_SM_QUERY_COUNT - 1)
78 enum nvc0_hw_sm_queries
79 {
80 NVC0_HW_SM_QUERY_ACTIVE_CYCLES = 0,
81 NVC0_HW_SM_QUERY_ACTIVE_WARPS,
82 NVC0_HW_SM_QUERY_ATOM_COUNT,
83 NVC0_HW_SM_QUERY_BRANCH,
84 NVC0_HW_SM_QUERY_DIVERGENT_BRANCH,
85 NVC0_HW_SM_QUERY_GLD_REQUEST,
86 NVC0_HW_SM_QUERY_GRED_COUNT,
87 NVC0_HW_SM_QUERY_GST_REQUEST,
88 NVC0_HW_SM_QUERY_INST_EXECUTED,
89 NVC0_HW_SM_QUERY_INST_ISSUED1_0,
90 NVC0_HW_SM_QUERY_INST_ISSUED1_1,
91 NVC0_HW_SM_QUERY_INST_ISSUED2_0,
92 NVC0_HW_SM_QUERY_INST_ISSUED2_1,
93 NVC0_HW_SM_QUERY_LOCAL_LD,
94 NVC0_HW_SM_QUERY_LOCAL_ST,
95 NVC0_HW_SM_QUERY_PROF_TRIGGER_0,
96 NVC0_HW_SM_QUERY_PROF_TRIGGER_1,
97 NVC0_HW_SM_QUERY_PROF_TRIGGER_2,
98 NVC0_HW_SM_QUERY_PROF_TRIGGER_3,
99 NVC0_HW_SM_QUERY_PROF_TRIGGER_4,
100 NVC0_HW_SM_QUERY_PROF_TRIGGER_5,
101 NVC0_HW_SM_QUERY_PROF_TRIGGER_6,
102 NVC0_HW_SM_QUERY_PROF_TRIGGER_7,
103 NVC0_HW_SM_QUERY_SHARED_LD,
104 NVC0_HW_SM_QUERY_SHARED_ST,
105 NVC0_HW_SM_QUERY_THREADS_LAUNCHED,
106 NVC0_HW_SM_QUERY_TH_INST_EXECUTED_0,
107 NVC0_HW_SM_QUERY_TH_INST_EXECUTED_1,
108 NVC0_HW_SM_QUERY_TH_INST_EXECUTED_2,
109 NVC0_HW_SM_QUERY_TH_INST_EXECUTED_3,
110 NVC0_HW_SM_QUERY_WARPS_LAUNCHED,
111 NVC0_HW_SM_QUERY_COUNT
112 };
113
114 struct nvc0_hw_query *
115 nvc0_hw_sm_create_query(struct nvc0_context *, unsigned);
116
117 #endif