2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
30 #include "nouveau_vp3_video.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
35 #include "nvc0/nvc0_graph_macros.h"
37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
42 nvc0_screen_is_format_supported(struct pipe_screen
*pscreen
,
43 enum pipe_format format
,
44 enum pipe_texture_target target
,
45 unsigned sample_count
,
50 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
53 if (!util_format_is_supported(format
, bindings
))
56 if ((bindings
& PIPE_BIND_SAMPLER_VIEW
) && (target
!= PIPE_BUFFER
))
57 if (util_format_get_blocksizebits(format
) == 3 * 32)
60 /* transfers & shared are always supported */
61 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
62 PIPE_BIND_TRANSFER_WRITE
|
65 return (nvc0_format_table
[format
].usage
& bindings
) == bindings
;
69 nvc0_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
71 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
78 return (class_3d
>= NVE4_3D_CLASS
) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
81 case PIPE_CAP_MIN_TEXEL_OFFSET
:
83 case PIPE_CAP_MAX_TEXEL_OFFSET
:
85 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
87 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
89 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
90 case PIPE_CAP_TEXTURE_SWIZZLE
:
91 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
92 case PIPE_CAP_NPOT_TEXTURES
:
93 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
94 case PIPE_CAP_ANISOTROPIC_FILTER
:
95 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
96 case PIPE_CAP_CUBE_MAP_ARRAY
:
97 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
98 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
100 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
102 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
103 return (class_3d
>= NVE4_3D_CLASS
) ? 1 : 0;
104 case PIPE_CAP_TWO_SIDED_STENCIL
:
105 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
106 case PIPE_CAP_POINT_SPRITE
:
107 case PIPE_CAP_TGSI_TEXCOORD
:
111 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
113 case PIPE_CAP_MAX_RENDER_TARGETS
:
115 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
117 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
118 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
119 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
121 case PIPE_CAP_QUERY_TIMESTAMP
:
122 case PIPE_CAP_QUERY_TIME_ELAPSED
:
123 case PIPE_CAP_OCCLUSION_QUERY
:
124 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
125 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
127 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
129 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
130 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
132 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
133 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
135 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
136 case PIPE_CAP_INDEP_BLEND_ENABLE
:
137 case PIPE_CAP_INDEP_BLEND_FUNC
:
139 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
140 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
142 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
143 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
145 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
147 case PIPE_CAP_PRIMITIVE_RESTART
:
148 case PIPE_CAP_TGSI_INSTANCEID
:
149 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
150 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
151 case PIPE_CAP_CONDITIONAL_RENDER
:
152 case PIPE_CAP_TEXTURE_BARRIER
:
153 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
154 case PIPE_CAP_START_INSTANCE
:
156 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
157 return 0; /* state trackers will know better */
158 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
159 case PIPE_CAP_USER_INDEX_BUFFERS
:
160 case PIPE_CAP_USER_VERTEX_BUFFERS
:
162 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
164 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
165 return 1; /* 256 for binding as RT, but that's not possible in GL */
166 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
167 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
168 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
169 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
170 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
172 case PIPE_CAP_COMPUTE
:
173 return (class_3d
>= NVE4_3D_CLASS
) ? 1 : 0;
174 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
176 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
177 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
178 case PIPE_CAP_ENDIANNESS
:
179 return PIPE_ENDIAN_LITTLE
;
180 case PIPE_CAP_TGSI_VS_LAYER
:
181 case PIPE_CAP_TEXTURE_GATHER_SM5
:
182 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
183 case PIPE_CAP_FAKE_SW_MSAA
:
184 case PIPE_CAP_SAMPLE_SHADING
:
186 case PIPE_CAP_MAX_VIEWPORTS
:
188 case PIPE_CAP_TEXTURE_QUERY_LOD
:
190 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
193 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
199 nvc0_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
200 enum pipe_shader_cap param
)
202 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
205 case PIPE_SHADER_VERTEX
:
207 case PIPE_SHADER_TESSELLATION_CONTROL:
208 case PIPE_SHADER_TESSELLATION_EVALUATION:
210 case PIPE_SHADER_GEOMETRY
:
211 case PIPE_SHADER_FRAGMENT
:
213 case PIPE_SHADER_COMPUTE
:
214 if (class_3d
< NVE4_3D_CLASS
)
222 case PIPE_SHADER_CAP_PREFERRED_IR
:
223 return PIPE_SHADER_IR_TGSI
;
224 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
225 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
226 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
227 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
229 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
231 case PIPE_SHADER_CAP_MAX_INPUTS
:
232 if (shader
== PIPE_SHADER_VERTEX
)
234 /* NOTE: These only count our slots for GENERIC varyings.
235 * The address space may be larger, but the actual hard limit seems to be
236 * less than what the address space layout permits, so don't add TEXCOORD,
239 if (shader
== PIPE_SHADER_FRAGMENT
)
241 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
242 * and excludes 0x60 per-patch inputs.
245 case PIPE_SHADER_CAP_MAX_CONSTS
:
247 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
248 if (shader
== PIPE_SHADER_COMPUTE
&& class_3d
>= NVE4_3D_CLASS
)
249 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE
;
250 return NVC0_MAX_PIPE_CONSTBUFS
;
251 case PIPE_SHADER_CAP_MAX_ADDRS
:
253 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
254 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
255 return shader
!= PIPE_SHADER_FRAGMENT
;
256 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
257 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
259 case PIPE_SHADER_CAP_MAX_PREDS
:
261 case PIPE_SHADER_CAP_MAX_TEMPS
:
262 return NVC0_CAP_MAX_PROGRAM_TEMPS
;
263 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
265 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
267 case PIPE_SHADER_CAP_SUBROUTINES
:
269 case PIPE_SHADER_CAP_INTEGERS
:
271 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
272 return 16; /* would be 32 in linked (OpenGL-style) mode */
273 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
274 return 16; /* XXX not sure if more are really safe */
276 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
282 nvc0_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
285 case PIPE_CAPF_MAX_LINE_WIDTH
:
286 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
288 case PIPE_CAPF_MAX_POINT_WIDTH
:
290 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
292 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
294 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
297 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
303 nvc0_screen_get_compute_param(struct pipe_screen
*pscreen
,
304 enum pipe_compute_cap param
, void *data
)
306 uint64_t *data64
= (uint64_t *)data
;
307 const uint16_t obj_class
= nvc0_screen(pscreen
)->compute
->oclass
;
310 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
313 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
314 data64
[0] = (obj_class
>= NVE4_COMPUTE_CLASS
) ? 0x7fffffff : 65535;
318 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
323 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
326 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g[] */
327 data64
[0] = (uint64_t)1 << 40;
329 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
330 data64
[0] = 48 << 10;
332 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
333 data64
[0] = 512 << 10;
335 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
344 nvc0_screen_destroy(struct pipe_screen
*pscreen
)
346 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
348 if (!nouveau_drm_screen_unref(&screen
->base
))
351 if (screen
->base
.fence
.current
) {
352 struct nouveau_fence
*current
= NULL
;
354 /* nouveau_fence_wait will create a new current fence, so wait on the
355 * _current_ one, and remove both.
357 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
358 nouveau_fence_wait(current
);
359 nouveau_fence_ref(NULL
, ¤t
);
360 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
362 if (screen
->base
.pushbuf
)
363 screen
->base
.pushbuf
->user_priv
= NULL
;
366 nvc0_blitter_destroy(screen
);
367 if (screen
->pm
.prog
) {
368 screen
->pm
.prog
->code
= NULL
; /* hardcoded, don't FREE */
369 nvc0_program_destroy(NULL
, screen
->pm
.prog
);
372 nouveau_bo_ref(NULL
, &screen
->text
);
373 nouveau_bo_ref(NULL
, &screen
->uniform_bo
);
374 nouveau_bo_ref(NULL
, &screen
->tls
);
375 nouveau_bo_ref(NULL
, &screen
->txc
);
376 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
377 nouveau_bo_ref(NULL
, &screen
->poly_cache
);
378 nouveau_bo_ref(NULL
, &screen
->parm
);
380 nouveau_heap_destroy(&screen
->lib_code
);
381 nouveau_heap_destroy(&screen
->text_heap
);
383 FREE(screen
->tic
.entries
);
385 nouveau_mm_destroy(screen
->mm_VRAM_fe0
);
387 nouveau_object_del(&screen
->eng3d
);
388 nouveau_object_del(&screen
->eng2d
);
389 nouveau_object_del(&screen
->m2mf
);
390 nouveau_object_del(&screen
->compute
);
391 nouveau_object_del(&screen
->nvsw
);
393 nouveau_screen_fini(&screen
->base
);
399 nvc0_graph_set_macro(struct nvc0_screen
*screen
, uint32_t m
, unsigned pos
,
400 unsigned size
, const uint32_t *data
)
402 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
406 BEGIN_NVC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_ID
), 2);
407 PUSH_DATA (push
, (m
- 0x3800) / 8);
408 PUSH_DATA (push
, pos
);
409 BEGIN_1IC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS
), size
+ 1);
410 PUSH_DATA (push
, pos
);
411 PUSH_DATAp(push
, data
, size
);
417 nvc0_magic_3d_init(struct nouveau_pushbuf
*push
, uint16_t obj_class
)
419 BEGIN_NVC0(push
, SUBC_3D(0x10cc), 1);
420 PUSH_DATA (push
, 0xff);
421 BEGIN_NVC0(push
, SUBC_3D(0x10e0), 2);
422 PUSH_DATA (push
, 0xff);
423 PUSH_DATA (push
, 0xff);
424 BEGIN_NVC0(push
, SUBC_3D(0x10ec), 2);
425 PUSH_DATA (push
, 0xff);
426 PUSH_DATA (push
, 0xff);
427 BEGIN_NVC0(push
, SUBC_3D(0x074c), 1);
428 PUSH_DATA (push
, 0x3f);
430 BEGIN_NVC0(push
, SUBC_3D(0x16a8), 1);
431 PUSH_DATA (push
, (3 << 16) | 3);
432 BEGIN_NVC0(push
, SUBC_3D(0x1794), 1);
433 PUSH_DATA (push
, (2 << 16) | 2);
434 BEGIN_NVC0(push
, SUBC_3D(0x0de8), 1);
437 BEGIN_NVC0(push
, SUBC_3D(0x12ac), 1);
439 BEGIN_NVC0(push
, SUBC_3D(0x0218), 1);
440 PUSH_DATA (push
, 0x10);
441 BEGIN_NVC0(push
, SUBC_3D(0x10fc), 1);
442 PUSH_DATA (push
, 0x10);
443 BEGIN_NVC0(push
, SUBC_3D(0x1290), 1);
444 PUSH_DATA (push
, 0x10);
445 BEGIN_NVC0(push
, SUBC_3D(0x12d8), 2);
446 PUSH_DATA (push
, 0x10);
447 PUSH_DATA (push
, 0x10);
448 BEGIN_NVC0(push
, SUBC_3D(0x1140), 1);
449 PUSH_DATA (push
, 0x10);
450 BEGIN_NVC0(push
, SUBC_3D(0x1610), 1);
451 PUSH_DATA (push
, 0xe);
453 BEGIN_NVC0(push
, SUBC_3D(0x164c), 1);
454 PUSH_DATA (push
, 1 << 12);
455 BEGIN_NVC0(push
, SUBC_3D(0x030c), 1);
457 BEGIN_NVC0(push
, SUBC_3D(0x0300), 1);
460 BEGIN_NVC0(push
, SUBC_3D(0x02d0), 1);
461 PUSH_DATA (push
, 0x3fffff);
462 BEGIN_NVC0(push
, SUBC_3D(0x0fdc), 1);
464 BEGIN_NVC0(push
, SUBC_3D(0x19c0), 1);
466 BEGIN_NVC0(push
, SUBC_3D(0x075c), 1);
469 if (obj_class
>= NVE4_3D_CLASS
) {
470 BEGIN_NVC0(push
, SUBC_3D(0x07fc), 1);
474 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
475 * are supposed to do */
479 nvc0_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
481 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
482 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
484 /* we need to do it after possible flush in MARK_RING */
485 *sequence
= ++screen
->base
.fence
.sequence
;
487 BEGIN_NVC0(push
, NVC0_3D(QUERY_ADDRESS_HIGH
), 4);
488 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
489 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
490 PUSH_DATA (push
, *sequence
);
491 PUSH_DATA (push
, NVC0_3D_QUERY_GET_FENCE
| NVC0_3D_QUERY_GET_SHORT
|
492 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT
));
496 nvc0_screen_fence_update(struct pipe_screen
*pscreen
)
498 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
499 return screen
->fence
.map
[0];
503 nvc0_screen_init_compute(struct nvc0_screen
*screen
)
505 screen
->base
.base
.get_compute_param
= nvc0_screen_get_compute_param
;
507 switch (screen
->base
.device
->chipset
& ~0xf) {
510 /* Using COMPUTE has weird effects on 3D state, we need to
511 * investigate this further before enabling it by default.
513 if (debug_get_bool_option("NVC0_COMPUTE", FALSE
))
514 return nvc0_screen_compute_setup(screen
, screen
->base
.pushbuf
);
519 return nve4_screen_compute_setup(screen
, screen
->base
.pushbuf
);
526 nvc0_screen_resize_tls_area(struct nvc0_screen
*screen
,
527 uint32_t lpos
, uint32_t lneg
, uint32_t cstack
)
529 struct nouveau_bo
*bo
= NULL
;
531 uint64_t size
= (lpos
+ lneg
) * 32 + cstack
;
533 if (size
>= (1 << 20)) {
534 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64
"\n", size
);
538 size
*= (screen
->base
.device
->chipset
>= 0xe0) ? 64 : 48; /* max warps */
539 size
= align(size
, 0x8000);
540 size
*= screen
->mp_count
;
542 size
= align(size
, 1 << 17);
544 ret
= nouveau_bo_new(screen
->base
.device
, NOUVEAU_BO_VRAM
, 1 << 17, size
,
547 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64
"\n", size
);
550 nouveau_bo_ref(NULL
, &screen
->tls
);
555 #define FAIL_SCREEN_INIT(str, err) \
557 NOUVEAU_ERR(str, err); \
558 nvc0_screen_destroy(pscreen); \
563 nvc0_screen_create(struct nouveau_device
*dev
)
565 struct nvc0_screen
*screen
;
566 struct pipe_screen
*pscreen
;
567 struct nouveau_object
*chan
;
568 struct nouveau_pushbuf
*push
;
573 union nouveau_bo_config mm_config
;
575 switch (dev
->chipset
& ~0xf) {
586 screen
= CALLOC_STRUCT(nvc0_screen
);
589 pscreen
= &screen
->base
.base
;
591 ret
= nouveau_screen_init(&screen
->base
, dev
);
593 nvc0_screen_destroy(pscreen
);
596 chan
= screen
->base
.channel
;
597 push
= screen
->base
.pushbuf
;
598 push
->user_priv
= screen
;
601 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
602 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
603 screen
->base
.sysmem_bindings
|=
604 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
606 pscreen
->destroy
= nvc0_screen_destroy
;
607 pscreen
->context_create
= nvc0_create
;
608 pscreen
->is_format_supported
= nvc0_screen_is_format_supported
;
609 pscreen
->get_param
= nvc0_screen_get_param
;
610 pscreen
->get_shader_param
= nvc0_screen_get_shader_param
;
611 pscreen
->get_paramf
= nvc0_screen_get_paramf
;
612 pscreen
->get_driver_query_info
= nvc0_screen_get_driver_query_info
;
614 nvc0_screen_init_resource_functions(pscreen
);
616 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
617 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
619 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096, NULL
,
623 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
624 screen
->fence
.map
= screen
->fence
.bo
->map
;
625 screen
->base
.fence
.emit
= nvc0_screen_fence_emit
;
626 screen
->base
.fence
.update
= nvc0_screen_fence_update
;
629 ret
= nouveau_object_new(chan
,
630 (dev
->chipset
< 0xe0) ? 0x1f906e : 0x906e, 0x906e,
631 NULL
, 0, &screen
->nvsw
);
633 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret
);
636 switch (dev
->chipset
& ~0xf) {
639 obj_class
= NVF0_P2MF_CLASS
;
642 obj_class
= NVE4_P2MF_CLASS
;
645 obj_class
= NVC0_M2MF_CLASS
;
648 ret
= nouveau_object_new(chan
, 0xbeef323f, obj_class
, NULL
, 0,
651 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
653 BEGIN_NVC0(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
654 PUSH_DATA (push
, screen
->m2mf
->oclass
);
655 if (screen
->m2mf
->oclass
== NVE4_P2MF_CLASS
) {
656 BEGIN_NVC0(push
, SUBC_COPY(NV01_SUBCHAN_OBJECT
), 1);
657 PUSH_DATA (push
, 0xa0b5);
660 ret
= nouveau_object_new(chan
, 0xbeef902d, NVC0_2D_CLASS
, NULL
, 0,
663 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
665 BEGIN_NVC0(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
666 PUSH_DATA (push
, screen
->eng2d
->oclass
);
667 BEGIN_NVC0(push
, NVC0_2D(SINGLE_GPC
), 1);
669 BEGIN_NVC0(push
, NVC0_2D(OPERATION
), 1);
670 PUSH_DATA (push
, NVC0_2D_OPERATION_SRCCOPY
);
671 BEGIN_NVC0(push
, NVC0_2D(CLIP_ENABLE
), 1);
673 BEGIN_NVC0(push
, NVC0_2D(COLOR_KEY_ENABLE
), 1);
675 BEGIN_NVC0(push
, SUBC_2D(0x0884), 1);
676 PUSH_DATA (push
, 0x3f);
677 BEGIN_NVC0(push
, SUBC_2D(0x0888), 1);
680 BEGIN_NVC0(push
, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH
), 2);
681 PUSH_DATAh(push
, screen
->fence
.bo
->offset
+ 16);
682 PUSH_DATA (push
, screen
->fence
.bo
->offset
+ 16);
684 switch (dev
->chipset
& ~0xf) {
687 obj_class
= NVF0_3D_CLASS
;
690 obj_class
= NVE4_3D_CLASS
;
693 obj_class
= NVC8_3D_CLASS
;
697 switch (dev
->chipset
) {
699 obj_class
= NVC8_3D_CLASS
;
702 obj_class
= NVC1_3D_CLASS
;
705 obj_class
= NVC0_3D_CLASS
;
710 ret
= nouveau_object_new(chan
, 0xbeef003d, obj_class
, NULL
, 0,
713 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
714 screen
->base
.class_3d
= obj_class
;
716 BEGIN_NVC0(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
717 PUSH_DATA (push
, screen
->eng3d
->oclass
);
719 BEGIN_NVC0(push
, NVC0_3D(COND_MODE
), 1);
720 PUSH_DATA (push
, NVC0_3D_COND_MODE_ALWAYS
);
722 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE
)) {
723 /* kill shaders after about 1 second (at 100 MHz) */
724 BEGIN_NVC0(push
, NVC0_3D(WATCHDOG_TIMER
), 1);
725 PUSH_DATA (push
, 0x17);
728 IMMED_NVC0(push
, NVC0_3D(ZETA_COMP_ENABLE
), dev
->drm_version
>= 0x01000101);
729 BEGIN_NVC0(push
, NVC0_3D(RT_COMP_ENABLE(0)), 8);
730 for (i
= 0; i
< 8; ++i
)
731 PUSH_DATA(push
, dev
->drm_version
>= 0x01000101);
733 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
736 BEGIN_NVC0(push
, NVC0_3D(CSAA_ENABLE
), 1);
738 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_ENABLE
), 1);
740 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 1);
741 PUSH_DATA (push
, NVC0_3D_MULTISAMPLE_MODE_MS1
);
742 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_CTRL
), 1);
744 BEGIN_NVC0(push
, NVC0_3D(LINE_WIDTH_SEPARATE
), 1);
746 BEGIN_NVC0(push
, NVC0_3D(LINE_LAST_PIXEL
), 1);
748 BEGIN_NVC0(push
, NVC0_3D(BLEND_SEPARATE_ALPHA
), 1);
750 BEGIN_NVC0(push
, NVC0_3D(BLEND_ENABLE_COMMON
), 1);
752 if (screen
->eng3d
->oclass
< NVE4_3D_CLASS
) {
753 BEGIN_NVC0(push
, NVC0_3D(TEX_MISC
), 1);
754 PUSH_DATA (push
, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
756 BEGIN_NVC0(push
, NVE4_3D(TEX_CB_INDEX
), 1);
757 PUSH_DATA (push
, 15);
759 BEGIN_NVC0(push
, NVC0_3D(CALL_LIMIT_LOG
), 1);
760 PUSH_DATA (push
, 8); /* 128 */
761 BEGIN_NVC0(push
, NVC0_3D(ZCULL_STATCTRS_ENABLE
), 1);
763 if (screen
->eng3d
->oclass
>= NVC1_3D_CLASS
) {
764 BEGIN_NVC0(push
, NVC0_3D(CACHE_SPLIT
), 1);
765 PUSH_DATA (push
, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1
);
768 nvc0_magic_3d_init(push
, screen
->eng3d
->oclass
);
770 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 20, NULL
,
775 /* XXX: getting a page fault at the end of the code buffer every few
776 * launches, don't use the last 256 bytes to work around them - prefetch ?
778 nouveau_heap_init(&screen
->text_heap
, 0, (1 << 20) - 0x100);
780 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 12, 6 << 16, NULL
,
781 &screen
->uniform_bo
);
785 PUSH_REFN (push
, screen
->uniform_bo
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
787 for (i
= 0; i
< 5; ++i
) {
788 /* TIC and TSC entries for each unit (nve4+ only) */
789 /* auxiliary constants (6 user clip planes, base instance id) */
790 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
791 PUSH_DATA (push
, 512);
792 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
793 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
794 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(i
)), 1);
795 PUSH_DATA (push
, (15 << 4) | 1);
796 if (screen
->eng3d
->oclass
>= NVE4_3D_CLASS
) {
798 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 9);
800 for (j
= 0; j
< 8; ++j
)
803 BEGIN_NVC0(push
, NVC0_3D(TEX_LIMITS(i
)), 1);
804 PUSH_DATA (push
, 0x54);
807 BEGIN_NVC0(push
, NVC0_3D(LINKED_TSC
), 1);
810 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
811 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
812 PUSH_DATA (push
, 256);
813 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
814 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
815 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 5);
817 PUSH_DATAf(push
, 0.0f
);
818 PUSH_DATAf(push
, 0.0f
);
819 PUSH_DATAf(push
, 0.0f
);
820 PUSH_DATAf(push
, 0.0f
);
821 BEGIN_NVC0(push
, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
822 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
823 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
825 if (dev
->drm_version
>= 0x01000101) {
826 ret
= nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
828 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
832 if (dev
->chipset
>= 0xe0 && dev
->chipset
< 0xf0)
833 value
= (8 << 8) | 4;
835 value
= (16 << 8) | 4;
837 screen
->mp_count
= value
>> 8;
838 screen
->mp_count_compute
= screen
->mp_count
;
840 nvc0_screen_resize_tls_area(screen
, 128 * 16, 0, 0x200);
842 BEGIN_NVC0(push
, NVC0_3D(CODE_ADDRESS_HIGH
), 2);
843 PUSH_DATAh(push
, screen
->text
->offset
);
844 PUSH_DATA (push
, screen
->text
->offset
);
845 BEGIN_NVC0(push
, NVC0_3D(TEMP_ADDRESS_HIGH
), 4);
846 PUSH_DATAh(push
, screen
->tls
->offset
);
847 PUSH_DATA (push
, screen
->tls
->offset
);
848 PUSH_DATA (push
, screen
->tls
->size
>> 32);
849 PUSH_DATA (push
, screen
->tls
->size
);
850 BEGIN_NVC0(push
, NVC0_3D(WARP_TEMP_ALLOC
), 1);
852 BEGIN_NVC0(push
, NVC0_3D(LOCAL_BASE
), 1);
855 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 20, NULL
,
856 &screen
->poly_cache
);
860 BEGIN_NVC0(push
, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH
), 3);
861 PUSH_DATAh(push
, screen
->poly_cache
->offset
);
862 PUSH_DATA (push
, screen
->poly_cache
->offset
);
865 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 17, NULL
,
870 BEGIN_NVC0(push
, NVC0_3D(TIC_ADDRESS_HIGH
), 3);
871 PUSH_DATAh(push
, screen
->txc
->offset
);
872 PUSH_DATA (push
, screen
->txc
->offset
);
873 PUSH_DATA (push
, NVC0_TIC_MAX_ENTRIES
- 1);
875 BEGIN_NVC0(push
, NVC0_3D(TSC_ADDRESS_HIGH
), 3);
876 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
877 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
878 PUSH_DATA (push
, NVC0_TSC_MAX_ENTRIES
- 1);
880 BEGIN_NVC0(push
, NVC0_3D(SCREEN_Y_CONTROL
), 1);
882 BEGIN_NVC0(push
, NVC0_3D(WINDOW_OFFSET_X
), 2);
885 BEGIN_NVC0(push
, NVC0_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
886 PUSH_DATA (push
, 0x3f);
888 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_MODE
), 1);
889 PUSH_DATA (push
, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
890 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
891 for (i
= 0; i
< 8 * 2; ++i
)
893 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_EN
), 1);
895 BEGIN_NVC0(push
, NVC0_3D(CLIPID_ENABLE
), 1);
898 /* neither scissors, viewport nor stencil mask should affect clears */
899 BEGIN_NVC0(push
, NVC0_3D(CLEAR_FLAGS
), 1);
902 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 1);
904 BEGIN_NVC0(push
, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
905 PUSH_DATAf(push
, 0.0f
);
906 PUSH_DATAf(push
, 1.0f
);
907 BEGIN_NVC0(push
, NVC0_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
908 PUSH_DATA (push
, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
);
910 /* We use scissors instead of exact view volume clipping,
911 * so they're always enabled.
913 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_ENABLE(0)), 3);
915 PUSH_DATA (push
, 8192 << 16);
916 PUSH_DATA (push
, 8192 << 16);
918 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
921 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE
, nvc0_9097_per_instance_bf
);
922 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES
, nvc0_9097_blend_enables
);
923 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT
, nvc0_9097_vertex_array_select
);
924 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT
, nvc0_9097_tep_select
);
925 MK_MACRO(NVC0_3D_MACRO_GP_SELECT
, nvc0_9097_gp_select
);
926 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT
, nvc0_9097_poly_mode_front
);
927 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK
, nvc0_9097_poly_mode_back
);
929 BEGIN_NVC0(push
, NVC0_3D(RASTERIZE_ENABLE
), 1);
931 BEGIN_NVC0(push
, NVC0_3D(RT_SEPARATE_FRAG_DATA
), 1);
933 BEGIN_NVC0(push
, NVC0_3D(MACRO_GP_SELECT
), 1);
934 PUSH_DATA (push
, 0x40);
935 BEGIN_NVC0(push
, NVC0_3D(LAYER
), 1);
937 BEGIN_NVC0(push
, NVC0_3D(MACRO_TEP_SELECT
), 1);
938 PUSH_DATA (push
, 0x30);
939 BEGIN_NVC0(push
, NVC0_3D(PATCH_VERTICES
), 1);
941 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(2)), 1);
942 PUSH_DATA (push
, 0x20);
943 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(0)), 1);
944 PUSH_DATA (push
, 0x00);
946 BEGIN_NVC0(push
, NVC0_3D(POINT_COORD_REPLACE
), 1);
948 BEGIN_NVC0(push
, NVC0_3D(POINT_RASTER_RULES
), 1);
949 PUSH_DATA (push
, NVC0_3D_POINT_RASTER_RULES_OGL
);
951 IMMED_NVC0(push
, NVC0_3D(EDGEFLAG
), 1);
953 if (nvc0_screen_init_compute(screen
))
958 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
959 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
961 mm_config
.nvc0
.tile_mode
= 0;
962 mm_config
.nvc0
.memtype
= 0xfe0;
963 screen
->mm_VRAM_fe0
= nouveau_mm_create(dev
, NOUVEAU_BO_VRAM
, &mm_config
);
965 if (!nvc0_blitter_create(screen
))
968 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);
973 nvc0_screen_destroy(pscreen
);
978 nvc0_screen_tic_alloc(struct nvc0_screen
*screen
, void *entry
)
980 int i
= screen
->tic
.next
;
982 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
983 i
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
985 screen
->tic
.next
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
987 if (screen
->tic
.entries
[i
])
988 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
990 screen
->tic
.entries
[i
] = entry
;
995 nvc0_screen_tsc_alloc(struct nvc0_screen
*screen
, void *entry
)
997 int i
= screen
->tsc
.next
;
999 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
1000 i
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1002 screen
->tsc
.next
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1004 if (screen
->tsc
.entries
[i
])
1005 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1007 screen
->tsc
.entries
[i
] = entry
;