2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
30 #include "nouveau_vp3_video.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
35 #include "nvc0/mme/com9097.mme.h"
37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
42 nvc0_screen_is_format_supported(struct pipe_screen
*pscreen
,
43 enum pipe_format format
,
44 enum pipe_texture_target target
,
45 unsigned sample_count
,
50 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
53 if (!util_format_is_supported(format
, bindings
))
56 if ((bindings
& PIPE_BIND_SAMPLER_VIEW
) && (target
!= PIPE_BUFFER
))
57 if (util_format_get_blocksizebits(format
) == 3 * 32)
60 /* transfers & shared are always supported */
61 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
62 PIPE_BIND_TRANSFER_WRITE
|
65 return (nvc0_format_table
[format
].usage
& bindings
) == bindings
;
69 nvc0_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
71 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
78 return (class_3d
>= NVE4_3D_CLASS
) ? 13 : 12;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
81 case PIPE_CAP_MIN_TEXEL_OFFSET
:
83 case PIPE_CAP_MAX_TEXEL_OFFSET
:
85 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
87 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
89 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
90 case PIPE_CAP_TEXTURE_SWIZZLE
:
91 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
92 case PIPE_CAP_NPOT_TEXTURES
:
93 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
94 case PIPE_CAP_ANISOTROPIC_FILTER
:
95 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
96 case PIPE_CAP_CUBE_MAP_ARRAY
:
97 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
98 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
100 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
102 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
103 return (class_3d
>= NVE4_3D_CLASS
) ? 1 : 0;
104 case PIPE_CAP_TWO_SIDED_STENCIL
:
105 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
106 case PIPE_CAP_POINT_SPRITE
:
107 case PIPE_CAP_TGSI_TEXCOORD
:
111 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
113 case PIPE_CAP_MAX_RENDER_TARGETS
:
115 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
117 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
118 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
119 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
121 case PIPE_CAP_QUERY_TIMESTAMP
:
122 case PIPE_CAP_QUERY_TIME_ELAPSED
:
123 case PIPE_CAP_OCCLUSION_QUERY
:
124 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
125 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
127 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
129 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
130 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
132 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
133 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
135 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
136 case PIPE_CAP_INDEP_BLEND_ENABLE
:
137 case PIPE_CAP_INDEP_BLEND_FUNC
:
139 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
140 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
142 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
143 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
145 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
147 case PIPE_CAP_PRIMITIVE_RESTART
:
148 case PIPE_CAP_TGSI_INSTANCEID
:
149 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
150 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
151 case PIPE_CAP_CONDITIONAL_RENDER
:
152 case PIPE_CAP_TEXTURE_BARRIER
:
153 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
154 case PIPE_CAP_START_INSTANCE
:
155 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
157 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
158 return 0; /* state trackers will know better */
159 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
160 case PIPE_CAP_USER_INDEX_BUFFERS
:
161 case PIPE_CAP_USER_VERTEX_BUFFERS
:
163 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
165 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
166 return 1; /* 256 for binding as RT, but that's not possible in GL */
167 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
168 return NOUVEAU_MIN_BUFFER_MAP_ALIGN
;
169 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
170 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
171 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
173 case PIPE_CAP_COMPUTE
:
174 return (class_3d
== NVE4_3D_CLASS
) ? 1 : 0;
175 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
177 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
178 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50
;
179 case PIPE_CAP_ENDIANNESS
:
180 return PIPE_ENDIAN_LITTLE
;
181 case PIPE_CAP_TGSI_VS_LAYER
:
182 case PIPE_CAP_TEXTURE_GATHER_SM5
:
183 case PIPE_CAP_FAKE_SW_MSAA
:
185 case PIPE_CAP_MAX_VIEWPORTS
:
187 case PIPE_CAP_TEXTURE_QUERY_LOD
:
188 case PIPE_CAP_SAMPLE_SHADING
:
189 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
191 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
193 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
196 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
202 nvc0_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
203 enum pipe_shader_cap param
)
205 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
208 case PIPE_SHADER_VERTEX
:
210 case PIPE_SHADER_TESSELLATION_CONTROL:
211 case PIPE_SHADER_TESSELLATION_EVALUATION:
213 case PIPE_SHADER_GEOMETRY
:
214 case PIPE_SHADER_FRAGMENT
:
216 case PIPE_SHADER_COMPUTE
:
217 if (class_3d
!= NVE4_3D_CLASS
)
225 case PIPE_SHADER_CAP_PREFERRED_IR
:
226 return PIPE_SHADER_IR_TGSI
;
227 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
228 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
229 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
230 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
232 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
234 case PIPE_SHADER_CAP_MAX_INPUTS
:
235 if (shader
== PIPE_SHADER_VERTEX
)
237 /* NOTE: These only count our slots for GENERIC varyings.
238 * The address space may be larger, but the actual hard limit seems to be
239 * less than what the address space layout permits, so don't add TEXCOORD,
242 if (shader
== PIPE_SHADER_FRAGMENT
)
244 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
245 * and excludes 0x60 per-patch inputs.
248 case PIPE_SHADER_CAP_MAX_CONSTS
:
250 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
251 if (shader
== PIPE_SHADER_COMPUTE
&& class_3d
>= NVE4_3D_CLASS
)
252 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE
;
253 return NVC0_MAX_PIPE_CONSTBUFS
;
254 case PIPE_SHADER_CAP_MAX_ADDRS
:
256 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
257 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
258 return shader
!= PIPE_SHADER_FRAGMENT
;
259 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
260 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
262 case PIPE_SHADER_CAP_MAX_PREDS
:
264 case PIPE_SHADER_CAP_MAX_TEMPS
:
265 return NVC0_CAP_MAX_PROGRAM_TEMPS
;
266 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
268 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
270 case PIPE_SHADER_CAP_SUBROUTINES
:
272 case PIPE_SHADER_CAP_INTEGERS
:
274 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
275 return 16; /* would be 32 in linked (OpenGL-style) mode */
276 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
277 return 16; /* XXX not sure if more are really safe */
279 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
285 nvc0_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
288 case PIPE_CAPF_MAX_LINE_WIDTH
:
289 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
291 case PIPE_CAPF_MAX_POINT_WIDTH
:
293 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
295 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
297 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
299 case PIPE_CAPF_GUARD_BAND_LEFT
:
300 case PIPE_CAPF_GUARD_BAND_TOP
:
302 case PIPE_CAPF_GUARD_BAND_RIGHT
:
303 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
304 return 0.0f
; /* that or infinity */
307 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param
);
312 nvc0_screen_get_compute_param(struct pipe_screen
*pscreen
,
313 enum pipe_compute_cap param
, void *data
)
315 uint64_t *data64
= (uint64_t *)data
;
316 const uint16_t obj_class
= nvc0_screen(pscreen
)->compute
->oclass
;
319 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
322 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
323 data64
[0] = (obj_class
>= NVE4_COMPUTE_CLASS
) ? 0x7fffffff : 65535;
327 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
332 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
335 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
: /* g[] */
336 data64
[0] = (uint64_t)1 << 40;
338 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
: /* s[] */
339 data64
[0] = 48 << 10;
341 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
: /* l[] */
342 data64
[0] = 512 << 10;
344 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
: /* c[], arbitrary limit */
353 nvc0_screen_destroy(struct pipe_screen
*pscreen
)
355 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
357 if (!nouveau_drm_screen_unref(&screen
->base
))
360 if (screen
->base
.fence
.current
) {
361 struct nouveau_fence
*current
= NULL
;
363 /* nouveau_fence_wait will create a new current fence, so wait on the
364 * _current_ one, and remove both.
366 nouveau_fence_ref(screen
->base
.fence
.current
, ¤t
);
367 nouveau_fence_wait(current
);
368 nouveau_fence_ref(NULL
, ¤t
);
369 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
371 if (screen
->base
.pushbuf
)
372 screen
->base
.pushbuf
->user_priv
= NULL
;
375 nvc0_blitter_destroy(screen
);
376 if (screen
->pm
.prog
) {
377 screen
->pm
.prog
->code
= NULL
; /* hardcoded, don't FREE */
378 nvc0_program_destroy(NULL
, screen
->pm
.prog
);
381 nouveau_bo_ref(NULL
, &screen
->text
);
382 nouveau_bo_ref(NULL
, &screen
->uniform_bo
);
383 nouveau_bo_ref(NULL
, &screen
->tls
);
384 nouveau_bo_ref(NULL
, &screen
->txc
);
385 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
386 nouveau_bo_ref(NULL
, &screen
->poly_cache
);
387 nouveau_bo_ref(NULL
, &screen
->parm
);
389 nouveau_heap_destroy(&screen
->lib_code
);
390 nouveau_heap_destroy(&screen
->text_heap
);
392 FREE(screen
->tic
.entries
);
394 nouveau_mm_destroy(screen
->mm_VRAM_fe0
);
396 nouveau_object_del(&screen
->eng3d
);
397 nouveau_object_del(&screen
->eng2d
);
398 nouveau_object_del(&screen
->m2mf
);
399 nouveau_object_del(&screen
->compute
);
400 nouveau_object_del(&screen
->nvsw
);
402 nouveau_screen_fini(&screen
->base
);
408 nvc0_graph_set_macro(struct nvc0_screen
*screen
, uint32_t m
, unsigned pos
,
409 unsigned size
, const uint32_t *data
)
411 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
415 BEGIN_NVC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_ID
), 2);
416 PUSH_DATA (push
, (m
- 0x3800) / 8);
417 PUSH_DATA (push
, pos
);
418 BEGIN_1IC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS
), size
+ 1);
419 PUSH_DATA (push
, pos
);
420 PUSH_DATAp(push
, data
, size
);
426 nvc0_magic_3d_init(struct nouveau_pushbuf
*push
, uint16_t obj_class
)
428 BEGIN_NVC0(push
, SUBC_3D(0x10cc), 1);
429 PUSH_DATA (push
, 0xff);
430 BEGIN_NVC0(push
, SUBC_3D(0x10e0), 2);
431 PUSH_DATA (push
, 0xff);
432 PUSH_DATA (push
, 0xff);
433 BEGIN_NVC0(push
, SUBC_3D(0x10ec), 2);
434 PUSH_DATA (push
, 0xff);
435 PUSH_DATA (push
, 0xff);
436 BEGIN_NVC0(push
, SUBC_3D(0x074c), 1);
437 PUSH_DATA (push
, 0x3f);
439 BEGIN_NVC0(push
, SUBC_3D(0x16a8), 1);
440 PUSH_DATA (push
, (3 << 16) | 3);
441 BEGIN_NVC0(push
, SUBC_3D(0x1794), 1);
442 PUSH_DATA (push
, (2 << 16) | 2);
443 BEGIN_NVC0(push
, SUBC_3D(0x0de8), 1);
446 if (obj_class
< GM107_3D_CLASS
) {
447 BEGIN_NVC0(push
, SUBC_3D(0x12ac), 1);
450 BEGIN_NVC0(push
, SUBC_3D(0x0218), 1);
451 PUSH_DATA (push
, 0x10);
452 BEGIN_NVC0(push
, SUBC_3D(0x10fc), 1);
453 PUSH_DATA (push
, 0x10);
454 BEGIN_NVC0(push
, SUBC_3D(0x1290), 1);
455 PUSH_DATA (push
, 0x10);
456 BEGIN_NVC0(push
, SUBC_3D(0x12d8), 2);
457 PUSH_DATA (push
, 0x10);
458 PUSH_DATA (push
, 0x10);
459 BEGIN_NVC0(push
, SUBC_3D(0x1140), 1);
460 PUSH_DATA (push
, 0x10);
461 BEGIN_NVC0(push
, SUBC_3D(0x1610), 1);
462 PUSH_DATA (push
, 0xe);
464 BEGIN_NVC0(push
, SUBC_3D(0x164c), 1);
465 PUSH_DATA (push
, 1 << 12);
466 BEGIN_NVC0(push
, SUBC_3D(0x030c), 1);
468 BEGIN_NVC0(push
, SUBC_3D(0x0300), 1);
471 BEGIN_NVC0(push
, SUBC_3D(0x02d0), 1);
472 PUSH_DATA (push
, 0x3fffff);
473 BEGIN_NVC0(push
, SUBC_3D(0x0fdc), 1);
475 BEGIN_NVC0(push
, SUBC_3D(0x19c0), 1);
478 if (obj_class
< GM107_3D_CLASS
) {
479 BEGIN_NVC0(push
, SUBC_3D(0x075c), 1);
482 if (obj_class
>= NVE4_3D_CLASS
) {
483 BEGIN_NVC0(push
, SUBC_3D(0x07fc), 1);
488 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
489 * are supposed to do */
493 nvc0_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
495 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
496 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
498 /* we need to do it after possible flush in MARK_RING */
499 *sequence
= ++screen
->base
.fence
.sequence
;
501 BEGIN_NVC0(push
, NVC0_3D(QUERY_ADDRESS_HIGH
), 4);
502 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
503 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
504 PUSH_DATA (push
, *sequence
);
505 PUSH_DATA (push
, NVC0_3D_QUERY_GET_FENCE
| NVC0_3D_QUERY_GET_SHORT
|
506 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT
));
510 nvc0_screen_fence_update(struct pipe_screen
*pscreen
)
512 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
513 return screen
->fence
.map
[0];
517 nvc0_screen_init_compute(struct nvc0_screen
*screen
)
519 screen
->base
.base
.get_compute_param
= nvc0_screen_get_compute_param
;
521 switch (screen
->base
.device
->chipset
& ~0xf) {
524 /* Using COMPUTE has weird effects on 3D state, we need to
525 * investigate this further before enabling it by default.
527 if (debug_get_bool_option("NVC0_COMPUTE", FALSE
))
528 return nvc0_screen_compute_setup(screen
, screen
->base
.pushbuf
);
531 return nve4_screen_compute_setup(screen
, screen
->base
.pushbuf
);
542 nvc0_screen_resize_tls_area(struct nvc0_screen
*screen
,
543 uint32_t lpos
, uint32_t lneg
, uint32_t cstack
)
545 struct nouveau_bo
*bo
= NULL
;
547 uint64_t size
= (lpos
+ lneg
) * 32 + cstack
;
549 if (size
>= (1 << 20)) {
550 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64
"\n", size
);
554 size
*= (screen
->base
.device
->chipset
>= 0xe0) ? 64 : 48; /* max warps */
555 size
= align(size
, 0x8000);
556 size
*= screen
->mp_count
;
558 size
= align(size
, 1 << 17);
560 ret
= nouveau_bo_new(screen
->base
.device
, NOUVEAU_BO_VRAM
, 1 << 17, size
,
563 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64
"\n", size
);
566 nouveau_bo_ref(NULL
, &screen
->tls
);
571 #define FAIL_SCREEN_INIT(str, err) \
573 NOUVEAU_ERR(str, err); \
574 nvc0_screen_destroy(pscreen); \
579 nvc0_screen_create(struct nouveau_device
*dev
)
581 struct nvc0_screen
*screen
;
582 struct pipe_screen
*pscreen
;
583 struct nouveau_object
*chan
;
584 struct nouveau_pushbuf
*push
;
589 union nouveau_bo_config mm_config
;
591 switch (dev
->chipset
& ~0xf) {
603 screen
= CALLOC_STRUCT(nvc0_screen
);
606 pscreen
= &screen
->base
.base
;
608 ret
= nouveau_screen_init(&screen
->base
, dev
);
610 nvc0_screen_destroy(pscreen
);
613 chan
= screen
->base
.channel
;
614 push
= screen
->base
.pushbuf
;
615 push
->user_priv
= screen
;
618 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
619 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
620 screen
->base
.sysmem_bindings
|=
621 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
623 pscreen
->destroy
= nvc0_screen_destroy
;
624 pscreen
->context_create
= nvc0_create
;
625 pscreen
->is_format_supported
= nvc0_screen_is_format_supported
;
626 pscreen
->get_param
= nvc0_screen_get_param
;
627 pscreen
->get_shader_param
= nvc0_screen_get_shader_param
;
628 pscreen
->get_paramf
= nvc0_screen_get_paramf
;
629 pscreen
->get_driver_query_info
= nvc0_screen_get_driver_query_info
;
631 nvc0_screen_init_resource_functions(pscreen
);
633 screen
->base
.base
.get_video_param
= nouveau_vp3_screen_get_video_param
;
634 screen
->base
.base
.is_video_format_supported
= nouveau_vp3_screen_video_supported
;
636 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096, NULL
,
640 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
641 screen
->fence
.map
= screen
->fence
.bo
->map
;
642 screen
->base
.fence
.emit
= nvc0_screen_fence_emit
;
643 screen
->base
.fence
.update
= nvc0_screen_fence_update
;
646 ret
= nouveau_object_new(chan
,
647 (dev
->chipset
< 0xe0) ? 0x1f906e : 0x906e, 0x906e,
648 NULL
, 0, &screen
->nvsw
);
650 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret
);
653 switch (dev
->chipset
& ~0xf) {
657 obj_class
= NVF0_P2MF_CLASS
;
660 obj_class
= NVE4_P2MF_CLASS
;
663 obj_class
= NVC0_M2MF_CLASS
;
666 ret
= nouveau_object_new(chan
, 0xbeef323f, obj_class
, NULL
, 0,
669 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
671 BEGIN_NVC0(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
672 PUSH_DATA (push
, screen
->m2mf
->oclass
);
673 if (screen
->m2mf
->oclass
== NVE4_P2MF_CLASS
) {
674 BEGIN_NVC0(push
, SUBC_COPY(NV01_SUBCHAN_OBJECT
), 1);
675 PUSH_DATA (push
, 0xa0b5);
678 ret
= nouveau_object_new(chan
, 0xbeef902d, NVC0_2D_CLASS
, NULL
, 0,
681 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
683 BEGIN_NVC0(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
684 PUSH_DATA (push
, screen
->eng2d
->oclass
);
685 BEGIN_NVC0(push
, NVC0_2D(SINGLE_GPC
), 1);
687 BEGIN_NVC0(push
, NVC0_2D(OPERATION
), 1);
688 PUSH_DATA (push
, NVC0_2D_OPERATION_SRCCOPY
);
689 BEGIN_NVC0(push
, NVC0_2D(CLIP_ENABLE
), 1);
691 BEGIN_NVC0(push
, NVC0_2D(COLOR_KEY_ENABLE
), 1);
693 BEGIN_NVC0(push
, SUBC_2D(0x0884), 1);
694 PUSH_DATA (push
, 0x3f);
695 BEGIN_NVC0(push
, SUBC_2D(0x0888), 1);
697 BEGIN_NVC0(push
, NVC0_2D(COND_MODE
), 1);
698 PUSH_DATA (push
, NVC0_2D_COND_MODE_ALWAYS
);
700 BEGIN_NVC0(push
, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH
), 2);
701 PUSH_DATAh(push
, screen
->fence
.bo
->offset
+ 16);
702 PUSH_DATA (push
, screen
->fence
.bo
->offset
+ 16);
704 switch (dev
->chipset
& ~0xf) {
706 obj_class
= GM107_3D_CLASS
;
710 obj_class
= NVF0_3D_CLASS
;
713 switch (dev
->chipset
) {
715 obj_class
= NVEA_3D_CLASS
;
718 obj_class
= NVE4_3D_CLASS
;
723 obj_class
= NVC8_3D_CLASS
;
727 switch (dev
->chipset
) {
729 obj_class
= NVC8_3D_CLASS
;
732 obj_class
= NVC1_3D_CLASS
;
735 obj_class
= NVC0_3D_CLASS
;
740 ret
= nouveau_object_new(chan
, 0xbeef003d, obj_class
, NULL
, 0,
743 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
744 screen
->base
.class_3d
= obj_class
;
746 BEGIN_NVC0(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
747 PUSH_DATA (push
, screen
->eng3d
->oclass
);
749 BEGIN_NVC0(push
, NVC0_3D(COND_MODE
), 1);
750 PUSH_DATA (push
, NVC0_3D_COND_MODE_ALWAYS
);
752 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE
)) {
753 /* kill shaders after about 1 second (at 100 MHz) */
754 BEGIN_NVC0(push
, NVC0_3D(WATCHDOG_TIMER
), 1);
755 PUSH_DATA (push
, 0x17);
758 IMMED_NVC0(push
, NVC0_3D(ZETA_COMP_ENABLE
), dev
->drm_version
>= 0x01000101);
759 BEGIN_NVC0(push
, NVC0_3D(RT_COMP_ENABLE(0)), 8);
760 for (i
= 0; i
< 8; ++i
)
761 PUSH_DATA(push
, dev
->drm_version
>= 0x01000101);
763 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
766 BEGIN_NVC0(push
, NVC0_3D(CSAA_ENABLE
), 1);
768 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_ENABLE
), 1);
770 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 1);
771 PUSH_DATA (push
, NVC0_3D_MULTISAMPLE_MODE_MS1
);
772 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_CTRL
), 1);
774 BEGIN_NVC0(push
, NVC0_3D(LINE_WIDTH_SEPARATE
), 1);
776 BEGIN_NVC0(push
, NVC0_3D(LINE_LAST_PIXEL
), 1);
778 BEGIN_NVC0(push
, NVC0_3D(BLEND_SEPARATE_ALPHA
), 1);
780 BEGIN_NVC0(push
, NVC0_3D(BLEND_ENABLE_COMMON
), 1);
782 if (screen
->eng3d
->oclass
< NVE4_3D_CLASS
) {
783 BEGIN_NVC0(push
, NVC0_3D(TEX_MISC
), 1);
784 PUSH_DATA (push
, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
786 BEGIN_NVC0(push
, NVE4_3D(TEX_CB_INDEX
), 1);
787 PUSH_DATA (push
, 15);
789 BEGIN_NVC0(push
, NVC0_3D(CALL_LIMIT_LOG
), 1);
790 PUSH_DATA (push
, 8); /* 128 */
791 BEGIN_NVC0(push
, NVC0_3D(ZCULL_STATCTRS_ENABLE
), 1);
793 if (screen
->eng3d
->oclass
>= NVC1_3D_CLASS
) {
794 BEGIN_NVC0(push
, NVC0_3D(CACHE_SPLIT
), 1);
795 PUSH_DATA (push
, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1
);
798 nvc0_magic_3d_init(push
, screen
->eng3d
->oclass
);
800 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 20, NULL
,
805 /* XXX: getting a page fault at the end of the code buffer every few
806 * launches, don't use the last 256 bytes to work around them - prefetch ?
808 nouveau_heap_init(&screen
->text_heap
, 0, (1 << 20) - 0x100);
810 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 12, 6 << 16, NULL
,
811 &screen
->uniform_bo
);
815 PUSH_REFN (push
, screen
->uniform_bo
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
817 for (i
= 0; i
< 5; ++i
) {
818 /* TIC and TSC entries for each unit (nve4+ only) */
819 /* auxiliary constants (6 user clip planes, base instance id) */
820 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
821 PUSH_DATA (push
, 512);
822 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
823 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
824 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(i
)), 1);
825 PUSH_DATA (push
, (15 << 4) | 1);
826 if (screen
->eng3d
->oclass
>= NVE4_3D_CLASS
) {
828 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 9);
830 for (j
= 0; j
< 8; ++j
)
833 BEGIN_NVC0(push
, NVC0_3D(TEX_LIMITS(i
)), 1);
834 PUSH_DATA (push
, 0x54);
837 BEGIN_NVC0(push
, NVC0_3D(LINKED_TSC
), 1);
840 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
841 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
842 PUSH_DATA (push
, 256);
843 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
844 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
845 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 5);
847 PUSH_DATAf(push
, 0.0f
);
848 PUSH_DATAf(push
, 0.0f
);
849 PUSH_DATAf(push
, 0.0f
);
850 PUSH_DATAf(push
, 0.0f
);
851 BEGIN_NVC0(push
, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
852 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
853 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (6 << 9));
855 if (dev
->drm_version
>= 0x01000101) {
856 ret
= nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
858 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
862 if (dev
->chipset
>= 0xe0 && dev
->chipset
< 0xf0)
863 value
= (8 << 8) | 4;
865 value
= (16 << 8) | 4;
867 screen
->mp_count
= value
>> 8;
868 screen
->mp_count_compute
= screen
->mp_count
;
870 nvc0_screen_resize_tls_area(screen
, 128 * 16, 0, 0x200);
872 BEGIN_NVC0(push
, NVC0_3D(CODE_ADDRESS_HIGH
), 2);
873 PUSH_DATAh(push
, screen
->text
->offset
);
874 PUSH_DATA (push
, screen
->text
->offset
);
875 BEGIN_NVC0(push
, NVC0_3D(TEMP_ADDRESS_HIGH
), 4);
876 PUSH_DATAh(push
, screen
->tls
->offset
);
877 PUSH_DATA (push
, screen
->tls
->offset
);
878 PUSH_DATA (push
, screen
->tls
->size
>> 32);
879 PUSH_DATA (push
, screen
->tls
->size
);
880 BEGIN_NVC0(push
, NVC0_3D(WARP_TEMP_ALLOC
), 1);
882 BEGIN_NVC0(push
, NVC0_3D(LOCAL_BASE
), 1);
885 if (screen
->eng3d
->oclass
< GM107_3D_CLASS
) {
886 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 20, NULL
,
887 &screen
->poly_cache
);
891 BEGIN_NVC0(push
, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH
), 3);
892 PUSH_DATAh(push
, screen
->poly_cache
->offset
);
893 PUSH_DATA (push
, screen
->poly_cache
->offset
);
897 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 17, NULL
,
902 BEGIN_NVC0(push
, NVC0_3D(TIC_ADDRESS_HIGH
), 3);
903 PUSH_DATAh(push
, screen
->txc
->offset
);
904 PUSH_DATA (push
, screen
->txc
->offset
);
905 PUSH_DATA (push
, NVC0_TIC_MAX_ENTRIES
- 1);
907 BEGIN_NVC0(push
, NVC0_3D(TSC_ADDRESS_HIGH
), 3);
908 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
909 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
910 PUSH_DATA (push
, NVC0_TSC_MAX_ENTRIES
- 1);
912 BEGIN_NVC0(push
, NVC0_3D(SCREEN_Y_CONTROL
), 1);
914 BEGIN_NVC0(push
, NVC0_3D(WINDOW_OFFSET_X
), 2);
917 BEGIN_NVC0(push
, NVC0_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
918 PUSH_DATA (push
, 0x3f);
920 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_MODE
), 1);
921 PUSH_DATA (push
, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
922 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
923 for (i
= 0; i
< 8 * 2; ++i
)
925 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_EN
), 1);
927 BEGIN_NVC0(push
, NVC0_3D(CLIPID_ENABLE
), 1);
930 /* neither scissors, viewport nor stencil mask should affect clears */
931 BEGIN_NVC0(push
, NVC0_3D(CLEAR_FLAGS
), 1);
934 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 1);
936 BEGIN_NVC0(push
, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
937 PUSH_DATAf(push
, 0.0f
);
938 PUSH_DATAf(push
, 1.0f
);
939 BEGIN_NVC0(push
, NVC0_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
940 PUSH_DATA (push
, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
);
942 /* We use scissors instead of exact view volume clipping,
943 * so they're always enabled.
945 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_ENABLE(0)), 3);
947 PUSH_DATA (push
, 8192 << 16);
948 PUSH_DATA (push
, 8192 << 16);
950 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
953 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE
, mme9097_per_instance_bf
);
954 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES
, mme9097_blend_enables
);
955 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT
, mme9097_vertex_array_select
);
956 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT
, mme9097_tep_select
);
957 MK_MACRO(NVC0_3D_MACRO_GP_SELECT
, mme9097_gp_select
);
958 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT
, mme9097_poly_mode_front
);
959 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK
, mme9097_poly_mode_back
);
961 BEGIN_NVC0(push
, NVC0_3D(RASTERIZE_ENABLE
), 1);
963 BEGIN_NVC0(push
, NVC0_3D(RT_SEPARATE_FRAG_DATA
), 1);
965 BEGIN_NVC0(push
, NVC0_3D(MACRO_GP_SELECT
), 1);
966 PUSH_DATA (push
, 0x40);
967 BEGIN_NVC0(push
, NVC0_3D(LAYER
), 1);
969 BEGIN_NVC0(push
, NVC0_3D(MACRO_TEP_SELECT
), 1);
970 PUSH_DATA (push
, 0x30);
971 BEGIN_NVC0(push
, NVC0_3D(PATCH_VERTICES
), 1);
973 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(2)), 1);
974 PUSH_DATA (push
, 0x20);
975 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(0)), 1);
976 PUSH_DATA (push
, 0x00);
978 BEGIN_NVC0(push
, NVC0_3D(POINT_COORD_REPLACE
), 1);
980 BEGIN_NVC0(push
, NVC0_3D(POINT_RASTER_RULES
), 1);
981 PUSH_DATA (push
, NVC0_3D_POINT_RASTER_RULES_OGL
);
983 IMMED_NVC0(push
, NVC0_3D(EDGEFLAG
), 1);
985 if (nvc0_screen_init_compute(screen
))
990 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
991 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
993 mm_config
.nvc0
.tile_mode
= 0;
994 mm_config
.nvc0
.memtype
= 0xfe0;
995 screen
->mm_VRAM_fe0
= nouveau_mm_create(dev
, NOUVEAU_BO_VRAM
, &mm_config
);
997 if (!nvc0_blitter_create(screen
))
1000 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);
1005 nvc0_screen_destroy(pscreen
);
1010 nvc0_screen_tic_alloc(struct nvc0_screen
*screen
, void *entry
)
1012 int i
= screen
->tic
.next
;
1014 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
1015 i
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1017 screen
->tic
.next
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
1019 if (screen
->tic
.entries
[i
])
1020 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
1022 screen
->tic
.entries
[i
] = entry
;
1027 nvc0_screen_tsc_alloc(struct nvc0_screen
*screen
, void *entry
)
1029 int i
= screen
->tsc
.next
;
1031 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
1032 i
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1034 screen
->tsc
.next
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
1036 if (screen
->tsc
.entries
[i
])
1037 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
1039 screen
->tsc
.entries
[i
] = entry
;