src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include "util/u_format.h"
  26 #include "util/u_format_s3tc.h"
  27 #include "pipe/p_screen.h"
  28
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31
  32 #include "nouveau_vp3_video.h"
  33
  34 #include "nvc0/nvc0_context.h"
  35 #include "nvc0/nvc0_screen.h"
  36
  37 #include "nvc0/mme/com9097.mme.h"
  38
  39 static boolean
  40 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (sample_count > 8)
  47       return false;
  48    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  49       return false;
  50
  51    if (!util_format_is_supported(format, bindings))
  52       return false;
  53
  54    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  55       if (util_format_get_blocksizebits(format) == 3 * 32)
  56          return false;
  57
  58    /* transfers & shared are always supported */
  59    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  60                  PIPE_BIND_TRANSFER_WRITE |
  61                  PIPE_BIND_SHARED);
  62
  63    return (nvc0_format_table[format].usage & bindings) == bindings;
  64 }
  65
  66 static int
  67 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  68 {
  69    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  70    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  71
  72    switch (param) {
  73    /* non-boolean caps */
  74    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76       return 15;
  77    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80       return 2048;
  81    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82       return -8;
  83    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84       return 7;
  85    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  86       return -32;
  87    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  88       return 31;
  89    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  90       return 128 * 1024 * 1024;
  91    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  92       return 410;
  93    case PIPE_CAP_MAX_RENDER_TARGETS:
  94       return 8;
  95    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  96       return 1;
  97    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  98       return 4;
  99    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 100    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 101       return 128;
 102    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 103    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 104       return 1024;
 105    case PIPE_CAP_MAX_VERTEX_STREAMS:
 106       return 4;
 107    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 108       return 2048;
 109    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 110       return 256;
 111    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 112       return 1; /* 256 for binding as RT, but that's not possible in GL */
 113    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 114       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 115    case PIPE_CAP_MAX_VIEWPORTS:
 116       return NVC0_MAX_VIEWPORTS;
 117    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 118       return 4;
 119    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 120       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 121    case PIPE_CAP_ENDIANNESS:
 122       return PIPE_ENDIAN_LITTLE;
 123    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 124       return 30;
 125
 126    /* supported caps */
 127    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 128    case PIPE_CAP_TEXTURE_SWIZZLE:
 129    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 130    case PIPE_CAP_NPOT_TEXTURES:
 131    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 132    case PIPE_CAP_ANISOTROPIC_FILTER:
 133    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 134    case PIPE_CAP_CUBE_MAP_ARRAY:
 135    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 136    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 137    case PIPE_CAP_TWO_SIDED_STENCIL:
 138    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 139    case PIPE_CAP_POINT_SPRITE:
 140    case PIPE_CAP_TGSI_TEXCOORD:
 141    case PIPE_CAP_SM3:
 142    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 143    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 144    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 145    case PIPE_CAP_QUERY_TIMESTAMP:
 146    case PIPE_CAP_QUERY_TIME_ELAPSED:
 147    case PIPE_CAP_OCCLUSION_QUERY:
 148    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 149    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 150    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 151    case PIPE_CAP_INDEP_BLEND_ENABLE:
 152    case PIPE_CAP_INDEP_BLEND_FUNC:
 153    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 154    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 155    case PIPE_CAP_PRIMITIVE_RESTART:
 156    case PIPE_CAP_TGSI_INSTANCEID:
 157    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 158    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 159    case PIPE_CAP_CONDITIONAL_RENDER:
 160    case PIPE_CAP_TEXTURE_BARRIER:
 161    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 162    case PIPE_CAP_START_INSTANCE:
 163    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 164    case PIPE_CAP_DRAW_INDIRECT:
 165    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 166    case PIPE_CAP_USER_INDEX_BUFFERS:
 167    case PIPE_CAP_USER_VERTEX_BUFFERS:
 168    case PIPE_CAP_TEXTURE_QUERY_LOD:
 169    case PIPE_CAP_SAMPLE_SHADING:
 170    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 171    case PIPE_CAP_TEXTURE_GATHER_SM5:
 172    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 173    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 174    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 175    case PIPE_CAP_CLIP_HALFZ:
 176    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 177    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 178    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 179    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 180    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 181    case PIPE_CAP_TGSI_TXQS:
 182    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 183    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 184    case PIPE_CAP_SHAREABLE_SHADERS:
 185       return 1;
 186    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 187       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 188    case PIPE_CAP_COMPUTE:
 189       return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
 190    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 191       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 192
 193    /* unsupported caps */
 194    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 195    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 196    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 197    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 198    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 199    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 200    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 201    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 202    case PIPE_CAP_FAKE_SW_MSAA:
 203    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 204    case PIPE_CAP_VERTEXID_NOBASE:
 205    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 206    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 207       return 0;
 208
 209    case PIPE_CAP_VENDOR_ID:
 210       return 0x10de;
 211    case PIPE_CAP_DEVICE_ID: {
 212       uint64_t device_id;
 213       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 214          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 215          return -1;
 216       }
 217       return device_id;
 218    }
 219    case PIPE_CAP_ACCELERATED:
 220       return 1;
 221    case PIPE_CAP_VIDEO_MEMORY:
 222       return dev->vram_size >> 20;
 223    case PIPE_CAP_UMA:
 224       return 0;
 225    }
 226
 227    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 228    return 0;
 229 }
 230
 231 static int
 232 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 233                              enum pipe_shader_cap param)
 234 {
 235    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 236
 237    switch (shader) {
 238    case PIPE_SHADER_VERTEX:
 239    case PIPE_SHADER_GEOMETRY:
 240    case PIPE_SHADER_FRAGMENT:
 241       break;
 242    case PIPE_SHADER_TESS_CTRL:
 243    case PIPE_SHADER_TESS_EVAL:
 244       if (class_3d >= GM107_3D_CLASS)
 245          return 0;
 246       break;
 247    case PIPE_SHADER_COMPUTE:
 248       if (class_3d != NVE4_3D_CLASS)
 249          return 0;
 250       break;
 251    default:
 252       return 0;
 253    }
 254
 255    switch (param) {
 256    case PIPE_SHADER_CAP_PREFERRED_IR:
 257       return PIPE_SHADER_IR_TGSI;
 258    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 259    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 260    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 261    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 262       return 16384;
 263    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 264       return 16;
 265    case PIPE_SHADER_CAP_MAX_INPUTS:
 266       if (shader == PIPE_SHADER_VERTEX)
 267          return 32;
 268       /* NOTE: These only count our slots for GENERIC varyings.
 269        * The address space may be larger, but the actual hard limit seems to be
 270        * less than what the address space layout permits, so don't add TEXCOORD,
 271        * COLOR, etc. here.
 272        */
 273       if (shader == PIPE_SHADER_FRAGMENT)
 274          return 0x1f0 / 16;
 275       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 276        * and excludes 0x60 per-patch inputs.
 277        */
 278       return 0x200 / 16;
 279    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 280       return 32;
 281    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 282       return 65536;
 283    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 284       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 285          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 286       return NVC0_MAX_PIPE_CONSTBUFS;
 287    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 288    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 289       return shader != PIPE_SHADER_FRAGMENT;
 290    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 291    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 292       return 1;
 293    case PIPE_SHADER_CAP_MAX_PREDS:
 294       return 0;
 295    case PIPE_SHADER_CAP_MAX_TEMPS:
 296       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 297    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 298       return 1;
 299    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 300       return 0;
 301    case PIPE_SHADER_CAP_SUBROUTINES:
 302       return 1;
 303    case PIPE_SHADER_CAP_INTEGERS:
 304       return 1;
 305    case PIPE_SHADER_CAP_DOUBLES:
 306       return 1;
 307    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 308       return 1;
 309    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 310    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 311    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 312       return 0;
 313    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 314       return 16; /* would be 32 in linked (OpenGL-style) mode */
 315    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 316       return 16; /* XXX not sure if more are really safe */
 317    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 318       return 32;
 319    default:
 320       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 321       return 0;
 322    }
 323 }
 324
 325 static float
 326 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 327 {
 328    switch (param) {
 329    case PIPE_CAPF_MAX_LINE_WIDTH:
 330    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 331       return 10.0f;
 332    case PIPE_CAPF_MAX_POINT_WIDTH:
 333       return 63.0f;
 334    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 335       return 63.375f;
 336    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 337       return 16.0f;
 338    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 339       return 15.0f;
 340    case PIPE_CAPF_GUARD_BAND_LEFT:
 341    case PIPE_CAPF_GUARD_BAND_TOP:
 342       return 0.0f;
 343    case PIPE_CAPF_GUARD_BAND_RIGHT:
 344    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 345       return 0.0f; /* that or infinity */
 346    }
 347
 348    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 349    return 0.0f;
 350 }
 351
 352 static int
 353 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 354                               enum pipe_compute_cap param, void *data)
 355 {
 356    uint64_t *data64 = (uint64_t *)data;
 357    uint32_t *data32 = (uint32_t *)data;
 358    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 359
 360    switch (param) {
 361    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 362       data64[0] = 3;
 363       return 8;
 364    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 365       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 366       data64[1] = 65535;
 367       data64[2] = 65535;
 368       return 24;
 369    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 370       data64[0] = 1024;
 371       data64[1] = 1024;
 372       data64[2] = 64;
 373       return 24;
 374    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 375       data64[0] = 1024;
 376       return 8;
 377    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 378       data64[0] = (uint64_t)1 << 40;
 379       return 8;
 380    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 381       data64[0] = 48 << 10;
 382       return 8;
 383    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 384       data64[0] = 512 << 10;
 385       return 8;
 386    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 387       data64[0] = 4096;
 388       return 8;
 389    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 390       data32[0] = 32;
 391       return 4;
 392    default:
 393       return 0;
 394    }
 395 }
 396
 397 static void
 398 nvc0_screen_destroy(struct pipe_screen *pscreen)
 399 {
 400    struct nvc0_screen *screen = nvc0_screen(pscreen);
 401
 402    if (!nouveau_drm_screen_unref(&screen->base))
 403       return;
 404
 405    if (screen->base.fence.current) {
 406       struct nouveau_fence *current = NULL;
 407
 408       /* nouveau_fence_wait will create a new current fence, so wait on the
 409        * _current_ one, and remove both.
 410        */
 411       nouveau_fence_ref(screen->base.fence.current, &current);
 412       nouveau_fence_wait(current);
 413       nouveau_fence_ref(NULL, &current);
 414       nouveau_fence_ref(NULL, &screen->base.fence.current);
 415    }
 416    if (screen->base.pushbuf)
 417       screen->base.pushbuf->user_priv = NULL;
 418
 419    if (screen->blitter)
 420       nvc0_blitter_destroy(screen);
 421    if (screen->pm.prog) {
 422       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 423       nvc0_program_destroy(NULL, screen->pm.prog);
 424    }
 425
 426    nouveau_bo_ref(NULL, &screen->text);
 427    nouveau_bo_ref(NULL, &screen->uniform_bo);
 428    nouveau_bo_ref(NULL, &screen->tls);
 429    nouveau_bo_ref(NULL, &screen->txc);
 430    nouveau_bo_ref(NULL, &screen->fence.bo);
 431    nouveau_bo_ref(NULL, &screen->poly_cache);
 432    nouveau_bo_ref(NULL, &screen->parm);
 433
 434    nouveau_heap_destroy(&screen->lib_code);
 435    nouveau_heap_destroy(&screen->text_heap);
 436
 437    FREE(screen->tic.entries);
 438
 439    nouveau_object_del(&screen->eng3d);
 440    nouveau_object_del(&screen->eng2d);
 441    nouveau_object_del(&screen->m2mf);
 442    nouveau_object_del(&screen->compute);
 443    nouveau_object_del(&screen->nvsw);
 444
 445    nouveau_screen_fini(&screen->base);
 446
 447    FREE(screen);
 448 }
 449
 450 static int
 451 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 452                      unsigned size, const uint32_t *data)
 453 {
 454    struct nouveau_pushbuf *push = screen->base.pushbuf;
 455
 456    size /= 4;
 457
 458    assert((pos + size) <= 0x800);
 459
 460    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 461    PUSH_DATA (push, (m - 0x3800) / 8);
 462    PUSH_DATA (push, pos);
 463    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 464    PUSH_DATA (push, pos);
 465    PUSH_DATAp(push, data, size);
 466
 467    return pos + size;
 468 }
 469
 470 static void
 471 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 472 {
 473    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 474    PUSH_DATA (push, 0xff);
 475    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 476    PUSH_DATA (push, 0xff);
 477    PUSH_DATA (push, 0xff);
 478    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 479    PUSH_DATA (push, 0xff);
 480    PUSH_DATA (push, 0xff);
 481    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 482    PUSH_DATA (push, 0x3f);
 483
 484    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 485    PUSH_DATA (push, (3 << 16) | 3);
 486    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 487    PUSH_DATA (push, (2 << 16) | 2);
 488
 489    if (obj_class < GM107_3D_CLASS) {
 490       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 491       PUSH_DATA (push, 0);
 492    }
 493    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 494    PUSH_DATA (push, 0x10);
 495    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 496    PUSH_DATA (push, 0x10);
 497    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 498    PUSH_DATA (push, 0x10);
 499    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 500    PUSH_DATA (push, 0x10);
 501    PUSH_DATA (push, 0x10);
 502    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 503    PUSH_DATA (push, 0x10);
 504    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 505    PUSH_DATA (push, 0xe);
 506
 507    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 508    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 509    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 510    PUSH_DATA (push, 0);
 511    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 512    PUSH_DATA (push, 3);
 513
 514    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 515    PUSH_DATA (push, 0x3fffff);
 516    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 517    PUSH_DATA (push, 1);
 518    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 519    PUSH_DATA (push, 1);
 520
 521    if (obj_class < GM107_3D_CLASS) {
 522       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 523       PUSH_DATA (push, 3);
 524
 525       if (obj_class >= NVE4_3D_CLASS) {
 526          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 527          PUSH_DATA (push, 1);
 528       }
 529    }
 530
 531    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 532     * are supposed to do */
 533 }
 534
 535 static void
 536 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 537 {
 538    struct nvc0_screen *screen = nvc0_screen(pscreen);
 539    struct nouveau_pushbuf *push = screen->base.pushbuf;
 540
 541    /* we need to do it after possible flush in MARK_RING */
 542    *sequence = ++screen->base.fence.sequence;
 543
 544    assert(PUSH_AVAIL(push) >= 5);
 545    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 546    PUSH_DATAh(push, screen->fence.bo->offset);
 547    PUSH_DATA (push, screen->fence.bo->offset);
 548    PUSH_DATA (push, *sequence);
 549    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 550               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 551 }
 552
 553 static u32
 554 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 555 {
 556    struct nvc0_screen *screen = nvc0_screen(pscreen);
 557    return screen->fence.map[0];
 558 }
 559
 560 static int
 561 nvc0_screen_init_compute(struct nvc0_screen *screen)
 562 {
 563    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 564
 565    switch (screen->base.device->chipset & ~0xf) {
 566    case 0xc0:
 567    case 0xd0:
 568       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 569    case 0xe0:
 570       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 571    case 0xf0:
 572    case 0x100:
 573    case 0x110:
 574       return 0;
 575    default:
 576       return -1;
 577    }
 578 }
 579
 580 bool
 581 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 582                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 583 {
 584    struct nouveau_bo *bo = NULL;
 585    int ret;
 586    uint64_t size = (lpos + lneg) * 32 + cstack;
 587
 588    if (size >= (1 << 20)) {
 589       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 590       return false;
 591    }
 592
 593    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 594    size  = align(size, 0x8000);
 595    size *= screen->mp_count;
 596
 597    size = align(size, 1 << 17);
 598
 599    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 600                         NULL, &bo);
 601    if (ret) {
 602       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 603       return false;
 604    }
 605    nouveau_bo_ref(NULL, &screen->tls);
 606    screen->tls = bo;
 607    return true;
 608 }
 609
 610 #define FAIL_SCREEN_INIT(str, err)                    \
 611    do {                                               \
 612       NOUVEAU_ERR(str, err);                          \
 613       nvc0_screen_destroy(pscreen);                   \
 614       return NULL;                                    \
 615    } while(0)
 616
 617 struct pipe_screen *
 618 nvc0_screen_create(struct nouveau_device *dev)
 619 {
 620    struct nvc0_screen *screen;
 621    struct pipe_screen *pscreen;
 622    struct nouveau_object *chan;
 623    struct nouveau_pushbuf *push;
 624    uint64_t value;
 625    uint32_t obj_class;
 626    uint32_t flags;
 627    int ret;
 628    unsigned i;
 629
 630    switch (dev->chipset & ~0xf) {
 631    case 0xc0:
 632    case 0xd0:
 633    case 0xe0:
 634    case 0xf0:
 635    case 0x100:
 636    case 0x110:
 637       break;
 638    default:
 639       return NULL;
 640    }
 641
 642    screen = CALLOC_STRUCT(nvc0_screen);
 643    if (!screen)
 644       return NULL;
 645    pscreen = &screen->base.base;
 646
 647    ret = nouveau_screen_init(&screen->base, dev);
 648    if (ret) {
 649       nvc0_screen_destroy(pscreen);
 650       return NULL;
 651    }
 652    chan = screen->base.channel;
 653    push = screen->base.pushbuf;
 654    push->user_priv = screen;
 655    push->rsvd_kick = 5;
 656
 657    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 658       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 659       PIPE_BIND_COMMAND_ARGS_BUFFER;
 660    screen->base.sysmem_bindings |=
 661       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 662
 663    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 664       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 665       screen->base.vidmem_bindings = 0;
 666    }
 667
 668    pscreen->destroy = nvc0_screen_destroy;
 669    pscreen->context_create = nvc0_create;
 670    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 671    pscreen->get_param = nvc0_screen_get_param;
 672    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 673    pscreen->get_paramf = nvc0_screen_get_paramf;
 674    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 675    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 676
 677    nvc0_screen_init_resource_functions(pscreen);
 678
 679    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 680    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 681
 682    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 683    if (dev->drm_version >= 0x01000202)
 684       flags |= NOUVEAU_BO_COHERENT;
 685
 686    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 687    if (ret)
 688       goto fail;
 689    nouveau_bo_map(screen->fence.bo, 0, NULL);
 690    screen->fence.map = screen->fence.bo->map;
 691    screen->base.fence.emit = nvc0_screen_fence_emit;
 692    screen->base.fence.update = nvc0_screen_fence_update;
 693
 694
 695    ret = nouveau_object_new(chan,
 696                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
 697                             NULL, 0, &screen->nvsw);
 698    if (ret)
 699       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 700
 701
 702    switch (dev->chipset & ~0xf) {
 703    case 0x110:
 704    case 0x100:
 705    case 0xf0:
 706       obj_class = NVF0_P2MF_CLASS;
 707       break;
 708    case 0xe0:
 709       obj_class = NVE4_P2MF_CLASS;
 710       break;
 711    default:
 712       obj_class = NVC0_M2MF_CLASS;
 713       break;
 714    }
 715    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 716                             &screen->m2mf);
 717    if (ret)
 718       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 719
 720    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 721    PUSH_DATA (push, screen->m2mf->oclass);
 722    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 723       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 724       PUSH_DATA (push, 0xa0b5);
 725    }
 726
 727    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 728                             &screen->eng2d);
 729    if (ret)
 730       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 731
 732    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 733    PUSH_DATA (push, screen->eng2d->oclass);
 734    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 735    PUSH_DATA (push, 0);
 736    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 737    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 738    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 739    PUSH_DATA (push, 0);
 740    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 741    PUSH_DATA (push, 0);
 742    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 743    PUSH_DATA (push, 0x3f);
 744    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 745    PUSH_DATA (push, 1);
 746    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 747    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 748
 749    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 750    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 751    PUSH_DATA (push, screen->fence.bo->offset + 16);
 752
 753    switch (dev->chipset & ~0xf) {
 754    case 0x110:
 755       obj_class = GM107_3D_CLASS;
 756       break;
 757    case 0x100:
 758    case 0xf0:
 759       obj_class = NVF0_3D_CLASS;
 760       break;
 761    case 0xe0:
 762       switch (dev->chipset) {
 763       case 0xea:
 764          obj_class = NVEA_3D_CLASS;
 765          break;
 766       default:
 767          obj_class = NVE4_3D_CLASS;
 768          break;
 769       }
 770       break;
 771    case 0xd0:
 772       obj_class = NVC8_3D_CLASS;
 773       break;
 774    case 0xc0:
 775    default:
 776       switch (dev->chipset) {
 777       case 0xc8:
 778          obj_class = NVC8_3D_CLASS;
 779          break;
 780       case 0xc1:
 781          obj_class = NVC1_3D_CLASS;
 782          break;
 783       default:
 784          obj_class = NVC0_3D_CLASS;
 785          break;
 786       }
 787       break;
 788    }
 789    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 790                             &screen->eng3d);
 791    if (ret)
 792       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 793    screen->base.class_3d = obj_class;
 794
 795    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 796    PUSH_DATA (push, screen->eng3d->oclass);
 797
 798    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 799    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 800
 801    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 802       /* kill shaders after about 1 second (at 100 MHz) */
 803       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 804       PUSH_DATA (push, 0x17);
 805    }
 806
 807    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 808    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 809    for (i = 0; i < 8; ++i)
 810            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 811
 812    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 813    PUSH_DATA (push, 1);
 814
 815    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 816    PUSH_DATA (push, 0);
 817    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 818    PUSH_DATA (push, 0);
 819    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 820    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 821    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 822    PUSH_DATA (push, 0);
 823    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 824    PUSH_DATA (push, 1);
 825    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 826    PUSH_DATA (push, 1);
 827    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 828    PUSH_DATA (push, 1);
 829    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 830    PUSH_DATA (push, 0);
 831    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 832    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 833    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 834       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 835       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 836    } else {
 837       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 838       PUSH_DATA (push, 15);
 839    }
 840    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 841    PUSH_DATA (push, 8); /* 128 */
 842    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 843    PUSH_DATA (push, 1);
 844    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 845       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 846       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 847    }
 848
 849    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 850
 851    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 852                         &screen->text);
 853    if (ret)
 854       goto fail;
 855
 856    /* XXX: getting a page fault at the end of the code buffer every few
 857     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 858     */
 859    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 860
 861    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
 862                         &screen->uniform_bo);
 863    if (ret)
 864       goto fail;
 865
 866    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 867
 868    for (i = 0; i < 5; ++i) {
 869       /* TIC and TSC entries for each unit (nve4+ only) */
 870       /* auxiliary constants (6 user clip planes, base instance id) */
 871       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 872       PUSH_DATA (push, 512);
 873       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 874       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 875       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 876       PUSH_DATA (push, (15 << 4) | 1);
 877       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 878          unsigned j;
 879          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 880          PUSH_DATA (push, 0);
 881          for (j = 0; j < 8; ++j)
 882             PUSH_DATA(push, j);
 883       } else {
 884          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 885          PUSH_DATA (push, 0x54);
 886       }
 887    }
 888    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 889    PUSH_DATA (push, 0);
 890
 891    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 892    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 893    PUSH_DATA (push, 256);
 894    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 895    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 896    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 897    PUSH_DATA (push, 0);
 898    PUSH_DATAf(push, 0.0f);
 899    PUSH_DATAf(push, 0.0f);
 900    PUSH_DATAf(push, 0.0f);
 901    PUSH_DATAf(push, 0.0f);
 902    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 903    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 904    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 905
 906    if (dev->drm_version >= 0x01000101) {
 907       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 908       if (ret) {
 909          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 910          goto fail;
 911       }
 912    } else {
 913       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 914          value = (8 << 8) | 4;
 915       else
 916          value = (16 << 8) | 4;
 917    }
 918    screen->gpc_count = value & 0x000000ff;
 919    screen->mp_count = value >> 8;
 920    screen->mp_count_compute = screen->mp_count;
 921
 922    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 923
 924    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 925    PUSH_DATAh(push, screen->text->offset);
 926    PUSH_DATA (push, screen->text->offset);
 927    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 928    PUSH_DATAh(push, screen->tls->offset);
 929    PUSH_DATA (push, screen->tls->offset);
 930    PUSH_DATA (push, screen->tls->size >> 32);
 931    PUSH_DATA (push, screen->tls->size);
 932    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 933    PUSH_DATA (push, 0);
 934    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 935    PUSH_DATA (push, 0);
 936
 937    if (screen->eng3d->oclass < GM107_3D_CLASS) {
 938       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 939                            &screen->poly_cache);
 940       if (ret)
 941          goto fail;
 942
 943       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 944       PUSH_DATAh(push, screen->poly_cache->offset);
 945       PUSH_DATA (push, screen->poly_cache->offset);
 946       PUSH_DATA (push, 3);
 947    }
 948
 949    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
 950                         &screen->txc);
 951    if (ret)
 952       goto fail;
 953
 954    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 955    PUSH_DATAh(push, screen->txc->offset);
 956    PUSH_DATA (push, screen->txc->offset);
 957    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 958
 959    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 960    PUSH_DATAh(push, screen->txc->offset + 65536);
 961    PUSH_DATA (push, screen->txc->offset + 65536);
 962    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 963
 964    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 965    PUSH_DATA (push, 0);
 966    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 967    PUSH_DATA (push, 0);
 968    PUSH_DATA (push, 0);
 969    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 970    PUSH_DATA (push, 0x3f);
 971
 972    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 973    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 974    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 975    for (i = 0; i < 8 * 2; ++i)
 976       PUSH_DATA(push, 0);
 977    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 978    PUSH_DATA (push, 0);
 979    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 980    PUSH_DATA (push, 0);
 981
 982    /* neither scissors, viewport nor stencil mask should affect clears */
 983    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 984    PUSH_DATA (push, 0);
 985
 986    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 987    PUSH_DATA (push, 1);
 988    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
 989       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
 990       PUSH_DATAf(push, 0.0f);
 991       PUSH_DATAf(push, 1.0f);
 992    }
 993    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 994    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 995
 996    /* We use scissors instead of exact view volume clipping,
 997     * so they're always enabled.
 998     */
 999    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1000       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1001       PUSH_DATA (push, 1);
1002       PUSH_DATA (push, 8192 << 16);
1003       PUSH_DATA (push, 8192 << 16);
1004    }
1005
1006 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1007
1008    i = 0;
1009    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1010    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1011    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1012    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1013    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1014    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1015    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1016    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1017    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1018
1019    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1020    PUSH_DATA (push, 1);
1021    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1022    PUSH_DATA (push, 1);
1023    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1024    PUSH_DATA (push, 0x40);
1025    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1026    PUSH_DATA (push, 0);
1027    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1028    PUSH_DATA (push, 0x30);
1029    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1030    PUSH_DATA (push, 3);
1031    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1032    PUSH_DATA (push, 0x20);
1033    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1034    PUSH_DATA (push, 0x00);
1035    screen->save_state.patch_vertices = 3;
1036
1037    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1038    PUSH_DATA (push, 0);
1039    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1040    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1041
1042    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1043
1044    if (nvc0_screen_init_compute(screen))
1045       goto fail;
1046
1047    PUSH_KICK (push);
1048
1049    screen->tic.entries = CALLOC(4096, sizeof(void *));
1050    screen->tsc.entries = screen->tic.entries + 2048;
1051
1052    if (!nvc0_blitter_create(screen))
1053       goto fail;
1054
1055    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1056
1057    return pscreen;
1058
1059 fail:
1060    nvc0_screen_destroy(pscreen);
1061    return NULL;
1062 }
1063
1064 int
1065 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1066 {
1067    int i = screen->tic.next;
1068
1069    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1070       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1071
1072    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1073
1074    if (screen->tic.entries[i])
1075       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1076
1077    screen->tic.entries[i] = entry;
1078    return i;
1079 }
1080
1081 int
1082 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1083 {
1084    int i = screen->tsc.next;
1085
1086    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1087       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1088
1089    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1090
1091    if (screen->tsc.entries[i])
1092       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1093
1094    screen->tsc.entries[i] = entry;
1095    return i;
1096 }