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[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 #include "nv50/g80_texture.xml.h"
42
43 static boolean
44 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
45 enum pipe_format format,
46 enum pipe_texture_target target,
47 unsigned sample_count,
48 unsigned bindings)
49 {
50 const struct util_format_description *desc = util_format_description(format);
51
52 if (sample_count > 8)
53 return false;
54 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
55 return false;
56
57 /* Short-circuit the rest of the logic -- this is used by the state tracker
58 * to determine valid MS levels in a no-attachments scenario.
59 */
60 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
61 return true;
62
63 if (!util_format_is_supported(format, bindings))
64 return false;
65
66 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
67 if (util_format_get_blocksizebits(format) == 3 * 32)
68 return false;
69
70 if (bindings & PIPE_BIND_LINEAR)
71 if (util_format_is_depth_or_stencil(format) ||
72 (target != PIPE_TEXTURE_1D &&
73 target != PIPE_TEXTURE_2D &&
74 target != PIPE_TEXTURE_RECT) ||
75 sample_count > 1)
76 return false;
77
78 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
79 */
80 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
81 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
82 /* The claim is that this should work on GM107 but it doesn't. Need to
83 * test further and figure out if it's a nouveau issue or a HW one.
84 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
85 */
86 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
87 return false;
88
89 /* shared is always supported */
90 bindings &= ~(PIPE_BIND_LINEAR |
91 PIPE_BIND_SHARED);
92
93 if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
94 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
95 /* MS images are currently unsupported on Maxwell because they have to
96 * be handled explicitly. */
97 return false;
98 }
99
100 return (( nvc0_format_table[format].usage |
101 nvc0_vertex_format[format].usage) & bindings) == bindings;
102 }
103
104 static int
105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
106 {
107 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
108 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
109
110 switch (param) {
111 /* non-boolean caps */
112 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
113 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
114 return 15;
115 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
116 return 12;
117 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
118 return 2048;
119 case PIPE_CAP_MIN_TEXEL_OFFSET:
120 return -8;
121 case PIPE_CAP_MAX_TEXEL_OFFSET:
122 return 7;
123 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
124 return -32;
125 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
126 return 31;
127 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
128 return 128 * 1024 * 1024;
129 case PIPE_CAP_GLSL_FEATURE_LEVEL:
130 return 430;
131 case PIPE_CAP_MAX_RENDER_TARGETS:
132 return 8;
133 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
134 return 1;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 return 4;
137 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
138 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
139 return 128;
140 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
141 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
142 return 1024;
143 case PIPE_CAP_MAX_VERTEX_STREAMS:
144 return 4;
145 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
146 return 2048;
147 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
148 return 256;
149 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
150 if (class_3d < NVE4_3D_CLASS)
151 return 256; /* IMAGE bindings require alignment to 256 */
152 return 16;
153 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
154 return 16;
155 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
156 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
157 case PIPE_CAP_MAX_VIEWPORTS:
158 return NVC0_MAX_VIEWPORTS;
159 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
160 return 4;
161 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
162 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
163 case PIPE_CAP_ENDIANNESS:
164 return PIPE_ENDIAN_LITTLE;
165 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
166 return 30;
167 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
168 return NVC0_MAX_WINDOW_RECTANGLES;
169
170 /* supported caps */
171 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
172 case PIPE_CAP_TEXTURE_SWIZZLE:
173 case PIPE_CAP_TEXTURE_SHADOW_MAP:
174 case PIPE_CAP_NPOT_TEXTURES:
175 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
176 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
177 case PIPE_CAP_ANISOTROPIC_FILTER:
178 case PIPE_CAP_SEAMLESS_CUBE_MAP:
179 case PIPE_CAP_CUBE_MAP_ARRAY:
180 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
181 case PIPE_CAP_TEXTURE_MULTISAMPLE:
182 case PIPE_CAP_TWO_SIDED_STENCIL:
183 case PIPE_CAP_DEPTH_CLIP_DISABLE:
184 case PIPE_CAP_POINT_SPRITE:
185 case PIPE_CAP_TGSI_TEXCOORD:
186 case PIPE_CAP_SM3:
187 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
188 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
189 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
190 case PIPE_CAP_QUERY_TIMESTAMP:
191 case PIPE_CAP_QUERY_TIME_ELAPSED:
192 case PIPE_CAP_OCCLUSION_QUERY:
193 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
194 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
195 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
196 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
197 case PIPE_CAP_INDEP_BLEND_ENABLE:
198 case PIPE_CAP_INDEP_BLEND_FUNC:
199 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
200 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
201 case PIPE_CAP_PRIMITIVE_RESTART:
202 case PIPE_CAP_TGSI_INSTANCEID:
203 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
204 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
205 case PIPE_CAP_CONDITIONAL_RENDER:
206 case PIPE_CAP_TEXTURE_BARRIER:
207 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
208 case PIPE_CAP_START_INSTANCE:
209 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
210 case PIPE_CAP_DRAW_INDIRECT:
211 case PIPE_CAP_USER_CONSTANT_BUFFERS:
212 case PIPE_CAP_USER_VERTEX_BUFFERS:
213 case PIPE_CAP_TEXTURE_QUERY_LOD:
214 case PIPE_CAP_SAMPLE_SHADING:
215 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
216 case PIPE_CAP_TEXTURE_GATHER_SM5:
217 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
218 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
219 case PIPE_CAP_SAMPLER_VIEW_TARGET:
220 case PIPE_CAP_CLIP_HALFZ:
221 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
222 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
223 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
224 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
225 case PIPE_CAP_DEPTH_BOUNDS_TEST:
226 case PIPE_CAP_TGSI_TXQS:
227 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
228 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
229 case PIPE_CAP_SHAREABLE_SHADERS:
230 case PIPE_CAP_CLEAR_TEXTURE:
231 case PIPE_CAP_DRAW_PARAMETERS:
232 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
233 case PIPE_CAP_MULTI_DRAW_INDIRECT:
234 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
235 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
236 case PIPE_CAP_QUERY_BUFFER_OBJECT:
237 case PIPE_CAP_INVALIDATE_BUFFER:
238 case PIPE_CAP_STRING_MARKER:
239 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
240 case PIPE_CAP_CULL_DISTANCE:
241 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
242 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
243 case PIPE_CAP_TGSI_VOTE:
244 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
245 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
246 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
247 case PIPE_CAP_DOUBLES:
248 case PIPE_CAP_INT64:
249 case PIPE_CAP_TGSI_TEX_TXF_LZ:
250 case PIPE_CAP_TGSI_CLOCK:
251 return 1;
252 case PIPE_CAP_COMPUTE:
253 return (class_3d < GP100_3D_CLASS);
254 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
255 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
256 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
257 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
258 case PIPE_CAP_TGSI_FS_FBFETCH:
259 return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
260 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
261 return class_3d >= GM200_3D_CLASS;
262
263 /* unsupported caps */
264 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
265 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
266 case PIPE_CAP_SHADER_STENCIL_EXPORT:
267 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
268 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
269 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
270 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
271 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
272 case PIPE_CAP_FAKE_SW_MSAA:
273 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
274 case PIPE_CAP_VERTEXID_NOBASE:
275 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
276 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
277 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
278 case PIPE_CAP_GENERATE_MIPMAP:
279 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
280 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
281 case PIPE_CAP_QUERY_MEMORY_INFO:
282 case PIPE_CAP_PCI_GROUP:
283 case PIPE_CAP_PCI_BUS:
284 case PIPE_CAP_PCI_DEVICE:
285 case PIPE_CAP_PCI_FUNCTION:
286 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
287 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
288 case PIPE_CAP_NATIVE_FENCE_FD:
289 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
290 case PIPE_CAP_INT64_DIVMOD:
291 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
292 case PIPE_CAP_TGSI_BALLOT:
293 return 0;
294
295 case PIPE_CAP_VENDOR_ID:
296 return 0x10de;
297 case PIPE_CAP_DEVICE_ID: {
298 uint64_t device_id;
299 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
300 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
301 return -1;
302 }
303 return device_id;
304 }
305 case PIPE_CAP_ACCELERATED:
306 return 1;
307 case PIPE_CAP_VIDEO_MEMORY:
308 return dev->vram_size >> 20;
309 case PIPE_CAP_UMA:
310 return 0;
311 }
312
313 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
314 return 0;
315 }
316
317 static int
318 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
319 enum pipe_shader_type shader,
320 enum pipe_shader_cap param)
321 {
322 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
323
324 switch (shader) {
325 case PIPE_SHADER_VERTEX:
326 case PIPE_SHADER_GEOMETRY:
327 case PIPE_SHADER_FRAGMENT:
328 case PIPE_SHADER_COMPUTE:
329 case PIPE_SHADER_TESS_CTRL:
330 case PIPE_SHADER_TESS_EVAL:
331 break;
332 default:
333 return 0;
334 }
335
336 switch (param) {
337 case PIPE_SHADER_CAP_PREFERRED_IR:
338 return PIPE_SHADER_IR_TGSI;
339 case PIPE_SHADER_CAP_SUPPORTED_IRS:
340 return 1 << PIPE_SHADER_IR_TGSI;
341 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
342 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
343 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
344 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
345 return 16384;
346 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
347 return 16;
348 case PIPE_SHADER_CAP_MAX_INPUTS:
349 if (shader == PIPE_SHADER_VERTEX)
350 return 32;
351 /* NOTE: These only count our slots for GENERIC varyings.
352 * The address space may be larger, but the actual hard limit seems to be
353 * less than what the address space layout permits, so don't add TEXCOORD,
354 * COLOR, etc. here.
355 */
356 if (shader == PIPE_SHADER_FRAGMENT)
357 return 0x1f0 / 16;
358 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
359 * and excludes 0x60 per-patch inputs.
360 */
361 return 0x200 / 16;
362 case PIPE_SHADER_CAP_MAX_OUTPUTS:
363 return 32;
364 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
365 return 65536;
366 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
367 return NVC0_MAX_PIPE_CONSTBUFS;
368 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
369 return shader != PIPE_SHADER_FRAGMENT;
370 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
371 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
372 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
373 return 1;
374 case PIPE_SHADER_CAP_MAX_TEMPS:
375 return NVC0_CAP_MAX_PROGRAM_TEMPS;
376 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
377 return 1;
378 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
379 return 1;
380 case PIPE_SHADER_CAP_SUBROUTINES:
381 return 1;
382 case PIPE_SHADER_CAP_INTEGERS:
383 return 1;
384 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
385 return 1;
386 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
387 return 1;
388 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
389 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
390 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
391 return 0;
392 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
393 return NVC0_MAX_BUFFERS;
394 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
395 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
396 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
397 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
398 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
399 return 32;
400 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
401 if (class_3d >= NVE4_3D_CLASS)
402 return NVC0_MAX_IMAGES;
403 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
404 return NVC0_MAX_IMAGES;
405 return 0;
406 default:
407 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
408 return 0;
409 }
410 }
411
412 static float
413 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
414 {
415 switch (param) {
416 case PIPE_CAPF_MAX_LINE_WIDTH:
417 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
418 return 10.0f;
419 case PIPE_CAPF_MAX_POINT_WIDTH:
420 return 63.0f;
421 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
422 return 63.375f;
423 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
424 return 16.0f;
425 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
426 return 15.0f;
427 case PIPE_CAPF_GUARD_BAND_LEFT:
428 case PIPE_CAPF_GUARD_BAND_TOP:
429 return 0.0f;
430 case PIPE_CAPF_GUARD_BAND_RIGHT:
431 case PIPE_CAPF_GUARD_BAND_BOTTOM:
432 return 0.0f; /* that or infinity */
433 }
434
435 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
436 return 0.0f;
437 }
438
439 static int
440 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
441 enum pipe_shader_ir ir_type,
442 enum pipe_compute_cap param, void *data)
443 {
444 struct nvc0_screen *screen = nvc0_screen(pscreen);
445 const uint16_t obj_class = screen->compute->oclass;
446
447 #define RET(x) do { \
448 if (data) \
449 memcpy(data, x, sizeof(x)); \
450 return sizeof(x); \
451 } while (0)
452
453 switch (param) {
454 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
455 RET((uint64_t []) { 3 });
456 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
457 if (obj_class >= NVE4_COMPUTE_CLASS) {
458 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
459 } else {
460 RET(((uint64_t []) { 65535, 65535, 65535 }));
461 }
462 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
463 RET(((uint64_t []) { 1024, 1024, 64 }));
464 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
465 RET((uint64_t []) { 1024 });
466 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
467 if (obj_class >= NVE4_COMPUTE_CLASS) {
468 RET((uint64_t []) { 1024 });
469 } else {
470 RET((uint64_t []) { 512 });
471 }
472 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
473 RET((uint64_t []) { 1ULL << 40 });
474 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
475 switch (obj_class) {
476 case GM200_COMPUTE_CLASS:
477 RET((uint64_t []) { 96 << 10 });
478 break;
479 case GM107_COMPUTE_CLASS:
480 RET((uint64_t []) { 64 << 10 });
481 break;
482 default:
483 RET((uint64_t []) { 48 << 10 });
484 break;
485 }
486 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
487 RET((uint64_t []) { 512 << 10 });
488 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
489 RET((uint64_t []) { 4096 });
490 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
491 RET((uint32_t []) { 32 });
492 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
493 RET((uint64_t []) { 1ULL << 40 });
494 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
495 RET((uint32_t []) { 0 });
496 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
497 RET((uint32_t []) { screen->mp_count_compute });
498 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
499 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
500 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
501 RET((uint32_t []) { 64 });
502 default:
503 return 0;
504 }
505
506 #undef RET
507 }
508
509 static void
510 nvc0_screen_destroy(struct pipe_screen *pscreen)
511 {
512 struct nvc0_screen *screen = nvc0_screen(pscreen);
513
514 if (!nouveau_drm_screen_unref(&screen->base))
515 return;
516
517 if (screen->base.fence.current) {
518 struct nouveau_fence *current = NULL;
519
520 /* nouveau_fence_wait will create a new current fence, so wait on the
521 * _current_ one, and remove both.
522 */
523 nouveau_fence_ref(screen->base.fence.current, &current);
524 nouveau_fence_wait(current, NULL);
525 nouveau_fence_ref(NULL, &current);
526 nouveau_fence_ref(NULL, &screen->base.fence.current);
527 }
528 if (screen->base.pushbuf)
529 screen->base.pushbuf->user_priv = NULL;
530
531 if (screen->blitter)
532 nvc0_blitter_destroy(screen);
533 if (screen->pm.prog) {
534 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
535 nvc0_program_destroy(NULL, screen->pm.prog);
536 FREE(screen->pm.prog);
537 }
538
539 nouveau_bo_ref(NULL, &screen->text);
540 nouveau_bo_ref(NULL, &screen->uniform_bo);
541 nouveau_bo_ref(NULL, &screen->tls);
542 nouveau_bo_ref(NULL, &screen->txc);
543 nouveau_bo_ref(NULL, &screen->fence.bo);
544 nouveau_bo_ref(NULL, &screen->poly_cache);
545
546 nouveau_heap_destroy(&screen->lib_code);
547 nouveau_heap_destroy(&screen->text_heap);
548
549 FREE(screen->default_tsc);
550 FREE(screen->tic.entries);
551
552 nouveau_object_del(&screen->eng3d);
553 nouveau_object_del(&screen->eng2d);
554 nouveau_object_del(&screen->m2mf);
555 nouveau_object_del(&screen->compute);
556 nouveau_object_del(&screen->nvsw);
557
558 nouveau_screen_fini(&screen->base);
559
560 FREE(screen);
561 }
562
563 static int
564 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
565 unsigned size, const uint32_t *data)
566 {
567 struct nouveau_pushbuf *push = screen->base.pushbuf;
568
569 size /= 4;
570
571 assert((pos + size) <= 0x800);
572
573 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
574 PUSH_DATA (push, (m - 0x3800) / 8);
575 PUSH_DATA (push, pos);
576 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
577 PUSH_DATA (push, pos);
578 PUSH_DATAp(push, data, size);
579
580 return pos + size;
581 }
582
583 static void
584 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
585 {
586 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
587 PUSH_DATA (push, 0xff);
588 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
589 PUSH_DATA (push, 0xff);
590 PUSH_DATA (push, 0xff);
591 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
592 PUSH_DATA (push, 0xff);
593 PUSH_DATA (push, 0xff);
594 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
595 PUSH_DATA (push, 0x3f);
596
597 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
598 PUSH_DATA (push, (3 << 16) | 3);
599 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
600 PUSH_DATA (push, (2 << 16) | 2);
601
602 if (obj_class < GM107_3D_CLASS) {
603 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
604 PUSH_DATA (push, 0);
605 }
606 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
607 PUSH_DATA (push, 0x10);
608 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
609 PUSH_DATA (push, 0x10);
610 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
611 PUSH_DATA (push, 0x10);
612 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
613 PUSH_DATA (push, 0x10);
614 PUSH_DATA (push, 0x10);
615 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
616 PUSH_DATA (push, 0x10);
617 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
618 PUSH_DATA (push, 0xe);
619
620 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
621 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
622 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
623 PUSH_DATA (push, 0);
624 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
625 PUSH_DATA (push, 3);
626
627 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
628 PUSH_DATA (push, 0x3fffff);
629 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
630 PUSH_DATA (push, 1);
631 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
632 PUSH_DATA (push, 1);
633
634 if (obj_class < GM107_3D_CLASS) {
635 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
636 PUSH_DATA (push, 3);
637
638 if (obj_class >= NVE4_3D_CLASS) {
639 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
640 PUSH_DATA (push, 1);
641 }
642 }
643
644 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
645 * are supposed to do */
646 }
647
648 static void
649 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
650 {
651 struct nvc0_screen *screen = nvc0_screen(pscreen);
652 struct nouveau_pushbuf *push = screen->base.pushbuf;
653
654 /* we need to do it after possible flush in MARK_RING */
655 *sequence = ++screen->base.fence.sequence;
656
657 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
658 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
659 PUSH_DATAh(push, screen->fence.bo->offset);
660 PUSH_DATA (push, screen->fence.bo->offset);
661 PUSH_DATA (push, *sequence);
662 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
663 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
664 }
665
666 static u32
667 nvc0_screen_fence_update(struct pipe_screen *pscreen)
668 {
669 struct nvc0_screen *screen = nvc0_screen(pscreen);
670 return screen->fence.map[0];
671 }
672
673 static int
674 nvc0_screen_init_compute(struct nvc0_screen *screen)
675 {
676 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
677
678 switch (screen->base.device->chipset & ~0xf) {
679 case 0xc0:
680 case 0xd0:
681 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
682 case 0xe0:
683 case 0xf0:
684 case 0x100:
685 case 0x110:
686 case 0x120:
687 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
688 case 0x130:
689 return 0;
690 default:
691 return -1;
692 }
693 }
694
695 static int
696 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
697 uint32_t lpos, uint32_t lneg, uint32_t cstack)
698 {
699 struct nouveau_bo *bo = NULL;
700 int ret;
701 uint64_t size = (lpos + lneg) * 32 + cstack;
702
703 if (size >= (1 << 20)) {
704 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
705 return -1;
706 }
707
708 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
709 size = align(size, 0x8000);
710 size *= screen->mp_count;
711
712 size = align(size, 1 << 17);
713
714 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
715 NULL, &bo);
716 if (ret)
717 return ret;
718 nouveau_bo_ref(NULL, &screen->tls);
719 screen->tls = bo;
720 return 0;
721 }
722
723 int
724 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
725 {
726 struct nouveau_pushbuf *push = screen->base.pushbuf;
727 struct nouveau_bo *bo;
728 int ret;
729
730 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
731 1 << 17, size, NULL, &bo);
732 if (ret)
733 return ret;
734
735 nouveau_bo_ref(NULL, &screen->text);
736 screen->text = bo;
737
738 nouveau_heap_destroy(&screen->lib_code);
739 nouveau_heap_destroy(&screen->text_heap);
740
741 /* XXX: getting a page fault at the end of the code buffer every few
742 * launches, don't use the last 256 bytes to work around them - prefetch ?
743 */
744 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
745
746 /* update the code segment setup */
747 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
748 PUSH_DATAh(push, screen->text->offset);
749 PUSH_DATA (push, screen->text->offset);
750 if (screen->compute) {
751 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
752 PUSH_DATAh(push, screen->text->offset);
753 PUSH_DATA (push, screen->text->offset);
754 }
755
756 return 0;
757 }
758
759 #define FAIL_SCREEN_INIT(str, err) \
760 do { \
761 NOUVEAU_ERR(str, err); \
762 goto fail; \
763 } while(0)
764
765 struct nouveau_screen *
766 nvc0_screen_create(struct nouveau_device *dev)
767 {
768 struct nvc0_screen *screen;
769 struct pipe_screen *pscreen;
770 struct nouveau_object *chan;
771 struct nouveau_pushbuf *push;
772 uint64_t value;
773 uint32_t obj_class;
774 uint32_t flags;
775 int ret;
776 unsigned i;
777
778 switch (dev->chipset & ~0xf) {
779 case 0xc0:
780 case 0xd0:
781 case 0xe0:
782 case 0xf0:
783 case 0x100:
784 case 0x110:
785 case 0x120:
786 case 0x130:
787 break;
788 default:
789 return NULL;
790 }
791
792 screen = CALLOC_STRUCT(nvc0_screen);
793 if (!screen)
794 return NULL;
795 pscreen = &screen->base.base;
796 pscreen->destroy = nvc0_screen_destroy;
797
798 ret = nouveau_screen_init(&screen->base, dev);
799 if (ret)
800 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
801 chan = screen->base.channel;
802 push = screen->base.pushbuf;
803 push->user_priv = screen;
804 push->rsvd_kick = 5;
805
806 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
807 PIPE_BIND_SHADER_BUFFER |
808 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
809 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
810 screen->base.sysmem_bindings |=
811 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
812
813 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
814 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
815 screen->base.vidmem_bindings = 0;
816 }
817
818 pscreen->context_create = nvc0_create;
819 pscreen->is_format_supported = nvc0_screen_is_format_supported;
820 pscreen->get_param = nvc0_screen_get_param;
821 pscreen->get_shader_param = nvc0_screen_get_shader_param;
822 pscreen->get_paramf = nvc0_screen_get_paramf;
823 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
824 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
825
826 nvc0_screen_init_resource_functions(pscreen);
827
828 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
829 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
830
831 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
832 if (screen->base.drm->version >= 0x01000202)
833 flags |= NOUVEAU_BO_COHERENT;
834
835 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
836 if (ret)
837 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
838 nouveau_bo_map(screen->fence.bo, 0, NULL);
839 screen->fence.map = screen->fence.bo->map;
840 screen->base.fence.emit = nvc0_screen_fence_emit;
841 screen->base.fence.update = nvc0_screen_fence_update;
842
843
844 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
845 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
846 if (ret)
847 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
848
849 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
850 PUSH_DATA (push, screen->nvsw->handle);
851
852 switch (dev->chipset & ~0xf) {
853 case 0x130:
854 case 0x120:
855 case 0x110:
856 case 0x100:
857 case 0xf0:
858 obj_class = NVF0_P2MF_CLASS;
859 break;
860 case 0xe0:
861 obj_class = NVE4_P2MF_CLASS;
862 break;
863 default:
864 obj_class = NVC0_M2MF_CLASS;
865 break;
866 }
867 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
868 &screen->m2mf);
869 if (ret)
870 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
871
872 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
873 PUSH_DATA (push, screen->m2mf->oclass);
874 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
875 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
876 PUSH_DATA (push, 0xa0b5);
877 }
878
879 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
880 &screen->eng2d);
881 if (ret)
882 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
883
884 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
885 PUSH_DATA (push, screen->eng2d->oclass);
886 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
887 PUSH_DATA (push, 0);
888 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
889 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
890 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
891 PUSH_DATA (push, 0);
892 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
893 PUSH_DATA (push, 0);
894 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
895 PUSH_DATA (push, 0x3f);
896 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
897 PUSH_DATA (push, 1);
898 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
899 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
900
901 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
902 PUSH_DATAh(push, screen->fence.bo->offset + 16);
903 PUSH_DATA (push, screen->fence.bo->offset + 16);
904
905 switch (dev->chipset & ~0xf) {
906 case 0x130:
907 switch (dev->chipset) {
908 case 0x130:
909 obj_class = GP100_3D_CLASS;
910 break;
911 default:
912 obj_class = GP102_3D_CLASS;
913 break;
914 }
915 break;
916 case 0x120:
917 obj_class = GM200_3D_CLASS;
918 break;
919 case 0x110:
920 obj_class = GM107_3D_CLASS;
921 break;
922 case 0x100:
923 case 0xf0:
924 obj_class = NVF0_3D_CLASS;
925 break;
926 case 0xe0:
927 switch (dev->chipset) {
928 case 0xea:
929 obj_class = NVEA_3D_CLASS;
930 break;
931 default:
932 obj_class = NVE4_3D_CLASS;
933 break;
934 }
935 break;
936 case 0xd0:
937 obj_class = NVC8_3D_CLASS;
938 break;
939 case 0xc0:
940 default:
941 switch (dev->chipset) {
942 case 0xc8:
943 obj_class = NVC8_3D_CLASS;
944 break;
945 case 0xc1:
946 obj_class = NVC1_3D_CLASS;
947 break;
948 default:
949 obj_class = NVC0_3D_CLASS;
950 break;
951 }
952 break;
953 }
954 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
955 &screen->eng3d);
956 if (ret)
957 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
958 screen->base.class_3d = obj_class;
959
960 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
961 PUSH_DATA (push, screen->eng3d->oclass);
962
963 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
964 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
965
966 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
967 /* kill shaders after about 1 second (at 100 MHz) */
968 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
969 PUSH_DATA (push, 0x17);
970 }
971
972 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
973 screen->base.drm->version >= 0x01000101);
974 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
975 for (i = 0; i < 8; ++i)
976 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
977
978 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
979 PUSH_DATA (push, 1);
980
981 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
982 PUSH_DATA (push, 0);
983 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
984 PUSH_DATA (push, 0);
985 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
986 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
987 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
988 PUSH_DATA (push, 0);
989 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
990 PUSH_DATA (push, 1);
991 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
992 PUSH_DATA (push, 1);
993 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
994 PUSH_DATA (push, 1);
995 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
996 PUSH_DATA (push, 0);
997 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
998 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
999 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1000 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1001 } else {
1002 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1003 PUSH_DATA (push, 15);
1004 }
1005 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1006 PUSH_DATA (push, 8); /* 128 */
1007 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1008 PUSH_DATA (push, 1);
1009 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1010 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1011 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1012 }
1013
1014 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1015
1016 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1017 if (ret)
1018 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1019
1020 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1021 &screen->uniform_bo);
1022 if (ret)
1023 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1024
1025 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1026
1027 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1028 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1029 PUSH_DATA (push, 256);
1030 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1031 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1032 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1033 PUSH_DATA (push, 0);
1034 PUSH_DATAf(push, 0.0f);
1035 PUSH_DATAf(push, 0.0f);
1036 PUSH_DATAf(push, 0.0f);
1037 PUSH_DATAf(push, 0.0f);
1038 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1039 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1040 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1041
1042 if (screen->base.drm->version >= 0x01000101) {
1043 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1044 if (ret)
1045 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1046 } else {
1047 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1048 value = (8 << 8) | 4;
1049 else
1050 value = (16 << 8) | 4;
1051 }
1052 screen->gpc_count = value & 0x000000ff;
1053 screen->mp_count = value >> 8;
1054 screen->mp_count_compute = screen->mp_count;
1055
1056 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1057 if (ret)
1058 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1059
1060 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1061 PUSH_DATAh(push, screen->tls->offset);
1062 PUSH_DATA (push, screen->tls->offset);
1063 PUSH_DATA (push, screen->tls->size >> 32);
1064 PUSH_DATA (push, screen->tls->size);
1065 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1066 PUSH_DATA (push, 0);
1067 /* Reduce likelihood of collision with real buffers by placing the hole at
1068 * the top of the 4G area. This will have to be dealt with for real
1069 * eventually by blocking off that area from the VM.
1070 */
1071 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1072 PUSH_DATA (push, 0xff << 24);
1073
1074 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1075 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1076 &screen->poly_cache);
1077 if (ret)
1078 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1079
1080 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1081 PUSH_DATAh(push, screen->poly_cache->offset);
1082 PUSH_DATA (push, screen->poly_cache->offset);
1083 PUSH_DATA (push, 3);
1084 }
1085
1086 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1087 &screen->txc);
1088 if (ret)
1089 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1090
1091 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1092 PUSH_DATAh(push, screen->txc->offset);
1093 PUSH_DATA (push, screen->txc->offset);
1094 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1095 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1096 screen->tic.maxwell = true;
1097 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1098 screen->tic.maxwell =
1099 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1100 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1101 }
1102 }
1103
1104 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1105 PUSH_DATAh(push, screen->txc->offset + 65536);
1106 PUSH_DATA (push, screen->txc->offset + 65536);
1107 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1108
1109 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1110 PUSH_DATA (push, 0);
1111 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1112 PUSH_DATA (push, 0);
1113 PUSH_DATA (push, 0);
1114 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1115 PUSH_DATA (push, 0x3f);
1116
1117 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1118 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1119 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1120 for (i = 0; i < 8 * 2; ++i)
1121 PUSH_DATA(push, 0);
1122 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1123 PUSH_DATA (push, 0);
1124 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1125 PUSH_DATA (push, 0);
1126
1127 /* neither scissors, viewport nor stencil mask should affect clears */
1128 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1129 PUSH_DATA (push, 0);
1130
1131 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1132 PUSH_DATA (push, 1);
1133 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1134 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1135 PUSH_DATAf(push, 0.0f);
1136 PUSH_DATAf(push, 1.0f);
1137 }
1138 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1139 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1140
1141 /* We use scissors instead of exact view volume clipping,
1142 * so they're always enabled.
1143 */
1144 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1145 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1146 PUSH_DATA (push, 1);
1147 PUSH_DATA (push, 8192 << 16);
1148 PUSH_DATA (push, 8192 << 16);
1149 }
1150
1151 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1152
1153 i = 0;
1154 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1155 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1156 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1157 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1158 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1159 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1160 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1161 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1162 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1163 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1164 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1165 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1166 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1167
1168 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1169 PUSH_DATA (push, 1);
1170 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1171 PUSH_DATA (push, 1);
1172 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1173 PUSH_DATA (push, 0x40);
1174 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1175 PUSH_DATA (push, 0);
1176 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1177 PUSH_DATA (push, 0x30);
1178 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1179 PUSH_DATA (push, 3);
1180 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1181 PUSH_DATA (push, 0x20);
1182 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1183 PUSH_DATA (push, 0x00);
1184 screen->save_state.patch_vertices = 3;
1185
1186 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1187 PUSH_DATA (push, 0);
1188 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1189 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1190
1191 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1192
1193 if (nvc0_screen_init_compute(screen))
1194 goto fail;
1195
1196 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1197 for (i = 0; i < 5; ++i) {
1198 /* TIC and TSC entries for each unit (nve4+ only) */
1199 /* auxiliary constants (6 user clip planes, base instance id) */
1200 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1201 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1202 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1203 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1204 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1205 PUSH_DATA (push, (15 << 4) | 1);
1206 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1207 unsigned j;
1208 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1209 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1210 for (j = 0; j < 8; ++j)
1211 PUSH_DATA(push, j);
1212 } else {
1213 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1214 PUSH_DATA (push, 0x54);
1215 }
1216
1217 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1218 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1219 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1220 PUSH_DATA (push, 0); /* 0 */
1221 PUSH_DATA (push, 0);
1222 PUSH_DATA (push, 1); /* 1 */
1223 PUSH_DATA (push, 0);
1224 PUSH_DATA (push, 0); /* 2 */
1225 PUSH_DATA (push, 1);
1226 PUSH_DATA (push, 1); /* 3 */
1227 PUSH_DATA (push, 1);
1228 PUSH_DATA (push, 2); /* 4 */
1229 PUSH_DATA (push, 0);
1230 PUSH_DATA (push, 3); /* 5 */
1231 PUSH_DATA (push, 0);
1232 PUSH_DATA (push, 2); /* 6 */
1233 PUSH_DATA (push, 1);
1234 PUSH_DATA (push, 3); /* 7 */
1235 PUSH_DATA (push, 1);
1236 }
1237 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1238 PUSH_DATA (push, 0);
1239
1240 PUSH_KICK (push);
1241
1242 screen->tic.entries = CALLOC(4096, sizeof(void *));
1243 screen->tsc.entries = screen->tic.entries + 2048;
1244
1245 if (!nvc0_blitter_create(screen))
1246 goto fail;
1247
1248 screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1249 screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1250
1251 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1252
1253 return &screen->base;
1254
1255 fail:
1256 screen->base.base.context_create = NULL;
1257 return &screen->base;
1258 }
1259
1260 int
1261 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1262 {
1263 int i = screen->tic.next;
1264
1265 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1266 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1267
1268 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1269
1270 if (screen->tic.entries[i])
1271 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1272
1273 screen->tic.entries[i] = entry;
1274 return i;
1275 }
1276
1277 int
1278 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1279 {
1280 int i = screen->tsc.next;
1281
1282 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1283 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1284
1285 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1286
1287 if (screen->tsc.entries[i])
1288 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1289
1290 screen->tsc.entries[i] = entry;
1291 return i;
1292 }