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84dbd69b8a514b4fe7001751cc490b3b697822b3
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
115 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
116 case PIPE_CAP_MAX_VIEWPORTS:
117 return NVC0_MAX_VIEWPORTS;
118 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
119 return 4;
120 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
121 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
122 case PIPE_CAP_ENDIANNESS:
123 return PIPE_ENDIAN_LITTLE;
124 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
125 return 30;
126
127 /* supported caps */
128 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
129 case PIPE_CAP_TEXTURE_SWIZZLE:
130 case PIPE_CAP_TEXTURE_SHADOW_MAP:
131 case PIPE_CAP_NPOT_TEXTURES:
132 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
133 case PIPE_CAP_ANISOTROPIC_FILTER:
134 case PIPE_CAP_SEAMLESS_CUBE_MAP:
135 case PIPE_CAP_CUBE_MAP_ARRAY:
136 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
137 case PIPE_CAP_TEXTURE_MULTISAMPLE:
138 case PIPE_CAP_TWO_SIDED_STENCIL:
139 case PIPE_CAP_DEPTH_CLIP_DISABLE:
140 case PIPE_CAP_POINT_SPRITE:
141 case PIPE_CAP_TGSI_TEXCOORD:
142 case PIPE_CAP_SM3:
143 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
144 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
145 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
146 case PIPE_CAP_QUERY_TIMESTAMP:
147 case PIPE_CAP_QUERY_TIME_ELAPSED:
148 case PIPE_CAP_OCCLUSION_QUERY:
149 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
150 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
151 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
152 case PIPE_CAP_INDEP_BLEND_ENABLE:
153 case PIPE_CAP_INDEP_BLEND_FUNC:
154 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
155 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
156 case PIPE_CAP_PRIMITIVE_RESTART:
157 case PIPE_CAP_TGSI_INSTANCEID:
158 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
160 case PIPE_CAP_CONDITIONAL_RENDER:
161 case PIPE_CAP_TEXTURE_BARRIER:
162 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
163 case PIPE_CAP_START_INSTANCE:
164 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
165 case PIPE_CAP_DRAW_INDIRECT:
166 case PIPE_CAP_USER_CONSTANT_BUFFERS:
167 case PIPE_CAP_USER_INDEX_BUFFERS:
168 case PIPE_CAP_USER_VERTEX_BUFFERS:
169 case PIPE_CAP_TEXTURE_QUERY_LOD:
170 case PIPE_CAP_SAMPLE_SHADING:
171 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
172 case PIPE_CAP_TEXTURE_GATHER_SM5:
173 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
174 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
175 case PIPE_CAP_SAMPLER_VIEW_TARGET:
176 case PIPE_CAP_CLIP_HALFZ:
177 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
178 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
179 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
180 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
181 case PIPE_CAP_DEPTH_BOUNDS_TEST:
182 case PIPE_CAP_TGSI_TXQS:
183 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
184 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
185 case PIPE_CAP_SHAREABLE_SHADERS:
186 case PIPE_CAP_CLEAR_TEXTURE:
187 case PIPE_CAP_DRAW_PARAMETERS:
188 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
189 case PIPE_CAP_MULTI_DRAW_INDIRECT:
190 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
191 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
192 return 1;
193 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
194 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
195 case PIPE_CAP_COMPUTE:
196 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
197 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
198 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
199
200 /* unsupported caps */
201 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
202 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
203 case PIPE_CAP_SHADER_STENCIL_EXPORT:
204 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
205 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
206 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
207 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
208 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
209 case PIPE_CAP_FAKE_SW_MSAA:
210 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
211 case PIPE_CAP_VERTEXID_NOBASE:
212 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
213 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
214 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
215 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
216 case PIPE_CAP_INVALIDATE_BUFFER:
217 case PIPE_CAP_GENERATE_MIPMAP:
218 case PIPE_CAP_STRING_MARKER:
219 return 0;
220
221 case PIPE_CAP_VENDOR_ID:
222 return 0x10de;
223 case PIPE_CAP_DEVICE_ID: {
224 uint64_t device_id;
225 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
226 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
227 return -1;
228 }
229 return device_id;
230 }
231 case PIPE_CAP_ACCELERATED:
232 return 1;
233 case PIPE_CAP_VIDEO_MEMORY:
234 return dev->vram_size >> 20;
235 case PIPE_CAP_UMA:
236 return 0;
237 }
238
239 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
240 return 0;
241 }
242
243 static int
244 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
245 enum pipe_shader_cap param)
246 {
247 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
248
249 switch (shader) {
250 case PIPE_SHADER_VERTEX:
251 case PIPE_SHADER_GEOMETRY:
252 case PIPE_SHADER_FRAGMENT:
253 break;
254 case PIPE_SHADER_TESS_CTRL:
255 case PIPE_SHADER_TESS_EVAL:
256 if (class_3d >= GM107_3D_CLASS)
257 return 0;
258 break;
259 case PIPE_SHADER_COMPUTE:
260 if (class_3d > NVE4_3D_CLASS)
261 return 0;
262 break;
263 default:
264 return 0;
265 }
266
267 switch (param) {
268 case PIPE_SHADER_CAP_PREFERRED_IR:
269 return PIPE_SHADER_IR_TGSI;
270 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
271 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
272 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
273 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
274 return 16384;
275 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
276 return 16;
277 case PIPE_SHADER_CAP_MAX_INPUTS:
278 if (shader == PIPE_SHADER_VERTEX)
279 return 32;
280 /* NOTE: These only count our slots for GENERIC varyings.
281 * The address space may be larger, but the actual hard limit seems to be
282 * less than what the address space layout permits, so don't add TEXCOORD,
283 * COLOR, etc. here.
284 */
285 if (shader == PIPE_SHADER_FRAGMENT)
286 return 0x1f0 / 16;
287 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
288 * and excludes 0x60 per-patch inputs.
289 */
290 return 0x200 / 16;
291 case PIPE_SHADER_CAP_MAX_OUTPUTS:
292 return 32;
293 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
294 return 65536;
295 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
296 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
297 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
298 return NVC0_MAX_PIPE_CONSTBUFS;
299 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
300 return shader != PIPE_SHADER_FRAGMENT;
301 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
302 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
303 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
304 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
305 return 1;
306 case PIPE_SHADER_CAP_MAX_PREDS:
307 return 0;
308 case PIPE_SHADER_CAP_MAX_TEMPS:
309 return NVC0_CAP_MAX_PROGRAM_TEMPS;
310 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
311 return 1;
312 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
313 return 0;
314 case PIPE_SHADER_CAP_SUBROUTINES:
315 return 1;
316 case PIPE_SHADER_CAP_INTEGERS:
317 return 1;
318 case PIPE_SHADER_CAP_DOUBLES:
319 return 1;
320 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
321 return 1;
322 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
323 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
324 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
325 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
326 return 0;
327 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
328 return 16; /* would be 32 in linked (OpenGL-style) mode */
329 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
330 return 16; /* XXX not sure if more are really safe */
331 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
332 return 32;
333 default:
334 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
335 return 0;
336 }
337 }
338
339 static float
340 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
341 {
342 switch (param) {
343 case PIPE_CAPF_MAX_LINE_WIDTH:
344 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
345 return 10.0f;
346 case PIPE_CAPF_MAX_POINT_WIDTH:
347 return 63.0f;
348 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
349 return 63.375f;
350 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
351 return 16.0f;
352 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
353 return 15.0f;
354 case PIPE_CAPF_GUARD_BAND_LEFT:
355 case PIPE_CAPF_GUARD_BAND_TOP:
356 return 0.0f;
357 case PIPE_CAPF_GUARD_BAND_RIGHT:
358 case PIPE_CAPF_GUARD_BAND_BOTTOM:
359 return 0.0f; /* that or infinity */
360 }
361
362 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
363 return 0.0f;
364 }
365
366 static int
367 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
368 enum pipe_compute_cap param, void *data)
369 {
370 struct nvc0_screen *screen = nvc0_screen(pscreen);
371 const uint16_t obj_class = screen->compute->oclass;
372
373 #define RET(x) do { \
374 if (data) \
375 memcpy(data, x, sizeof(x)); \
376 return sizeof(x); \
377 } while (0)
378
379 switch (param) {
380 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
381 RET((uint64_t []) { 3 });
382 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
383 if (obj_class >= NVE4_COMPUTE_CLASS) {
384 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
385 } else {
386 RET(((uint64_t []) { 65535, 65535, 65535 }));
387 }
388 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
389 RET(((uint64_t []) { 1024, 1024, 64 }));
390 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
391 RET((uint64_t []) { 1024 });
392 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
393 RET((uint64_t []) { 1ULL << 40 });
394 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
395 RET((uint64_t []) { 48 << 10 });
396 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
397 RET((uint64_t []) { 512 << 10 });
398 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
399 RET((uint64_t []) { 4096 });
400 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
401 RET((uint32_t []) { 32 });
402 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
403 RET((uint64_t []) { 1ULL << 40 });
404 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
405 RET((uint32_t []) { 0 });
406 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
407 RET((uint32_t []) { screen->mp_count_compute });
408 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
409 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
410 default:
411 return 0;
412 }
413
414 #undef RET
415 }
416
417 static void
418 nvc0_screen_destroy(struct pipe_screen *pscreen)
419 {
420 struct nvc0_screen *screen = nvc0_screen(pscreen);
421
422 if (!nouveau_drm_screen_unref(&screen->base))
423 return;
424
425 if (screen->base.fence.current) {
426 struct nouveau_fence *current = NULL;
427
428 /* nouveau_fence_wait will create a new current fence, so wait on the
429 * _current_ one, and remove both.
430 */
431 nouveau_fence_ref(screen->base.fence.current, &current);
432 nouveau_fence_wait(current, NULL);
433 nouveau_fence_ref(NULL, &current);
434 nouveau_fence_ref(NULL, &screen->base.fence.current);
435 }
436 if (screen->base.pushbuf)
437 screen->base.pushbuf->user_priv = NULL;
438
439 if (screen->blitter)
440 nvc0_blitter_destroy(screen);
441 if (screen->pm.prog) {
442 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
443 nvc0_program_destroy(NULL, screen->pm.prog);
444 FREE(screen->pm.prog);
445 }
446
447 nouveau_bo_ref(NULL, &screen->text);
448 nouveau_bo_ref(NULL, &screen->uniform_bo);
449 nouveau_bo_ref(NULL, &screen->tls);
450 nouveau_bo_ref(NULL, &screen->txc);
451 nouveau_bo_ref(NULL, &screen->fence.bo);
452 nouveau_bo_ref(NULL, &screen->poly_cache);
453 nouveau_bo_ref(NULL, &screen->parm);
454
455 nouveau_heap_destroy(&screen->lib_code);
456 nouveau_heap_destroy(&screen->text_heap);
457
458 FREE(screen->tic.entries);
459
460 nouveau_object_del(&screen->eng3d);
461 nouveau_object_del(&screen->eng2d);
462 nouveau_object_del(&screen->m2mf);
463 nouveau_object_del(&screen->compute);
464 nouveau_object_del(&screen->nvsw);
465
466 nouveau_screen_fini(&screen->base);
467
468 FREE(screen);
469 }
470
471 static int
472 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
473 unsigned size, const uint32_t *data)
474 {
475 struct nouveau_pushbuf *push = screen->base.pushbuf;
476
477 size /= 4;
478
479 assert((pos + size) <= 0x800);
480
481 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
482 PUSH_DATA (push, (m - 0x3800) / 8);
483 PUSH_DATA (push, pos);
484 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
485 PUSH_DATA (push, pos);
486 PUSH_DATAp(push, data, size);
487
488 return pos + size;
489 }
490
491 static void
492 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
493 {
494 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
495 PUSH_DATA (push, 0xff);
496 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
497 PUSH_DATA (push, 0xff);
498 PUSH_DATA (push, 0xff);
499 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
500 PUSH_DATA (push, 0xff);
501 PUSH_DATA (push, 0xff);
502 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
503 PUSH_DATA (push, 0x3f);
504
505 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
506 PUSH_DATA (push, (3 << 16) | 3);
507 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
508 PUSH_DATA (push, (2 << 16) | 2);
509
510 if (obj_class < GM107_3D_CLASS) {
511 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
512 PUSH_DATA (push, 0);
513 }
514 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
515 PUSH_DATA (push, 0x10);
516 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
517 PUSH_DATA (push, 0x10);
518 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
519 PUSH_DATA (push, 0x10);
520 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
521 PUSH_DATA (push, 0x10);
522 PUSH_DATA (push, 0x10);
523 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
524 PUSH_DATA (push, 0x10);
525 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
526 PUSH_DATA (push, 0xe);
527
528 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
529 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
530 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
531 PUSH_DATA (push, 0);
532 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
533 PUSH_DATA (push, 3);
534
535 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
536 PUSH_DATA (push, 0x3fffff);
537 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
538 PUSH_DATA (push, 1);
539 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
540 PUSH_DATA (push, 1);
541
542 if (obj_class < GM107_3D_CLASS) {
543 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
544 PUSH_DATA (push, 3);
545
546 if (obj_class >= NVE4_3D_CLASS) {
547 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
548 PUSH_DATA (push, 1);
549 }
550 }
551
552 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
553 * are supposed to do */
554 }
555
556 static void
557 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
558 {
559 struct nvc0_screen *screen = nvc0_screen(pscreen);
560 struct nouveau_pushbuf *push = screen->base.pushbuf;
561
562 /* we need to do it after possible flush in MARK_RING */
563 *sequence = ++screen->base.fence.sequence;
564
565 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
566 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
567 PUSH_DATAh(push, screen->fence.bo->offset);
568 PUSH_DATA (push, screen->fence.bo->offset);
569 PUSH_DATA (push, *sequence);
570 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
571 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
572 }
573
574 static u32
575 nvc0_screen_fence_update(struct pipe_screen *pscreen)
576 {
577 struct nvc0_screen *screen = nvc0_screen(pscreen);
578 return screen->fence.map[0];
579 }
580
581 static int
582 nvc0_screen_init_compute(struct nvc0_screen *screen)
583 {
584 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
585
586 switch (screen->base.device->chipset & ~0xf) {
587 case 0xc0:
588 case 0xd0:
589 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
590 case 0xe0:
591 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
592 case 0xf0:
593 case 0x100:
594 case 0x110:
595 return 0;
596 default:
597 return -1;
598 }
599 }
600
601 bool
602 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
603 uint32_t lpos, uint32_t lneg, uint32_t cstack)
604 {
605 struct nouveau_bo *bo = NULL;
606 int ret;
607 uint64_t size = (lpos + lneg) * 32 + cstack;
608
609 if (size >= (1 << 20)) {
610 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
611 return false;
612 }
613
614 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
615 size = align(size, 0x8000);
616 size *= screen->mp_count;
617
618 size = align(size, 1 << 17);
619
620 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
621 NULL, &bo);
622 if (ret) {
623 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
624 return false;
625 }
626 nouveau_bo_ref(NULL, &screen->tls);
627 screen->tls = bo;
628 return true;
629 }
630
631 #define FAIL_SCREEN_INIT(str, err) \
632 do { \
633 NOUVEAU_ERR(str, err); \
634 goto fail; \
635 } while(0)
636
637 struct nouveau_screen *
638 nvc0_screen_create(struct nouveau_device *dev)
639 {
640 struct nvc0_screen *screen;
641 struct pipe_screen *pscreen;
642 struct nouveau_object *chan;
643 struct nouveau_pushbuf *push;
644 uint64_t value;
645 uint32_t obj_class;
646 uint32_t flags;
647 int ret;
648 unsigned i;
649
650 switch (dev->chipset & ~0xf) {
651 case 0xc0:
652 case 0xd0:
653 case 0xe0:
654 case 0xf0:
655 case 0x100:
656 case 0x110:
657 break;
658 default:
659 return NULL;
660 }
661
662 screen = CALLOC_STRUCT(nvc0_screen);
663 if (!screen)
664 return NULL;
665 pscreen = &screen->base.base;
666 pscreen->destroy = nvc0_screen_destroy;
667
668 ret = nouveau_screen_init(&screen->base, dev);
669 if (ret) {
670 nvc0_screen_destroy(pscreen);
671 return NULL;
672 }
673 chan = screen->base.channel;
674 push = screen->base.pushbuf;
675 push->user_priv = screen;
676 push->rsvd_kick = 5;
677
678 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
679 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
680 PIPE_BIND_COMMAND_ARGS_BUFFER;
681 screen->base.sysmem_bindings |=
682 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
683
684 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
685 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
686 screen->base.vidmem_bindings = 0;
687 }
688
689 pscreen->context_create = nvc0_create;
690 pscreen->is_format_supported = nvc0_screen_is_format_supported;
691 pscreen->get_param = nvc0_screen_get_param;
692 pscreen->get_shader_param = nvc0_screen_get_shader_param;
693 pscreen->get_paramf = nvc0_screen_get_paramf;
694 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
695 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
696
697 nvc0_screen_init_resource_functions(pscreen);
698
699 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
700 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
701
702 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
703 if (screen->base.drm->version >= 0x01000202)
704 flags |= NOUVEAU_BO_COHERENT;
705
706 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
707 if (ret)
708 goto fail;
709 nouveau_bo_map(screen->fence.bo, 0, NULL);
710 screen->fence.map = screen->fence.bo->map;
711 screen->base.fence.emit = nvc0_screen_fence_emit;
712 screen->base.fence.update = nvc0_screen_fence_update;
713
714
715 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
716 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
717 if (ret)
718 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
719
720 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
721 PUSH_DATA (push, screen->nvsw->handle);
722
723 switch (dev->chipset & ~0xf) {
724 case 0x110:
725 case 0x100:
726 case 0xf0:
727 obj_class = NVF0_P2MF_CLASS;
728 break;
729 case 0xe0:
730 obj_class = NVE4_P2MF_CLASS;
731 break;
732 default:
733 obj_class = NVC0_M2MF_CLASS;
734 break;
735 }
736 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
737 &screen->m2mf);
738 if (ret)
739 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
740
741 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
742 PUSH_DATA (push, screen->m2mf->oclass);
743 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
744 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
745 PUSH_DATA (push, 0xa0b5);
746 }
747
748 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
749 &screen->eng2d);
750 if (ret)
751 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
752
753 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
754 PUSH_DATA (push, screen->eng2d->oclass);
755 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
756 PUSH_DATA (push, 0);
757 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
758 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
759 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
760 PUSH_DATA (push, 0);
761 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
762 PUSH_DATA (push, 0);
763 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
764 PUSH_DATA (push, 0x3f);
765 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
766 PUSH_DATA (push, 1);
767 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
768 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
769
770 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
771 PUSH_DATAh(push, screen->fence.bo->offset + 16);
772 PUSH_DATA (push, screen->fence.bo->offset + 16);
773
774 switch (dev->chipset & ~0xf) {
775 case 0x110:
776 obj_class = GM107_3D_CLASS;
777 break;
778 case 0x100:
779 case 0xf0:
780 obj_class = NVF0_3D_CLASS;
781 break;
782 case 0xe0:
783 switch (dev->chipset) {
784 case 0xea:
785 obj_class = NVEA_3D_CLASS;
786 break;
787 default:
788 obj_class = NVE4_3D_CLASS;
789 break;
790 }
791 break;
792 case 0xd0:
793 obj_class = NVC8_3D_CLASS;
794 break;
795 case 0xc0:
796 default:
797 switch (dev->chipset) {
798 case 0xc8:
799 obj_class = NVC8_3D_CLASS;
800 break;
801 case 0xc1:
802 obj_class = NVC1_3D_CLASS;
803 break;
804 default:
805 obj_class = NVC0_3D_CLASS;
806 break;
807 }
808 break;
809 }
810 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
811 &screen->eng3d);
812 if (ret)
813 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
814 screen->base.class_3d = obj_class;
815
816 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
817 PUSH_DATA (push, screen->eng3d->oclass);
818
819 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
820 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
821
822 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
823 /* kill shaders after about 1 second (at 100 MHz) */
824 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
825 PUSH_DATA (push, 0x17);
826 }
827
828 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
829 screen->base.drm->version >= 0x01000101);
830 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
831 for (i = 0; i < 8; ++i)
832 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
833
834 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
835 PUSH_DATA (push, 1);
836
837 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
838 PUSH_DATA (push, 0);
839 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
840 PUSH_DATA (push, 0);
841 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
842 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
843 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
844 PUSH_DATA (push, 0);
845 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
846 PUSH_DATA (push, 1);
847 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
848 PUSH_DATA (push, 1);
849 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
850 PUSH_DATA (push, 1);
851 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
852 PUSH_DATA (push, 0);
853 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
854 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
855 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
856 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
857 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
858 } else {
859 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
860 PUSH_DATA (push, 15);
861 }
862 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
863 PUSH_DATA (push, 8); /* 128 */
864 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
865 PUSH_DATA (push, 1);
866 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
867 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
868 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
869 }
870
871 nvc0_magic_3d_init(push, screen->eng3d->oclass);
872
873 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
874 &screen->text);
875 if (ret)
876 goto fail;
877
878 /* XXX: getting a page fault at the end of the code buffer every few
879 * launches, don't use the last 256 bytes to work around them - prefetch ?
880 */
881 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
882
883 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
884 &screen->uniform_bo);
885 if (ret)
886 goto fail;
887
888 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
889
890 for (i = 0; i < 5; ++i) {
891 /* TIC and TSC entries for each unit (nve4+ only) */
892 /* auxiliary constants (6 user clip planes, base instance id) */
893 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
894 PUSH_DATA (push, 512);
895 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
896 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
897 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
898 PUSH_DATA (push, (15 << 4) | 1);
899 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
900 unsigned j;
901 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
902 PUSH_DATA (push, 0);
903 for (j = 0; j < 8; ++j)
904 PUSH_DATA(push, j);
905 } else {
906 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
907 PUSH_DATA (push, 0x54);
908 }
909 }
910 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
911 PUSH_DATA (push, 0);
912
913 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
914 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
915 PUSH_DATA (push, 256);
916 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
917 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
918 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
919 PUSH_DATA (push, 0);
920 PUSH_DATAf(push, 0.0f);
921 PUSH_DATAf(push, 0.0f);
922 PUSH_DATAf(push, 0.0f);
923 PUSH_DATAf(push, 0.0f);
924 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
925 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
926 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
927
928 if (screen->base.drm->version >= 0x01000101) {
929 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
930 if (ret) {
931 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
932 goto fail;
933 }
934 } else {
935 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
936 value = (8 << 8) | 4;
937 else
938 value = (16 << 8) | 4;
939 }
940 screen->gpc_count = value & 0x000000ff;
941 screen->mp_count = value >> 8;
942 screen->mp_count_compute = screen->mp_count;
943
944 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
945
946 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
947 PUSH_DATAh(push, screen->text->offset);
948 PUSH_DATA (push, screen->text->offset);
949 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
950 PUSH_DATAh(push, screen->tls->offset);
951 PUSH_DATA (push, screen->tls->offset);
952 PUSH_DATA (push, screen->tls->size >> 32);
953 PUSH_DATA (push, screen->tls->size);
954 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
955 PUSH_DATA (push, 0);
956 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
957 PUSH_DATA (push, 0);
958
959 if (screen->eng3d->oclass < GM107_3D_CLASS) {
960 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
961 &screen->poly_cache);
962 if (ret)
963 goto fail;
964
965 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
966 PUSH_DATAh(push, screen->poly_cache->offset);
967 PUSH_DATA (push, screen->poly_cache->offset);
968 PUSH_DATA (push, 3);
969 }
970
971 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
972 &screen->txc);
973 if (ret)
974 goto fail;
975
976 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
977 PUSH_DATAh(push, screen->txc->offset);
978 PUSH_DATA (push, screen->txc->offset);
979 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
980
981 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
982 PUSH_DATAh(push, screen->txc->offset + 65536);
983 PUSH_DATA (push, screen->txc->offset + 65536);
984 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
985
986 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
987 PUSH_DATA (push, 0);
988 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
989 PUSH_DATA (push, 0);
990 PUSH_DATA (push, 0);
991 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
992 PUSH_DATA (push, 0x3f);
993
994 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
995 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
996 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
997 for (i = 0; i < 8 * 2; ++i)
998 PUSH_DATA(push, 0);
999 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1000 PUSH_DATA (push, 0);
1001 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1002 PUSH_DATA (push, 0);
1003
1004 /* neither scissors, viewport nor stencil mask should affect clears */
1005 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1006 PUSH_DATA (push, 0);
1007
1008 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1009 PUSH_DATA (push, 1);
1010 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1011 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1012 PUSH_DATAf(push, 0.0f);
1013 PUSH_DATAf(push, 1.0f);
1014 }
1015 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1016 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1017
1018 /* We use scissors instead of exact view volume clipping,
1019 * so they're always enabled.
1020 */
1021 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1022 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1023 PUSH_DATA (push, 1);
1024 PUSH_DATA (push, 8192 << 16);
1025 PUSH_DATA (push, 8192 << 16);
1026 }
1027
1028 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1029
1030 i = 0;
1031 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1032 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1033 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1034 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1035 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1036 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1037 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1038 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1039 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1040 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1041 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1042
1043 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1044 PUSH_DATA (push, 1);
1045 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1046 PUSH_DATA (push, 1);
1047 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1048 PUSH_DATA (push, 0x40);
1049 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1050 PUSH_DATA (push, 0);
1051 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1052 PUSH_DATA (push, 0x30);
1053 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1054 PUSH_DATA (push, 3);
1055 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1056 PUSH_DATA (push, 0x20);
1057 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1058 PUSH_DATA (push, 0x00);
1059 screen->save_state.patch_vertices = 3;
1060
1061 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1062 PUSH_DATA (push, 0);
1063 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1064 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1065
1066 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1067
1068 if (nvc0_screen_init_compute(screen))
1069 goto fail;
1070
1071 PUSH_KICK (push);
1072
1073 screen->tic.entries = CALLOC(4096, sizeof(void *));
1074 screen->tsc.entries = screen->tic.entries + 2048;
1075
1076 if (!nvc0_blitter_create(screen))
1077 goto fail;
1078
1079 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1080
1081 return &screen->base;
1082
1083 fail:
1084 screen->base.base.context_create = NULL;
1085 return &screen->base;
1086 }
1087
1088 int
1089 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1090 {
1091 int i = screen->tic.next;
1092
1093 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1094 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1095
1096 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1097
1098 if (screen->tic.entries[i])
1099 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1100
1101 screen->tic.entries[i] = entry;
1102 return i;
1103 }
1104
1105 int
1106 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1107 {
1108 int i = screen->tsc.next;
1109
1110 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1111 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1112
1113 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1114
1115 if (screen->tsc.entries[i])
1116 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1117
1118 screen->tsc.entries[i] = entry;
1119 return i;
1120 }