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nvc0: enable GL 4.3 on gm107+
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 const struct util_format_description *desc = util_format_description(format);
49
50 if (sample_count > 8)
51 return false;
52 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
53 return false;
54
55 /* Short-circuit the rest of the logic -- this is used by the state tracker
56 * to determine valid MS levels in a no-attachments scenario.
57 */
58 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
59 return true;
60
61 if (!util_format_is_supported(format, bindings))
62 return false;
63
64 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
65 if (util_format_get_blocksizebits(format) == 3 * 32)
66 return false;
67
68 if (bindings & PIPE_BIND_LINEAR)
69 if (util_format_is_depth_or_stencil(format) ||
70 (target != PIPE_TEXTURE_1D &&
71 target != PIPE_TEXTURE_2D &&
72 target != PIPE_TEXTURE_RECT) ||
73 sample_count > 1)
74 return false;
75
76 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
77 */
78 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
79 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
80 /* The claim is that this should work on GM107 but it doesn't. Need to
81 * test further and figure out if it's a nouveau issue or a HW one.
82 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
83 */
84 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
85 return false;
86
87 /* shared is always supported */
88 bindings &= ~(PIPE_BIND_LINEAR |
89 PIPE_BIND_SHARED);
90
91 if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 return (( nvc0_format_table[format].usage |
99 nvc0_vertex_format[format].usage) & bindings) == bindings;
100 }
101
102 static int
103 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
104 {
105 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
106 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
107
108 switch (param) {
109 /* non-boolean caps */
110 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
111 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
112 return 15;
113 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
114 return 12;
115 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
116 return 2048;
117 case PIPE_CAP_MIN_TEXEL_OFFSET:
118 return -8;
119 case PIPE_CAP_MAX_TEXEL_OFFSET:
120 return 7;
121 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
122 return -32;
123 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
124 return 31;
125 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
126 return 128 * 1024 * 1024;
127 case PIPE_CAP_GLSL_FEATURE_LEVEL:
128 return 430;
129 case PIPE_CAP_MAX_RENDER_TARGETS:
130 return 8;
131 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
132 return 1;
133 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
134 return 4;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
136 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
137 return 128;
138 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
139 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
140 return 1024;
141 case PIPE_CAP_MAX_VERTEX_STREAMS:
142 return 4;
143 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
144 return 2048;
145 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
146 return 256;
147 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
148 return 16; /* 256 for binding as RT, but that's not possible in GL */
149 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
150 return 16;
151 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
152 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
153 case PIPE_CAP_MAX_VIEWPORTS:
154 return NVC0_MAX_VIEWPORTS;
155 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
156 return 4;
157 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
158 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
159 case PIPE_CAP_ENDIANNESS:
160 return PIPE_ENDIAN_LITTLE;
161 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
162 return 30;
163 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
164 return NVC0_MAX_WINDOW_RECTANGLES;
165
166 /* supported caps */
167 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
168 case PIPE_CAP_TEXTURE_SWIZZLE:
169 case PIPE_CAP_TEXTURE_SHADOW_MAP:
170 case PIPE_CAP_NPOT_TEXTURES:
171 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
172 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
173 case PIPE_CAP_ANISOTROPIC_FILTER:
174 case PIPE_CAP_SEAMLESS_CUBE_MAP:
175 case PIPE_CAP_CUBE_MAP_ARRAY:
176 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
177 case PIPE_CAP_TEXTURE_MULTISAMPLE:
178 case PIPE_CAP_TWO_SIDED_STENCIL:
179 case PIPE_CAP_DEPTH_CLIP_DISABLE:
180 case PIPE_CAP_POINT_SPRITE:
181 case PIPE_CAP_TGSI_TEXCOORD:
182 case PIPE_CAP_SM3:
183 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
184 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
185 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
186 case PIPE_CAP_QUERY_TIMESTAMP:
187 case PIPE_CAP_QUERY_TIME_ELAPSED:
188 case PIPE_CAP_OCCLUSION_QUERY:
189 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
190 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
191 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
192 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
193 case PIPE_CAP_INDEP_BLEND_ENABLE:
194 case PIPE_CAP_INDEP_BLEND_FUNC:
195 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
196 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
197 case PIPE_CAP_PRIMITIVE_RESTART:
198 case PIPE_CAP_TGSI_INSTANCEID:
199 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
200 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
201 case PIPE_CAP_CONDITIONAL_RENDER:
202 case PIPE_CAP_TEXTURE_BARRIER:
203 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
204 case PIPE_CAP_START_INSTANCE:
205 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
206 case PIPE_CAP_DRAW_INDIRECT:
207 case PIPE_CAP_USER_CONSTANT_BUFFERS:
208 case PIPE_CAP_USER_INDEX_BUFFERS:
209 case PIPE_CAP_USER_VERTEX_BUFFERS:
210 case PIPE_CAP_TEXTURE_QUERY_LOD:
211 case PIPE_CAP_SAMPLE_SHADING:
212 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
213 case PIPE_CAP_TEXTURE_GATHER_SM5:
214 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
215 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
216 case PIPE_CAP_SAMPLER_VIEW_TARGET:
217 case PIPE_CAP_CLIP_HALFZ:
218 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
219 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
220 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
221 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
222 case PIPE_CAP_DEPTH_BOUNDS_TEST:
223 case PIPE_CAP_TGSI_TXQS:
224 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
225 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
226 case PIPE_CAP_SHAREABLE_SHADERS:
227 case PIPE_CAP_CLEAR_TEXTURE:
228 case PIPE_CAP_DRAW_PARAMETERS:
229 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
230 case PIPE_CAP_MULTI_DRAW_INDIRECT:
231 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
232 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
233 case PIPE_CAP_QUERY_BUFFER_OBJECT:
234 case PIPE_CAP_INVALIDATE_BUFFER:
235 case PIPE_CAP_STRING_MARKER:
236 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
237 case PIPE_CAP_CULL_DISTANCE:
238 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
239 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
240 case PIPE_CAP_TGSI_VOTE:
241 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
242 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
243 return 1;
244 case PIPE_CAP_COMPUTE:
245 return (class_3d < GP100_3D_CLASS);
246 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
247 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
248 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
249 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
250
251 /* unsupported caps */
252 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
253 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
254 case PIPE_CAP_SHADER_STENCIL_EXPORT:
255 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
256 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
257 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
258 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
259 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
260 case PIPE_CAP_FAKE_SW_MSAA:
261 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
262 case PIPE_CAP_VERTEXID_NOBASE:
263 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
264 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
265 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
266 case PIPE_CAP_GENERATE_MIPMAP:
267 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
268 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
269 case PIPE_CAP_QUERY_MEMORY_INFO:
270 case PIPE_CAP_PCI_GROUP:
271 case PIPE_CAP_PCI_BUS:
272 case PIPE_CAP_PCI_DEVICE:
273 case PIPE_CAP_PCI_FUNCTION:
274 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
275 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
276 case PIPE_CAP_NATIVE_FENCE_FD:
277 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
278 return 0;
279
280 case PIPE_CAP_VENDOR_ID:
281 return 0x10de;
282 case PIPE_CAP_DEVICE_ID: {
283 uint64_t device_id;
284 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
285 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
286 return -1;
287 }
288 return device_id;
289 }
290 case PIPE_CAP_ACCELERATED:
291 return 1;
292 case PIPE_CAP_VIDEO_MEMORY:
293 return dev->vram_size >> 20;
294 case PIPE_CAP_UMA:
295 return 0;
296 }
297
298 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
299 return 0;
300 }
301
302 static int
303 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
304 enum pipe_shader_cap param)
305 {
306 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
307
308 switch (shader) {
309 case PIPE_SHADER_VERTEX:
310 case PIPE_SHADER_GEOMETRY:
311 case PIPE_SHADER_FRAGMENT:
312 case PIPE_SHADER_COMPUTE:
313 case PIPE_SHADER_TESS_CTRL:
314 case PIPE_SHADER_TESS_EVAL:
315 break;
316 default:
317 return 0;
318 }
319
320 switch (param) {
321 case PIPE_SHADER_CAP_PREFERRED_IR:
322 return PIPE_SHADER_IR_TGSI;
323 case PIPE_SHADER_CAP_SUPPORTED_IRS:
324 return 1 << PIPE_SHADER_IR_TGSI;
325 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
326 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
327 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
328 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
329 return 16384;
330 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
331 return 16;
332 case PIPE_SHADER_CAP_MAX_INPUTS:
333 if (shader == PIPE_SHADER_VERTEX)
334 return 32;
335 /* NOTE: These only count our slots for GENERIC varyings.
336 * The address space may be larger, but the actual hard limit seems to be
337 * less than what the address space layout permits, so don't add TEXCOORD,
338 * COLOR, etc. here.
339 */
340 if (shader == PIPE_SHADER_FRAGMENT)
341 return 0x1f0 / 16;
342 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
343 * and excludes 0x60 per-patch inputs.
344 */
345 return 0x200 / 16;
346 case PIPE_SHADER_CAP_MAX_OUTPUTS:
347 return 32;
348 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
349 return 65536;
350 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
351 return NVC0_MAX_PIPE_CONSTBUFS;
352 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
353 return shader != PIPE_SHADER_FRAGMENT;
354 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
355 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
356 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
357 return 1;
358 case PIPE_SHADER_CAP_MAX_PREDS:
359 return 0;
360 case PIPE_SHADER_CAP_MAX_TEMPS:
361 return NVC0_CAP_MAX_PROGRAM_TEMPS;
362 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
363 return 1;
364 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
365 return 1;
366 case PIPE_SHADER_CAP_SUBROUTINES:
367 return 1;
368 case PIPE_SHADER_CAP_INTEGERS:
369 return 1;
370 case PIPE_SHADER_CAP_DOUBLES:
371 return 1;
372 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
373 return 1;
374 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
375 return 1;
376 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
377 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
378 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
379 return 0;
380 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
381 return NVC0_MAX_BUFFERS;
382 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
383 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
384 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
385 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
386 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
387 return 32;
388 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
389 if (class_3d >= NVE4_3D_CLASS)
390 return NVC0_MAX_IMAGES;
391 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
392 return NVC0_MAX_IMAGES;
393 return 0;
394 default:
395 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
396 return 0;
397 }
398 }
399
400 static float
401 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
402 {
403 switch (param) {
404 case PIPE_CAPF_MAX_LINE_WIDTH:
405 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
406 return 10.0f;
407 case PIPE_CAPF_MAX_POINT_WIDTH:
408 return 63.0f;
409 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
410 return 63.375f;
411 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
412 return 16.0f;
413 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
414 return 15.0f;
415 case PIPE_CAPF_GUARD_BAND_LEFT:
416 case PIPE_CAPF_GUARD_BAND_TOP:
417 return 0.0f;
418 case PIPE_CAPF_GUARD_BAND_RIGHT:
419 case PIPE_CAPF_GUARD_BAND_BOTTOM:
420 return 0.0f; /* that or infinity */
421 }
422
423 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
424 return 0.0f;
425 }
426
427 static int
428 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
429 enum pipe_shader_ir ir_type,
430 enum pipe_compute_cap param, void *data)
431 {
432 struct nvc0_screen *screen = nvc0_screen(pscreen);
433 const uint16_t obj_class = screen->compute->oclass;
434
435 #define RET(x) do { \
436 if (data) \
437 memcpy(data, x, sizeof(x)); \
438 return sizeof(x); \
439 } while (0)
440
441 switch (param) {
442 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
443 RET((uint64_t []) { 3 });
444 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
445 if (obj_class >= NVE4_COMPUTE_CLASS) {
446 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
447 } else {
448 RET(((uint64_t []) { 65535, 65535, 65535 }));
449 }
450 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
451 RET(((uint64_t []) { 1024, 1024, 64 }));
452 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
453 RET((uint64_t []) { 1024 });
454 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
455 if (obj_class >= NVE4_COMPUTE_CLASS) {
456 RET((uint64_t []) { 1024 });
457 } else {
458 RET((uint64_t []) { 512 });
459 }
460 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
461 RET((uint64_t []) { 1ULL << 40 });
462 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
463 switch (obj_class) {
464 case GM200_COMPUTE_CLASS:
465 RET((uint64_t []) { 96 << 10 });
466 break;
467 case GM107_COMPUTE_CLASS:
468 RET((uint64_t []) { 64 << 10 });
469 break;
470 default:
471 RET((uint64_t []) { 48 << 10 });
472 break;
473 }
474 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
475 RET((uint64_t []) { 512 << 10 });
476 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
477 RET((uint64_t []) { 4096 });
478 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
479 RET((uint32_t []) { 32 });
480 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
481 RET((uint64_t []) { 1ULL << 40 });
482 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
483 RET((uint32_t []) { 0 });
484 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
485 RET((uint32_t []) { screen->mp_count_compute });
486 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
487 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
488 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
489 RET((uint32_t []) { 64 });
490 default:
491 return 0;
492 }
493
494 #undef RET
495 }
496
497 static void
498 nvc0_screen_destroy(struct pipe_screen *pscreen)
499 {
500 struct nvc0_screen *screen = nvc0_screen(pscreen);
501
502 if (!nouveau_drm_screen_unref(&screen->base))
503 return;
504
505 if (screen->base.fence.current) {
506 struct nouveau_fence *current = NULL;
507
508 /* nouveau_fence_wait will create a new current fence, so wait on the
509 * _current_ one, and remove both.
510 */
511 nouveau_fence_ref(screen->base.fence.current, &current);
512 nouveau_fence_wait(current, NULL);
513 nouveau_fence_ref(NULL, &current);
514 nouveau_fence_ref(NULL, &screen->base.fence.current);
515 }
516 if (screen->base.pushbuf)
517 screen->base.pushbuf->user_priv = NULL;
518
519 if (screen->blitter)
520 nvc0_blitter_destroy(screen);
521 if (screen->pm.prog) {
522 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
523 nvc0_program_destroy(NULL, screen->pm.prog);
524 FREE(screen->pm.prog);
525 }
526
527 nouveau_bo_ref(NULL, &screen->text);
528 nouveau_bo_ref(NULL, &screen->uniform_bo);
529 nouveau_bo_ref(NULL, &screen->tls);
530 nouveau_bo_ref(NULL, &screen->txc);
531 nouveau_bo_ref(NULL, &screen->fence.bo);
532 nouveau_bo_ref(NULL, &screen->poly_cache);
533
534 nouveau_heap_destroy(&screen->lib_code);
535 nouveau_heap_destroy(&screen->text_heap);
536
537 FREE(screen->tic.entries);
538
539 nouveau_object_del(&screen->eng3d);
540 nouveau_object_del(&screen->eng2d);
541 nouveau_object_del(&screen->m2mf);
542 nouveau_object_del(&screen->compute);
543 nouveau_object_del(&screen->nvsw);
544
545 nouveau_screen_fini(&screen->base);
546
547 FREE(screen);
548 }
549
550 static int
551 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
552 unsigned size, const uint32_t *data)
553 {
554 struct nouveau_pushbuf *push = screen->base.pushbuf;
555
556 size /= 4;
557
558 assert((pos + size) <= 0x800);
559
560 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
561 PUSH_DATA (push, (m - 0x3800) / 8);
562 PUSH_DATA (push, pos);
563 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
564 PUSH_DATA (push, pos);
565 PUSH_DATAp(push, data, size);
566
567 return pos + size;
568 }
569
570 static void
571 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
572 {
573 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
574 PUSH_DATA (push, 0xff);
575 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
576 PUSH_DATA (push, 0xff);
577 PUSH_DATA (push, 0xff);
578 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
579 PUSH_DATA (push, 0xff);
580 PUSH_DATA (push, 0xff);
581 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
582 PUSH_DATA (push, 0x3f);
583
584 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
585 PUSH_DATA (push, (3 << 16) | 3);
586 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
587 PUSH_DATA (push, (2 << 16) | 2);
588
589 if (obj_class < GM107_3D_CLASS) {
590 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
591 PUSH_DATA (push, 0);
592 }
593 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
594 PUSH_DATA (push, 0x10);
595 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
596 PUSH_DATA (push, 0x10);
597 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
598 PUSH_DATA (push, 0x10);
599 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
600 PUSH_DATA (push, 0x10);
601 PUSH_DATA (push, 0x10);
602 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
603 PUSH_DATA (push, 0x10);
604 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
605 PUSH_DATA (push, 0xe);
606
607 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
608 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
609 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
610 PUSH_DATA (push, 0);
611 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
612 PUSH_DATA (push, 3);
613
614 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
615 PUSH_DATA (push, 0x3fffff);
616 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
617 PUSH_DATA (push, 1);
618 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
619 PUSH_DATA (push, 1);
620
621 if (obj_class < GM107_3D_CLASS) {
622 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
623 PUSH_DATA (push, 3);
624
625 if (obj_class >= NVE4_3D_CLASS) {
626 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
627 PUSH_DATA (push, 1);
628 }
629 }
630
631 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
632 * are supposed to do */
633 }
634
635 static void
636 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
637 {
638 struct nvc0_screen *screen = nvc0_screen(pscreen);
639 struct nouveau_pushbuf *push = screen->base.pushbuf;
640
641 /* we need to do it after possible flush in MARK_RING */
642 *sequence = ++screen->base.fence.sequence;
643
644 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
645 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
646 PUSH_DATAh(push, screen->fence.bo->offset);
647 PUSH_DATA (push, screen->fence.bo->offset);
648 PUSH_DATA (push, *sequence);
649 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
650 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
651 }
652
653 static u32
654 nvc0_screen_fence_update(struct pipe_screen *pscreen)
655 {
656 struct nvc0_screen *screen = nvc0_screen(pscreen);
657 return screen->fence.map[0];
658 }
659
660 static int
661 nvc0_screen_init_compute(struct nvc0_screen *screen)
662 {
663 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
664
665 switch (screen->base.device->chipset & ~0xf) {
666 case 0xc0:
667 case 0xd0:
668 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
669 case 0xe0:
670 case 0xf0:
671 case 0x100:
672 case 0x110:
673 case 0x120:
674 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
675 case 0x130:
676 return 0;
677 default:
678 return -1;
679 }
680 }
681
682 static int
683 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
684 uint32_t lpos, uint32_t lneg, uint32_t cstack)
685 {
686 struct nouveau_bo *bo = NULL;
687 int ret;
688 uint64_t size = (lpos + lneg) * 32 + cstack;
689
690 if (size >= (1 << 20)) {
691 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
692 return -1;
693 }
694
695 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
696 size = align(size, 0x8000);
697 size *= screen->mp_count;
698
699 size = align(size, 1 << 17);
700
701 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
702 NULL, &bo);
703 if (ret)
704 return ret;
705 nouveau_bo_ref(NULL, &screen->tls);
706 screen->tls = bo;
707 return 0;
708 }
709
710 int
711 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
712 {
713 struct nouveau_pushbuf *push = screen->base.pushbuf;
714 struct nouveau_bo *bo;
715 int ret;
716
717 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
718 1 << 17, size, NULL, &bo);
719 if (ret)
720 return ret;
721
722 nouveau_bo_ref(NULL, &screen->text);
723 screen->text = bo;
724
725 nouveau_heap_destroy(&screen->lib_code);
726 nouveau_heap_destroy(&screen->text_heap);
727
728 /* XXX: getting a page fault at the end of the code buffer every few
729 * launches, don't use the last 256 bytes to work around them - prefetch ?
730 */
731 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
732
733 /* update the code segment setup */
734 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
735 PUSH_DATAh(push, screen->text->offset);
736 PUSH_DATA (push, screen->text->offset);
737 if (screen->compute) {
738 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
739 PUSH_DATAh(push, screen->text->offset);
740 PUSH_DATA (push, screen->text->offset);
741 }
742
743 return 0;
744 }
745
746 #define FAIL_SCREEN_INIT(str, err) \
747 do { \
748 NOUVEAU_ERR(str, err); \
749 goto fail; \
750 } while(0)
751
752 struct nouveau_screen *
753 nvc0_screen_create(struct nouveau_device *dev)
754 {
755 struct nvc0_screen *screen;
756 struct pipe_screen *pscreen;
757 struct nouveau_object *chan;
758 struct nouveau_pushbuf *push;
759 uint64_t value;
760 uint32_t obj_class;
761 uint32_t flags;
762 int ret;
763 unsigned i;
764
765 switch (dev->chipset & ~0xf) {
766 case 0xc0:
767 case 0xd0:
768 case 0xe0:
769 case 0xf0:
770 case 0x100:
771 case 0x110:
772 case 0x120:
773 case 0x130:
774 break;
775 default:
776 return NULL;
777 }
778
779 screen = CALLOC_STRUCT(nvc0_screen);
780 if (!screen)
781 return NULL;
782 pscreen = &screen->base.base;
783 pscreen->destroy = nvc0_screen_destroy;
784
785 ret = nouveau_screen_init(&screen->base, dev);
786 if (ret)
787 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
788 chan = screen->base.channel;
789 push = screen->base.pushbuf;
790 push->user_priv = screen;
791 push->rsvd_kick = 5;
792
793 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
794 PIPE_BIND_SHADER_BUFFER |
795 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
796 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
797 screen->base.sysmem_bindings |=
798 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
799
800 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
801 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
802 screen->base.vidmem_bindings = 0;
803 }
804
805 pscreen->context_create = nvc0_create;
806 pscreen->is_format_supported = nvc0_screen_is_format_supported;
807 pscreen->get_param = nvc0_screen_get_param;
808 pscreen->get_shader_param = nvc0_screen_get_shader_param;
809 pscreen->get_paramf = nvc0_screen_get_paramf;
810 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
811 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
812
813 nvc0_screen_init_resource_functions(pscreen);
814
815 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
816 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
817
818 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
819 if (screen->base.drm->version >= 0x01000202)
820 flags |= NOUVEAU_BO_COHERENT;
821
822 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
823 if (ret)
824 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
825 nouveau_bo_map(screen->fence.bo, 0, NULL);
826 screen->fence.map = screen->fence.bo->map;
827 screen->base.fence.emit = nvc0_screen_fence_emit;
828 screen->base.fence.update = nvc0_screen_fence_update;
829
830
831 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
832 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
833 if (ret)
834 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
835
836 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
837 PUSH_DATA (push, screen->nvsw->handle);
838
839 switch (dev->chipset & ~0xf) {
840 case 0x130:
841 case 0x120:
842 case 0x110:
843 case 0x100:
844 case 0xf0:
845 obj_class = NVF0_P2MF_CLASS;
846 break;
847 case 0xe0:
848 obj_class = NVE4_P2MF_CLASS;
849 break;
850 default:
851 obj_class = NVC0_M2MF_CLASS;
852 break;
853 }
854 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
855 &screen->m2mf);
856 if (ret)
857 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
858
859 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
860 PUSH_DATA (push, screen->m2mf->oclass);
861 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
862 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
863 PUSH_DATA (push, 0xa0b5);
864 }
865
866 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
867 &screen->eng2d);
868 if (ret)
869 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
870
871 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
872 PUSH_DATA (push, screen->eng2d->oclass);
873 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
874 PUSH_DATA (push, 0);
875 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
876 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
877 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
878 PUSH_DATA (push, 0);
879 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
880 PUSH_DATA (push, 0);
881 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
882 PUSH_DATA (push, 0x3f);
883 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
884 PUSH_DATA (push, 1);
885 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
886 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
887
888 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
889 PUSH_DATAh(push, screen->fence.bo->offset + 16);
890 PUSH_DATA (push, screen->fence.bo->offset + 16);
891
892 switch (dev->chipset & ~0xf) {
893 case 0x130:
894 obj_class = GP100_3D_CLASS;
895 break;
896 case 0x120:
897 obj_class = GM200_3D_CLASS;
898 break;
899 case 0x110:
900 obj_class = GM107_3D_CLASS;
901 break;
902 case 0x100:
903 case 0xf0:
904 obj_class = NVF0_3D_CLASS;
905 break;
906 case 0xe0:
907 switch (dev->chipset) {
908 case 0xea:
909 obj_class = NVEA_3D_CLASS;
910 break;
911 default:
912 obj_class = NVE4_3D_CLASS;
913 break;
914 }
915 break;
916 case 0xd0:
917 obj_class = NVC8_3D_CLASS;
918 break;
919 case 0xc0:
920 default:
921 switch (dev->chipset) {
922 case 0xc8:
923 obj_class = NVC8_3D_CLASS;
924 break;
925 case 0xc1:
926 obj_class = NVC1_3D_CLASS;
927 break;
928 default:
929 obj_class = NVC0_3D_CLASS;
930 break;
931 }
932 break;
933 }
934 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
935 &screen->eng3d);
936 if (ret)
937 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
938 screen->base.class_3d = obj_class;
939
940 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
941 PUSH_DATA (push, screen->eng3d->oclass);
942
943 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
944 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
945
946 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
947 /* kill shaders after about 1 second (at 100 MHz) */
948 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
949 PUSH_DATA (push, 0x17);
950 }
951
952 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
953 screen->base.drm->version >= 0x01000101);
954 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
955 for (i = 0; i < 8; ++i)
956 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
957
958 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
959 PUSH_DATA (push, 1);
960
961 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
962 PUSH_DATA (push, 0);
963 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
964 PUSH_DATA (push, 0);
965 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
966 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
967 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
968 PUSH_DATA (push, 0);
969 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
970 PUSH_DATA (push, 1);
971 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
972 PUSH_DATA (push, 1);
973 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
974 PUSH_DATA (push, 1);
975 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
976 PUSH_DATA (push, 0);
977 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
978 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
979 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
980 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
981 } else {
982 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
983 PUSH_DATA (push, 15);
984 }
985 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
986 PUSH_DATA (push, 8); /* 128 */
987 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
988 PUSH_DATA (push, 1);
989 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
990 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
991 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
992 }
993
994 nvc0_magic_3d_init(push, screen->eng3d->oclass);
995
996 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
997 if (ret)
998 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
999
1000 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1001 &screen->uniform_bo);
1002 if (ret)
1003 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1004
1005 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1006
1007 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1008 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1009 PUSH_DATA (push, 256);
1010 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1011 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1012 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1013 PUSH_DATA (push, 0);
1014 PUSH_DATAf(push, 0.0f);
1015 PUSH_DATAf(push, 0.0f);
1016 PUSH_DATAf(push, 0.0f);
1017 PUSH_DATAf(push, 0.0f);
1018 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1019 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1020 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1021
1022 if (screen->base.drm->version >= 0x01000101) {
1023 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1024 if (ret)
1025 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1026 } else {
1027 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1028 value = (8 << 8) | 4;
1029 else
1030 value = (16 << 8) | 4;
1031 }
1032 screen->gpc_count = value & 0x000000ff;
1033 screen->mp_count = value >> 8;
1034 screen->mp_count_compute = screen->mp_count;
1035
1036 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1037 if (ret)
1038 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1039
1040 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1041 PUSH_DATAh(push, screen->tls->offset);
1042 PUSH_DATA (push, screen->tls->offset);
1043 PUSH_DATA (push, screen->tls->size >> 32);
1044 PUSH_DATA (push, screen->tls->size);
1045 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1046 PUSH_DATA (push, 0);
1047 /* Reduce likelihood of collision with real buffers by placing the hole at
1048 * the top of the 4G area. This will have to be dealt with for real
1049 * eventually by blocking off that area from the VM.
1050 */
1051 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1052 PUSH_DATA (push, 0xff << 24);
1053
1054 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1055 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1056 &screen->poly_cache);
1057 if (ret)
1058 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1059
1060 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1061 PUSH_DATAh(push, screen->poly_cache->offset);
1062 PUSH_DATA (push, screen->poly_cache->offset);
1063 PUSH_DATA (push, 3);
1064 }
1065
1066 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1067 &screen->txc);
1068 if (ret)
1069 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1070
1071 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1072 PUSH_DATAh(push, screen->txc->offset);
1073 PUSH_DATA (push, screen->txc->offset);
1074 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1075 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1076 screen->tic.maxwell = true;
1077 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1078 screen->tic.maxwell =
1079 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1080 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1081 }
1082 }
1083
1084 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1085 PUSH_DATAh(push, screen->txc->offset + 65536);
1086 PUSH_DATA (push, screen->txc->offset + 65536);
1087 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1088
1089 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1090 PUSH_DATA (push, 0);
1091 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1092 PUSH_DATA (push, 0);
1093 PUSH_DATA (push, 0);
1094 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1095 PUSH_DATA (push, 0x3f);
1096
1097 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1098 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1099 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1100 for (i = 0; i < 8 * 2; ++i)
1101 PUSH_DATA(push, 0);
1102 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1103 PUSH_DATA (push, 0);
1104 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1105 PUSH_DATA (push, 0);
1106
1107 /* neither scissors, viewport nor stencil mask should affect clears */
1108 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1109 PUSH_DATA (push, 0);
1110
1111 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1112 PUSH_DATA (push, 1);
1113 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1114 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1115 PUSH_DATAf(push, 0.0f);
1116 PUSH_DATAf(push, 1.0f);
1117 }
1118 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1119 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1120
1121 /* We use scissors instead of exact view volume clipping,
1122 * so they're always enabled.
1123 */
1124 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1125 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1126 PUSH_DATA (push, 1);
1127 PUSH_DATA (push, 8192 << 16);
1128 PUSH_DATA (push, 8192 << 16);
1129 }
1130
1131 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1132
1133 i = 0;
1134 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1135 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1136 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1137 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1138 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1139 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1140 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1141 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1142 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1143 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1144 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1145 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1146 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1147
1148 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1149 PUSH_DATA (push, 1);
1150 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1151 PUSH_DATA (push, 1);
1152 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1153 PUSH_DATA (push, 0x40);
1154 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1155 PUSH_DATA (push, 0);
1156 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1157 PUSH_DATA (push, 0x30);
1158 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1159 PUSH_DATA (push, 3);
1160 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1161 PUSH_DATA (push, 0x20);
1162 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1163 PUSH_DATA (push, 0x00);
1164 screen->save_state.patch_vertices = 3;
1165
1166 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1167 PUSH_DATA (push, 0);
1168 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1169 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1170
1171 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1172
1173 if (nvc0_screen_init_compute(screen))
1174 goto fail;
1175
1176 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1177 for (i = 0; i < 5; ++i) {
1178 /* TIC and TSC entries for each unit (nve4+ only) */
1179 /* auxiliary constants (6 user clip planes, base instance id) */
1180 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1181 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1182 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1183 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1184 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1185 PUSH_DATA (push, (15 << 4) | 1);
1186 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1187 unsigned j;
1188 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1189 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1190 for (j = 0; j < 8; ++j)
1191 PUSH_DATA(push, j);
1192 } else {
1193 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1194 PUSH_DATA (push, 0x54);
1195 }
1196
1197 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1198 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1199 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1200 PUSH_DATA (push, 0); /* 0 */
1201 PUSH_DATA (push, 0);
1202 PUSH_DATA (push, 1); /* 1 */
1203 PUSH_DATA (push, 0);
1204 PUSH_DATA (push, 0); /* 2 */
1205 PUSH_DATA (push, 1);
1206 PUSH_DATA (push, 1); /* 3 */
1207 PUSH_DATA (push, 1);
1208 PUSH_DATA (push, 2); /* 4 */
1209 PUSH_DATA (push, 0);
1210 PUSH_DATA (push, 3); /* 5 */
1211 PUSH_DATA (push, 0);
1212 PUSH_DATA (push, 2); /* 6 */
1213 PUSH_DATA (push, 1);
1214 PUSH_DATA (push, 3); /* 7 */
1215 PUSH_DATA (push, 1);
1216 }
1217 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1218 PUSH_DATA (push, 0);
1219
1220 PUSH_KICK (push);
1221
1222 screen->tic.entries = CALLOC(4096, sizeof(void *));
1223 screen->tsc.entries = screen->tic.entries + 2048;
1224
1225 if (!nvc0_blitter_create(screen))
1226 goto fail;
1227
1228 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1229
1230 return &screen->base;
1231
1232 fail:
1233 screen->base.base.context_create = NULL;
1234 return &screen->base;
1235 }
1236
1237 int
1238 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1239 {
1240 int i = screen->tic.next;
1241
1242 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1243 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1244
1245 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1246
1247 if (screen->tic.entries[i])
1248 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1249
1250 screen->tic.entries[i] = entry;
1251 return i;
1252 }
1253
1254 int
1255 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1256 {
1257 int i = screen->tsc.next;
1258
1259 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1260 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1261
1262 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1263
1264 if (screen->tsc.entries[i])
1265 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1266
1267 screen->tsc.entries[i] = entry;
1268 return i;
1269 }