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gallium: Add PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 const struct util_format_description *desc = util_format_description(format);
49
50 if (sample_count > 8)
51 return false;
52 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
53 return false;
54
55 if (!util_format_is_supported(format, bindings))
56 return false;
57
58 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
59 if (util_format_get_blocksizebits(format) == 3 * 32)
60 return false;
61
62 if (bindings & PIPE_BIND_LINEAR)
63 if (util_format_is_depth_or_stencil(format) ||
64 (target != PIPE_TEXTURE_1D &&
65 target != PIPE_TEXTURE_2D &&
66 target != PIPE_TEXTURE_RECT) ||
67 sample_count > 1)
68 return false;
69
70 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
71 */
72 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
73 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
74 /* The claim is that this should work on GM107 but it doesn't. Need to
75 * test further and figure out if it's a nouveau issue or a HW one.
76 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
77 */
78 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
79 return false;
80
81 /* transfers & shared are always supported */
82 bindings &= ~(PIPE_BIND_TRANSFER_READ |
83 PIPE_BIND_TRANSFER_WRITE |
84 PIPE_BIND_LINEAR |
85 PIPE_BIND_SHARED);
86
87 return (( nvc0_format_table[format].usage |
88 nvc0_vertex_format[format].usage) & bindings) == bindings;
89 }
90
91 static int
92 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
93 {
94 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
95 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
96
97 switch (param) {
98 /* non-boolean caps */
99 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
100 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
101 return 15;
102 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
103 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
104 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
105 return 2048;
106 case PIPE_CAP_MIN_TEXEL_OFFSET:
107 return -8;
108 case PIPE_CAP_MAX_TEXEL_OFFSET:
109 return 7;
110 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
111 return -32;
112 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
113 return 31;
114 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
115 return 128 * 1024 * 1024;
116 case PIPE_CAP_GLSL_FEATURE_LEVEL:
117 return 410;
118 case PIPE_CAP_MAX_RENDER_TARGETS:
119 return 8;
120 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
121 return 1;
122 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
123 return 4;
124 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
125 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
126 return 128;
127 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
128 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
129 return 1024;
130 case PIPE_CAP_MAX_VERTEX_STREAMS:
131 return 4;
132 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
133 return 2048;
134 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
135 return 256;
136 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
137 return 16; /* 256 for binding as RT, but that's not possible in GL */
138 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
139 return 16;
140 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
141 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
142 case PIPE_CAP_MAX_VIEWPORTS:
143 return NVC0_MAX_VIEWPORTS;
144 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
145 return 4;
146 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
147 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
148 case PIPE_CAP_ENDIANNESS:
149 return PIPE_ENDIAN_LITTLE;
150 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
151 return 30;
152
153 /* supported caps */
154 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
155 case PIPE_CAP_TEXTURE_SWIZZLE:
156 case PIPE_CAP_TEXTURE_SHADOW_MAP:
157 case PIPE_CAP_NPOT_TEXTURES:
158 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
159 case PIPE_CAP_ANISOTROPIC_FILTER:
160 case PIPE_CAP_SEAMLESS_CUBE_MAP:
161 case PIPE_CAP_CUBE_MAP_ARRAY:
162 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
163 case PIPE_CAP_TEXTURE_MULTISAMPLE:
164 case PIPE_CAP_TWO_SIDED_STENCIL:
165 case PIPE_CAP_DEPTH_CLIP_DISABLE:
166 case PIPE_CAP_POINT_SPRITE:
167 case PIPE_CAP_TGSI_TEXCOORD:
168 case PIPE_CAP_SM3:
169 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
170 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
171 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
172 case PIPE_CAP_QUERY_TIMESTAMP:
173 case PIPE_CAP_QUERY_TIME_ELAPSED:
174 case PIPE_CAP_OCCLUSION_QUERY:
175 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
176 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
177 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
178 case PIPE_CAP_INDEP_BLEND_ENABLE:
179 case PIPE_CAP_INDEP_BLEND_FUNC:
180 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
181 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
182 case PIPE_CAP_PRIMITIVE_RESTART:
183 case PIPE_CAP_TGSI_INSTANCEID:
184 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
185 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
186 case PIPE_CAP_CONDITIONAL_RENDER:
187 case PIPE_CAP_TEXTURE_BARRIER:
188 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
189 case PIPE_CAP_START_INSTANCE:
190 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
191 case PIPE_CAP_DRAW_INDIRECT:
192 case PIPE_CAP_USER_CONSTANT_BUFFERS:
193 case PIPE_CAP_USER_INDEX_BUFFERS:
194 case PIPE_CAP_USER_VERTEX_BUFFERS:
195 case PIPE_CAP_TEXTURE_QUERY_LOD:
196 case PIPE_CAP_SAMPLE_SHADING:
197 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
198 case PIPE_CAP_TEXTURE_GATHER_SM5:
199 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
200 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
201 case PIPE_CAP_SAMPLER_VIEW_TARGET:
202 case PIPE_CAP_CLIP_HALFZ:
203 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
204 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
205 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
206 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
207 case PIPE_CAP_DEPTH_BOUNDS_TEST:
208 case PIPE_CAP_TGSI_TXQS:
209 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
210 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
211 case PIPE_CAP_SHAREABLE_SHADERS:
212 case PIPE_CAP_CLEAR_TEXTURE:
213 case PIPE_CAP_DRAW_PARAMETERS:
214 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
215 case PIPE_CAP_MULTI_DRAW_INDIRECT:
216 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
217 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
218 case PIPE_CAP_QUERY_BUFFER_OBJECT:
219 return 1;
220 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
221 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
222 case PIPE_CAP_COMPUTE:
223 if (debug_get_bool_option("NVF0_COMPUTE", false))
224 return 1;
225 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
226 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
227 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
228
229 /* unsupported caps */
230 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
231 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
232 case PIPE_CAP_SHADER_STENCIL_EXPORT:
233 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
234 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
235 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
236 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
237 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
238 case PIPE_CAP_FAKE_SW_MSAA:
239 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
240 case PIPE_CAP_VERTEXID_NOBASE:
241 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
242 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
243 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
244 case PIPE_CAP_INVALIDATE_BUFFER:
245 case PIPE_CAP_GENERATE_MIPMAP:
246 case PIPE_CAP_STRING_MARKER:
247 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
248 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
249 case PIPE_CAP_QUERY_MEMORY_INFO:
250 case PIPE_CAP_PCI_GROUP:
251 case PIPE_CAP_PCI_BUS:
252 case PIPE_CAP_PCI_DEVICE:
253 case PIPE_CAP_PCI_FUNCTION:
254 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
255 return 0;
256
257 case PIPE_CAP_VENDOR_ID:
258 return 0x10de;
259 case PIPE_CAP_DEVICE_ID: {
260 uint64_t device_id;
261 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
262 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
263 return -1;
264 }
265 return device_id;
266 }
267 case PIPE_CAP_ACCELERATED:
268 return 1;
269 case PIPE_CAP_VIDEO_MEMORY:
270 return dev->vram_size >> 20;
271 case PIPE_CAP_UMA:
272 return 0;
273 }
274
275 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
276 return 0;
277 }
278
279 static int
280 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
281 enum pipe_shader_cap param)
282 {
283 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
284
285 switch (shader) {
286 case PIPE_SHADER_VERTEX:
287 case PIPE_SHADER_GEOMETRY:
288 case PIPE_SHADER_FRAGMENT:
289 break;
290 case PIPE_SHADER_TESS_CTRL:
291 case PIPE_SHADER_TESS_EVAL:
292 if (class_3d >= GM107_3D_CLASS)
293 return 0;
294 break;
295 case PIPE_SHADER_COMPUTE:
296 if (!debug_get_bool_option("NVF0_COMPUTE", false))
297 if (class_3d > NVE4_3D_CLASS)
298 return 0;
299 break;
300 default:
301 return 0;
302 }
303
304 switch (param) {
305 case PIPE_SHADER_CAP_PREFERRED_IR:
306 return PIPE_SHADER_IR_TGSI;
307 case PIPE_SHADER_CAP_SUPPORTED_IRS:
308 if (class_3d == NVF0_3D_CLASS &&
309 !debug_get_bool_option("NVF0_COMPUTE", false))
310 return 0;
311 return 1 << PIPE_SHADER_IR_TGSI;
312 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
313 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
314 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
315 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
316 return 16384;
317 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
318 return 16;
319 case PIPE_SHADER_CAP_MAX_INPUTS:
320 if (shader == PIPE_SHADER_VERTEX)
321 return 32;
322 /* NOTE: These only count our slots for GENERIC varyings.
323 * The address space may be larger, but the actual hard limit seems to be
324 * less than what the address space layout permits, so don't add TEXCOORD,
325 * COLOR, etc. here.
326 */
327 if (shader == PIPE_SHADER_FRAGMENT)
328 return 0x1f0 / 16;
329 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
330 * and excludes 0x60 per-patch inputs.
331 */
332 return 0x200 / 16;
333 case PIPE_SHADER_CAP_MAX_OUTPUTS:
334 return 32;
335 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
336 return 65536;
337 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
338 return NVC0_MAX_PIPE_CONSTBUFS;
339 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
340 return shader != PIPE_SHADER_FRAGMENT;
341 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
342 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
343 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
344 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
345 return 1;
346 case PIPE_SHADER_CAP_MAX_PREDS:
347 return 0;
348 case PIPE_SHADER_CAP_MAX_TEMPS:
349 return NVC0_CAP_MAX_PROGRAM_TEMPS;
350 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
351 return 1;
352 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
353 return 1;
354 case PIPE_SHADER_CAP_SUBROUTINES:
355 return 1;
356 case PIPE_SHADER_CAP_INTEGERS:
357 return 1;
358 case PIPE_SHADER_CAP_DOUBLES:
359 return 1;
360 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
361 return 1;
362 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
363 return 1;
364 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
365 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
366 return 0;
367 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
368 return NVC0_MAX_BUFFERS;
369 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
370 return 16; /* would be 32 in linked (OpenGL-style) mode */
371 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
372 return 16; /* XXX not sure if more are really safe */
373 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
374 return 32;
375 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
376 return 0;
377 default:
378 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
379 return 0;
380 }
381 }
382
383 static float
384 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
385 {
386 switch (param) {
387 case PIPE_CAPF_MAX_LINE_WIDTH:
388 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
389 return 10.0f;
390 case PIPE_CAPF_MAX_POINT_WIDTH:
391 return 63.0f;
392 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
393 return 63.375f;
394 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
395 return 16.0f;
396 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
397 return 15.0f;
398 case PIPE_CAPF_GUARD_BAND_LEFT:
399 case PIPE_CAPF_GUARD_BAND_TOP:
400 return 0.0f;
401 case PIPE_CAPF_GUARD_BAND_RIGHT:
402 case PIPE_CAPF_GUARD_BAND_BOTTOM:
403 return 0.0f; /* that or infinity */
404 }
405
406 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
407 return 0.0f;
408 }
409
410 static int
411 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
412 enum pipe_shader_ir ir_type,
413 enum pipe_compute_cap param, void *data)
414 {
415 struct nvc0_screen *screen = nvc0_screen(pscreen);
416 const uint16_t obj_class = screen->compute->oclass;
417
418 #define RET(x) do { \
419 if (data) \
420 memcpy(data, x, sizeof(x)); \
421 return sizeof(x); \
422 } while (0)
423
424 switch (param) {
425 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
426 RET((uint64_t []) { 3 });
427 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
428 if (obj_class >= NVE4_COMPUTE_CLASS) {
429 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
430 } else {
431 RET(((uint64_t []) { 65535, 65535, 65535 }));
432 }
433 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
434 RET(((uint64_t []) { 1024, 1024, 64 }));
435 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
436 RET((uint64_t []) { 1024 });
437 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
438 RET((uint64_t []) { 1ULL << 40 });
439 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
440 RET((uint64_t []) { 48 << 10 });
441 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
442 RET((uint64_t []) { 512 << 10 });
443 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
444 RET((uint64_t []) { 4096 });
445 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
446 RET((uint32_t []) { 32 });
447 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
448 RET((uint64_t []) { 1ULL << 40 });
449 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
450 RET((uint32_t []) { 0 });
451 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
452 RET((uint32_t []) { screen->mp_count_compute });
453 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
454 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
455 default:
456 return 0;
457 }
458
459 #undef RET
460 }
461
462 static void
463 nvc0_screen_destroy(struct pipe_screen *pscreen)
464 {
465 struct nvc0_screen *screen = nvc0_screen(pscreen);
466
467 if (!nouveau_drm_screen_unref(&screen->base))
468 return;
469
470 if (screen->base.fence.current) {
471 struct nouveau_fence *current = NULL;
472
473 /* nouveau_fence_wait will create a new current fence, so wait on the
474 * _current_ one, and remove both.
475 */
476 nouveau_fence_ref(screen->base.fence.current, &current);
477 nouveau_fence_wait(current, NULL);
478 nouveau_fence_ref(NULL, &current);
479 nouveau_fence_ref(NULL, &screen->base.fence.current);
480 }
481 if (screen->base.pushbuf)
482 screen->base.pushbuf->user_priv = NULL;
483
484 if (screen->blitter)
485 nvc0_blitter_destroy(screen);
486 if (screen->pm.prog) {
487 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
488 nvc0_program_destroy(NULL, screen->pm.prog);
489 FREE(screen->pm.prog);
490 }
491
492 nouveau_bo_ref(NULL, &screen->text);
493 nouveau_bo_ref(NULL, &screen->uniform_bo);
494 nouveau_bo_ref(NULL, &screen->tls);
495 nouveau_bo_ref(NULL, &screen->txc);
496 nouveau_bo_ref(NULL, &screen->fence.bo);
497 nouveau_bo_ref(NULL, &screen->poly_cache);
498 nouveau_bo_ref(NULL, &screen->parm);
499
500 nouveau_heap_destroy(&screen->lib_code);
501 nouveau_heap_destroy(&screen->text_heap);
502
503 FREE(screen->tic.entries);
504
505 nouveau_object_del(&screen->eng3d);
506 nouveau_object_del(&screen->eng2d);
507 nouveau_object_del(&screen->m2mf);
508 nouveau_object_del(&screen->compute);
509 nouveau_object_del(&screen->nvsw);
510
511 nouveau_screen_fini(&screen->base);
512
513 FREE(screen);
514 }
515
516 static int
517 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
518 unsigned size, const uint32_t *data)
519 {
520 struct nouveau_pushbuf *push = screen->base.pushbuf;
521
522 size /= 4;
523
524 assert((pos + size) <= 0x800);
525
526 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
527 PUSH_DATA (push, (m - 0x3800) / 8);
528 PUSH_DATA (push, pos);
529 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
530 PUSH_DATA (push, pos);
531 PUSH_DATAp(push, data, size);
532
533 return pos + size;
534 }
535
536 static void
537 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
538 {
539 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
540 PUSH_DATA (push, 0xff);
541 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
542 PUSH_DATA (push, 0xff);
543 PUSH_DATA (push, 0xff);
544 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
545 PUSH_DATA (push, 0xff);
546 PUSH_DATA (push, 0xff);
547 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
548 PUSH_DATA (push, 0x3f);
549
550 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
551 PUSH_DATA (push, (3 << 16) | 3);
552 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
553 PUSH_DATA (push, (2 << 16) | 2);
554
555 if (obj_class < GM107_3D_CLASS) {
556 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
557 PUSH_DATA (push, 0);
558 }
559 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
560 PUSH_DATA (push, 0x10);
561 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
562 PUSH_DATA (push, 0x10);
563 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
564 PUSH_DATA (push, 0x10);
565 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
566 PUSH_DATA (push, 0x10);
567 PUSH_DATA (push, 0x10);
568 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
569 PUSH_DATA (push, 0x10);
570 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
571 PUSH_DATA (push, 0xe);
572
573 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
574 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
575 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
576 PUSH_DATA (push, 0);
577 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
578 PUSH_DATA (push, 3);
579
580 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
581 PUSH_DATA (push, 0x3fffff);
582 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
583 PUSH_DATA (push, 1);
584 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
585 PUSH_DATA (push, 1);
586
587 if (obj_class < GM107_3D_CLASS) {
588 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
589 PUSH_DATA (push, 3);
590
591 if (obj_class >= NVE4_3D_CLASS) {
592 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
593 PUSH_DATA (push, 1);
594 }
595 }
596
597 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
598 * are supposed to do */
599 }
600
601 static void
602 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
603 {
604 struct nvc0_screen *screen = nvc0_screen(pscreen);
605 struct nouveau_pushbuf *push = screen->base.pushbuf;
606
607 /* we need to do it after possible flush in MARK_RING */
608 *sequence = ++screen->base.fence.sequence;
609
610 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
611 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
612 PUSH_DATAh(push, screen->fence.bo->offset);
613 PUSH_DATA (push, screen->fence.bo->offset);
614 PUSH_DATA (push, *sequence);
615 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
616 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
617 }
618
619 static u32
620 nvc0_screen_fence_update(struct pipe_screen *pscreen)
621 {
622 struct nvc0_screen *screen = nvc0_screen(pscreen);
623 return screen->fence.map[0];
624 }
625
626 static int
627 nvc0_screen_init_compute(struct nvc0_screen *screen)
628 {
629 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
630
631 switch (screen->base.device->chipset & ~0xf) {
632 case 0xc0:
633 case 0xd0:
634 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
635 case 0xe0:
636 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
637 case 0xf0:
638 case 0x100:
639 case 0x110:
640 if (debug_get_bool_option("NVF0_COMPUTE", false))
641 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
642 case 0x120:
643 return 0;
644 default:
645 return -1;
646 }
647 }
648
649 bool
650 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
651 uint32_t lpos, uint32_t lneg, uint32_t cstack)
652 {
653 struct nouveau_bo *bo = NULL;
654 int ret;
655 uint64_t size = (lpos + lneg) * 32 + cstack;
656
657 if (size >= (1 << 20)) {
658 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
659 return false;
660 }
661
662 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
663 size = align(size, 0x8000);
664 size *= screen->mp_count;
665
666 size = align(size, 1 << 17);
667
668 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
669 NULL, &bo);
670 if (ret) {
671 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
672 return false;
673 }
674 nouveau_bo_ref(NULL, &screen->tls);
675 screen->tls = bo;
676 return true;
677 }
678
679 #define FAIL_SCREEN_INIT(str, err) \
680 do { \
681 NOUVEAU_ERR(str, err); \
682 goto fail; \
683 } while(0)
684
685 struct nouveau_screen *
686 nvc0_screen_create(struct nouveau_device *dev)
687 {
688 struct nvc0_screen *screen;
689 struct pipe_screen *pscreen;
690 struct nouveau_object *chan;
691 struct nouveau_pushbuf *push;
692 uint64_t value;
693 uint32_t obj_class;
694 uint32_t flags;
695 int ret;
696 unsigned i;
697
698 switch (dev->chipset & ~0xf) {
699 case 0xc0:
700 case 0xd0:
701 case 0xe0:
702 case 0xf0:
703 case 0x100:
704 case 0x110:
705 case 0x120:
706 break;
707 default:
708 return NULL;
709 }
710
711 screen = CALLOC_STRUCT(nvc0_screen);
712 if (!screen)
713 return NULL;
714 pscreen = &screen->base.base;
715 pscreen->destroy = nvc0_screen_destroy;
716
717 ret = nouveau_screen_init(&screen->base, dev);
718 if (ret) {
719 nvc0_screen_destroy(pscreen);
720 return NULL;
721 }
722 chan = screen->base.channel;
723 push = screen->base.pushbuf;
724 push->user_priv = screen;
725 push->rsvd_kick = 5;
726
727 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
728 PIPE_BIND_SHADER_BUFFER |
729 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
730 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
731 screen->base.sysmem_bindings |=
732 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
733
734 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
735 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
736 screen->base.vidmem_bindings = 0;
737 }
738
739 pscreen->context_create = nvc0_create;
740 pscreen->is_format_supported = nvc0_screen_is_format_supported;
741 pscreen->get_param = nvc0_screen_get_param;
742 pscreen->get_shader_param = nvc0_screen_get_shader_param;
743 pscreen->get_paramf = nvc0_screen_get_paramf;
744 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
745 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
746
747 nvc0_screen_init_resource_functions(pscreen);
748
749 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
750 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
751
752 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
753 if (screen->base.drm->version >= 0x01000202)
754 flags |= NOUVEAU_BO_COHERENT;
755
756 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
757 if (ret)
758 goto fail;
759 nouveau_bo_map(screen->fence.bo, 0, NULL);
760 screen->fence.map = screen->fence.bo->map;
761 screen->base.fence.emit = nvc0_screen_fence_emit;
762 screen->base.fence.update = nvc0_screen_fence_update;
763
764
765 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
766 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
767 if (ret)
768 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
769
770 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
771 PUSH_DATA (push, screen->nvsw->handle);
772
773 switch (dev->chipset & ~0xf) {
774 case 0x120:
775 case 0x110:
776 case 0x100:
777 case 0xf0:
778 obj_class = NVF0_P2MF_CLASS;
779 break;
780 case 0xe0:
781 obj_class = NVE4_P2MF_CLASS;
782 break;
783 default:
784 obj_class = NVC0_M2MF_CLASS;
785 break;
786 }
787 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
788 &screen->m2mf);
789 if (ret)
790 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
791
792 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
793 PUSH_DATA (push, screen->m2mf->oclass);
794 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
795 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
796 PUSH_DATA (push, 0xa0b5);
797 }
798
799 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
800 &screen->eng2d);
801 if (ret)
802 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
803
804 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
805 PUSH_DATA (push, screen->eng2d->oclass);
806 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
807 PUSH_DATA (push, 0);
808 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
809 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
810 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
811 PUSH_DATA (push, 0);
812 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
813 PUSH_DATA (push, 0);
814 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
815 PUSH_DATA (push, 0x3f);
816 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
817 PUSH_DATA (push, 1);
818 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
819 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
820
821 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
822 PUSH_DATAh(push, screen->fence.bo->offset + 16);
823 PUSH_DATA (push, screen->fence.bo->offset + 16);
824
825 switch (dev->chipset & ~0xf) {
826 case 0x120:
827 obj_class = GM200_3D_CLASS;
828 break;
829 case 0x110:
830 obj_class = GM107_3D_CLASS;
831 break;
832 case 0x100:
833 case 0xf0:
834 obj_class = NVF0_3D_CLASS;
835 break;
836 case 0xe0:
837 switch (dev->chipset) {
838 case 0xea:
839 obj_class = NVEA_3D_CLASS;
840 break;
841 default:
842 obj_class = NVE4_3D_CLASS;
843 break;
844 }
845 break;
846 case 0xd0:
847 obj_class = NVC8_3D_CLASS;
848 break;
849 case 0xc0:
850 default:
851 switch (dev->chipset) {
852 case 0xc8:
853 obj_class = NVC8_3D_CLASS;
854 break;
855 case 0xc1:
856 obj_class = NVC1_3D_CLASS;
857 break;
858 default:
859 obj_class = NVC0_3D_CLASS;
860 break;
861 }
862 break;
863 }
864 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
865 &screen->eng3d);
866 if (ret)
867 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
868 screen->base.class_3d = obj_class;
869
870 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
871 PUSH_DATA (push, screen->eng3d->oclass);
872
873 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
874 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
875
876 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
877 /* kill shaders after about 1 second (at 100 MHz) */
878 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
879 PUSH_DATA (push, 0x17);
880 }
881
882 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
883 screen->base.drm->version >= 0x01000101);
884 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
885 for (i = 0; i < 8; ++i)
886 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
887
888 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
889 PUSH_DATA (push, 1);
890
891 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
892 PUSH_DATA (push, 0);
893 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
894 PUSH_DATA (push, 0);
895 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
896 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
897 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
898 PUSH_DATA (push, 0);
899 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
900 PUSH_DATA (push, 1);
901 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
902 PUSH_DATA (push, 1);
903 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
904 PUSH_DATA (push, 1);
905 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
906 PUSH_DATA (push, 0);
907 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
908 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
909 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
910 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
911 } else {
912 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
913 PUSH_DATA (push, 15);
914 }
915 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
916 PUSH_DATA (push, 8); /* 128 */
917 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
918 PUSH_DATA (push, 1);
919 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
920 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
921 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
922 }
923
924 nvc0_magic_3d_init(push, screen->eng3d->oclass);
925
926 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
927 &screen->text);
928 if (ret)
929 goto fail;
930
931 /* XXX: getting a page fault at the end of the code buffer every few
932 * launches, don't use the last 256 bytes to work around them - prefetch ?
933 */
934 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
935
936 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
937 &screen->uniform_bo);
938 if (ret)
939 goto fail;
940
941 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
942
943 for (i = 0; i < 5; ++i) {
944 /* TIC and TSC entries for each unit (nve4+ only) */
945 /* auxiliary constants (6 user clip planes, base instance id) */
946 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
947 PUSH_DATA (push, 1024);
948 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
949 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
950 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
951 PUSH_DATA (push, (15 << 4) | 1);
952 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
953 unsigned j;
954 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
955 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
956 for (j = 0; j < 8; ++j)
957 PUSH_DATA(push, j);
958 } else {
959 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
960 PUSH_DATA (push, 0x54);
961 }
962 }
963 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
964 PUSH_DATA (push, 0);
965
966 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
967 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
968 PUSH_DATA (push, 256);
969 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
970 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
971 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
972 PUSH_DATA (push, 0);
973 PUSH_DATAf(push, 0.0f);
974 PUSH_DATAf(push, 0.0f);
975 PUSH_DATAf(push, 0.0f);
976 PUSH_DATAf(push, 0.0f);
977 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
978 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
979 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
980
981 if (screen->base.drm->version >= 0x01000101) {
982 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
983 if (ret) {
984 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
985 goto fail;
986 }
987 } else {
988 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
989 value = (8 << 8) | 4;
990 else
991 value = (16 << 8) | 4;
992 }
993 screen->gpc_count = value & 0x000000ff;
994 screen->mp_count = value >> 8;
995 screen->mp_count_compute = screen->mp_count;
996
997 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
998
999 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
1000 PUSH_DATAh(push, screen->text->offset);
1001 PUSH_DATA (push, screen->text->offset);
1002 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1003 PUSH_DATAh(push, screen->tls->offset);
1004 PUSH_DATA (push, screen->tls->offset);
1005 PUSH_DATA (push, screen->tls->size >> 32);
1006 PUSH_DATA (push, screen->tls->size);
1007 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1008 PUSH_DATA (push, 0);
1009 /* Reduce likelihood of collision with real buffers by placing the hole at
1010 * the top of the 4G area. This will have to be dealt with for real
1011 * eventually by blocking off that area from the VM.
1012 */
1013 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1014 PUSH_DATA (push, 0xff << 24);
1015
1016 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1017 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1018 &screen->poly_cache);
1019 if (ret)
1020 goto fail;
1021
1022 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1023 PUSH_DATAh(push, screen->poly_cache->offset);
1024 PUSH_DATA (push, screen->poly_cache->offset);
1025 PUSH_DATA (push, 3);
1026 }
1027
1028 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1029 &screen->txc);
1030 if (ret)
1031 goto fail;
1032
1033 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1034 PUSH_DATAh(push, screen->txc->offset);
1035 PUSH_DATA (push, screen->txc->offset);
1036 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1037 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1038 screen->tic.maxwell = true;
1039 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1040 screen->tic.maxwell =
1041 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1042 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1043 }
1044 }
1045
1046 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1047 PUSH_DATAh(push, screen->txc->offset + 65536);
1048 PUSH_DATA (push, screen->txc->offset + 65536);
1049 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1050
1051 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1052 PUSH_DATA (push, 0);
1053 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1054 PUSH_DATA (push, 0);
1055 PUSH_DATA (push, 0);
1056 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1057 PUSH_DATA (push, 0x3f);
1058
1059 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1060 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1061 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1062 for (i = 0; i < 8 * 2; ++i)
1063 PUSH_DATA(push, 0);
1064 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1065 PUSH_DATA (push, 0);
1066 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1067 PUSH_DATA (push, 0);
1068
1069 /* neither scissors, viewport nor stencil mask should affect clears */
1070 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1071 PUSH_DATA (push, 0);
1072
1073 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1074 PUSH_DATA (push, 1);
1075 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1076 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1077 PUSH_DATAf(push, 0.0f);
1078 PUSH_DATAf(push, 1.0f);
1079 }
1080 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1081 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1082
1083 /* We use scissors instead of exact view volume clipping,
1084 * so they're always enabled.
1085 */
1086 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1087 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1088 PUSH_DATA (push, 1);
1089 PUSH_DATA (push, 8192 << 16);
1090 PUSH_DATA (push, 8192 << 16);
1091 }
1092
1093 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1094
1095 i = 0;
1096 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1097 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1098 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1099 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1100 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1101 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1102 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1103 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1104 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1105 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1106 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1107 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1108 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1109
1110 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1111 PUSH_DATA (push, 1);
1112 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1113 PUSH_DATA (push, 1);
1114 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1115 PUSH_DATA (push, 0x40);
1116 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1117 PUSH_DATA (push, 0);
1118 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1119 PUSH_DATA (push, 0x30);
1120 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1121 PUSH_DATA (push, 3);
1122 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1123 PUSH_DATA (push, 0x20);
1124 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1125 PUSH_DATA (push, 0x00);
1126 screen->save_state.patch_vertices = 3;
1127
1128 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1129 PUSH_DATA (push, 0);
1130 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1131 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1132
1133 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1134
1135 if (nvc0_screen_init_compute(screen))
1136 goto fail;
1137
1138 PUSH_KICK (push);
1139
1140 screen->tic.entries = CALLOC(4096, sizeof(void *));
1141 screen->tsc.entries = screen->tic.entries + 2048;
1142
1143 if (!nvc0_blitter_create(screen))
1144 goto fail;
1145
1146 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1147
1148 return &screen->base;
1149
1150 fail:
1151 screen->base.base.context_create = NULL;
1152 return &screen->base;
1153 }
1154
1155 int
1156 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1157 {
1158 int i = screen->tic.next;
1159
1160 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1161 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1162
1163 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1164
1165 if (screen->tic.entries[i])
1166 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1167
1168 screen->tic.entries[i] = entry;
1169 return i;
1170 }
1171
1172 int
1173 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1174 {
1175 int i = screen->tsc.next;
1176
1177 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1178 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1179
1180 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1181
1182 if (screen->tsc.entries[i])
1183 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1184
1185 screen->tsc.entries[i] = entry;
1186 return i;
1187 }