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c6d9b91cedecc6a6f347052ed8d682f1129de003
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/mme/com9097.mme.h"
36
37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
39 #endif
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 if (sample_count > 8)
49 return FALSE;
50 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
51 return FALSE;
52
53 if (!util_format_is_supported(format, bindings))
54 return FALSE;
55
56 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
57 if (util_format_get_blocksizebits(format) == 3 * 32)
58 return FALSE;
59
60 /* transfers & shared are always supported */
61 bindings &= ~(PIPE_BIND_TRANSFER_READ |
62 PIPE_BIND_TRANSFER_WRITE |
63 PIPE_BIND_SHARED);
64
65 return (nvc0_format_table[format].usage & bindings) == bindings;
66 }
67
68 static int
69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
70 {
71 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 65536;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 400;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
109 return 256;
110 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
111 return 1; /* 256 for binding as RT, but that's not possible in GL */
112 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
113 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
114 case PIPE_CAP_MAX_VIEWPORTS:
115 return NVC0_MAX_VIEWPORTS;
116 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
117 return 4;
118 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
119 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
120 case PIPE_CAP_ENDIANNESS:
121 return PIPE_ENDIAN_LITTLE;
122
123 /* supported caps */
124 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
125 case PIPE_CAP_TEXTURE_SWIZZLE:
126 case PIPE_CAP_TEXTURE_SHADOW_MAP:
127 case PIPE_CAP_NPOT_TEXTURES:
128 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
129 case PIPE_CAP_ANISOTROPIC_FILTER:
130 case PIPE_CAP_SEAMLESS_CUBE_MAP:
131 case PIPE_CAP_CUBE_MAP_ARRAY:
132 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
133 case PIPE_CAP_TEXTURE_MULTISAMPLE:
134 case PIPE_CAP_TWO_SIDED_STENCIL:
135 case PIPE_CAP_DEPTH_CLIP_DISABLE:
136 case PIPE_CAP_POINT_SPRITE:
137 case PIPE_CAP_TGSI_TEXCOORD:
138 case PIPE_CAP_SM3:
139 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
140 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
141 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
142 case PIPE_CAP_QUERY_TIMESTAMP:
143 case PIPE_CAP_QUERY_TIME_ELAPSED:
144 case PIPE_CAP_OCCLUSION_QUERY:
145 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
146 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
147 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
148 case PIPE_CAP_INDEP_BLEND_ENABLE:
149 case PIPE_CAP_INDEP_BLEND_FUNC:
150 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
151 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
152 case PIPE_CAP_PRIMITIVE_RESTART:
153 case PIPE_CAP_TGSI_INSTANCEID:
154 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
155 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
156 case PIPE_CAP_CONDITIONAL_RENDER:
157 case PIPE_CAP_TEXTURE_BARRIER:
158 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
159 case PIPE_CAP_START_INSTANCE:
160 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
161 case PIPE_CAP_DRAW_INDIRECT:
162 case PIPE_CAP_USER_CONSTANT_BUFFERS:
163 case PIPE_CAP_USER_INDEX_BUFFERS:
164 case PIPE_CAP_USER_VERTEX_BUFFERS:
165 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
166 case PIPE_CAP_TEXTURE_QUERY_LOD:
167 case PIPE_CAP_SAMPLE_SHADING:
168 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
169 case PIPE_CAP_TEXTURE_GATHER_SM5:
170 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
171 return 1;
172 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
173 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
174 case PIPE_CAP_COMPUTE:
175 return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
176
177 /* unsupported caps */
178 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
179 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
180 case PIPE_CAP_SHADER_STENCIL_EXPORT:
181 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
182 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
183 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
184 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
185 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
186 case PIPE_CAP_FAKE_SW_MSAA:
187 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
188 return 0;
189 }
190
191 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
192 return 0;
193 }
194
195 static int
196 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
197 enum pipe_shader_cap param)
198 {
199 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
200
201 switch (shader) {
202 case PIPE_SHADER_VERTEX:
203 /*
204 case PIPE_SHADER_TESSELLATION_CONTROL:
205 case PIPE_SHADER_TESSELLATION_EVALUATION:
206 */
207 case PIPE_SHADER_GEOMETRY:
208 case PIPE_SHADER_FRAGMENT:
209 break;
210 case PIPE_SHADER_COMPUTE:
211 if (class_3d != NVE4_3D_CLASS)
212 return 0;
213 break;
214 default:
215 return 0;
216 }
217
218 switch (param) {
219 case PIPE_SHADER_CAP_PREFERRED_IR:
220 return PIPE_SHADER_IR_TGSI;
221 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
222 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
223 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
224 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
225 return 16384;
226 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
227 return 16;
228 case PIPE_SHADER_CAP_MAX_INPUTS:
229 if (shader == PIPE_SHADER_VERTEX)
230 return 32;
231 /* NOTE: These only count our slots for GENERIC varyings.
232 * The address space may be larger, but the actual hard limit seems to be
233 * less than what the address space layout permits, so don't add TEXCOORD,
234 * COLOR, etc. here.
235 */
236 if (shader == PIPE_SHADER_FRAGMENT)
237 return 0x1f0 / 16;
238 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
239 * and excludes 0x60 per-patch inputs.
240 */
241 return 0x200 / 16;
242 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
243 return 65536;
244 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
245 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
246 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
247 return NVC0_MAX_PIPE_CONSTBUFS;
248 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
249 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
250 return shader != PIPE_SHADER_FRAGMENT;
251 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
252 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
253 return 1;
254 case PIPE_SHADER_CAP_MAX_PREDS:
255 return 0;
256 case PIPE_SHADER_CAP_MAX_TEMPS:
257 return NVC0_CAP_MAX_PROGRAM_TEMPS;
258 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
259 return 1;
260 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
261 return 0;
262 case PIPE_SHADER_CAP_SUBROUTINES:
263 return 1;
264 case PIPE_SHADER_CAP_INTEGERS:
265 return 1;
266 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
267 return 16; /* would be 32 in linked (OpenGL-style) mode */
268 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
269 return 16; /* XXX not sure if more are really safe */
270 default:
271 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
272 return 0;
273 }
274 }
275
276 static float
277 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
278 {
279 switch (param) {
280 case PIPE_CAPF_MAX_LINE_WIDTH:
281 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
282 return 10.0f;
283 case PIPE_CAPF_MAX_POINT_WIDTH:
284 return 63.0f;
285 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
286 return 63.375f;
287 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
288 return 16.0f;
289 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
290 return 15.0f;
291 case PIPE_CAPF_GUARD_BAND_LEFT:
292 case PIPE_CAPF_GUARD_BAND_TOP:
293 return 0.0f;
294 case PIPE_CAPF_GUARD_BAND_RIGHT:
295 case PIPE_CAPF_GUARD_BAND_BOTTOM:
296 return 0.0f; /* that or infinity */
297 }
298
299 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
300 return 0.0f;
301 }
302
303 static int
304 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
305 enum pipe_compute_cap param, void *data)
306 {
307 uint64_t *data64 = (uint64_t *)data;
308 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
309
310 switch (param) {
311 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
312 data64[0] = 3;
313 return 8;
314 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
315 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
316 data64[1] = 65535;
317 data64[2] = 65535;
318 return 24;
319 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
320 data64[0] = 1024;
321 data64[1] = 1024;
322 data64[2] = 64;
323 return 24;
324 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
325 data64[0] = 1024;
326 return 8;
327 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
328 data64[0] = (uint64_t)1 << 40;
329 return 8;
330 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
331 data64[0] = 48 << 10;
332 return 8;
333 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
334 data64[0] = 512 << 10;
335 return 8;
336 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
337 data64[0] = 4096;
338 return 8;
339 default:
340 return 0;
341 }
342 }
343
344 static void
345 nvc0_screen_destroy(struct pipe_screen *pscreen)
346 {
347 struct nvc0_screen *screen = nvc0_screen(pscreen);
348
349 if (!nouveau_drm_screen_unref(&screen->base))
350 return;
351
352 if (screen->base.fence.current) {
353 struct nouveau_fence *current = NULL;
354
355 /* nouveau_fence_wait will create a new current fence, so wait on the
356 * _current_ one, and remove both.
357 */
358 nouveau_fence_ref(screen->base.fence.current, &current);
359 nouveau_fence_wait(current);
360 nouveau_fence_ref(NULL, &current);
361 nouveau_fence_ref(NULL, &screen->base.fence.current);
362 }
363 if (screen->base.pushbuf)
364 screen->base.pushbuf->user_priv = NULL;
365
366 if (screen->blitter)
367 nvc0_blitter_destroy(screen);
368 if (screen->pm.prog) {
369 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
370 nvc0_program_destroy(NULL, screen->pm.prog);
371 }
372
373 nouveau_bo_ref(NULL, &screen->text);
374 nouveau_bo_ref(NULL, &screen->uniform_bo);
375 nouveau_bo_ref(NULL, &screen->tls);
376 nouveau_bo_ref(NULL, &screen->txc);
377 nouveau_bo_ref(NULL, &screen->fence.bo);
378 nouveau_bo_ref(NULL, &screen->poly_cache);
379 nouveau_bo_ref(NULL, &screen->parm);
380
381 nouveau_heap_destroy(&screen->lib_code);
382 nouveau_heap_destroy(&screen->text_heap);
383
384 FREE(screen->tic.entries);
385
386 nouveau_mm_destroy(screen->mm_VRAM_fe0);
387
388 nouveau_object_del(&screen->eng3d);
389 nouveau_object_del(&screen->eng2d);
390 nouveau_object_del(&screen->m2mf);
391 nouveau_object_del(&screen->compute);
392 nouveau_object_del(&screen->nvsw);
393
394 nouveau_screen_fini(&screen->base);
395
396 FREE(screen);
397 }
398
399 static int
400 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
401 unsigned size, const uint32_t *data)
402 {
403 struct nouveau_pushbuf *push = screen->base.pushbuf;
404
405 size /= 4;
406
407 assert((pos + size) <= 0x800);
408
409 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
410 PUSH_DATA (push, (m - 0x3800) / 8);
411 PUSH_DATA (push, pos);
412 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
413 PUSH_DATA (push, pos);
414 PUSH_DATAp(push, data, size);
415
416 return pos + size;
417 }
418
419 static void
420 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
421 {
422 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
423 PUSH_DATA (push, 0xff);
424 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
425 PUSH_DATA (push, 0xff);
426 PUSH_DATA (push, 0xff);
427 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
428 PUSH_DATA (push, 0xff);
429 PUSH_DATA (push, 0xff);
430 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
431 PUSH_DATA (push, 0x3f);
432
433 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
434 PUSH_DATA (push, (3 << 16) | 3);
435 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
436 PUSH_DATA (push, (2 << 16) | 2);
437
438 if (obj_class < GM107_3D_CLASS) {
439 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
440 PUSH_DATA (push, 0);
441 }
442 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
443 PUSH_DATA (push, 0x10);
444 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
445 PUSH_DATA (push, 0x10);
446 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
447 PUSH_DATA (push, 0x10);
448 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
449 PUSH_DATA (push, 0x10);
450 PUSH_DATA (push, 0x10);
451 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
452 PUSH_DATA (push, 0x10);
453 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
454 PUSH_DATA (push, 0xe);
455
456 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
457 PUSH_DATA (push, 1 << 12);
458 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
459 PUSH_DATA (push, 0);
460 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
461 PUSH_DATA (push, 3);
462
463 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
464 PUSH_DATA (push, 0x3fffff);
465 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
466 PUSH_DATA (push, 1);
467 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
468 PUSH_DATA (push, 1);
469
470 if (obj_class < GM107_3D_CLASS) {
471 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
472 PUSH_DATA (push, 3);
473
474 if (obj_class >= NVE4_3D_CLASS) {
475 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
476 PUSH_DATA (push, 1);
477 }
478 }
479
480 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
481 * are supposed to do */
482 }
483
484 static void
485 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
486 {
487 struct nvc0_screen *screen = nvc0_screen(pscreen);
488 struct nouveau_pushbuf *push = screen->base.pushbuf;
489
490 /* we need to do it after possible flush in MARK_RING */
491 *sequence = ++screen->base.fence.sequence;
492
493 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
494 PUSH_DATAh(push, screen->fence.bo->offset);
495 PUSH_DATA (push, screen->fence.bo->offset);
496 PUSH_DATA (push, *sequence);
497 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
498 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
499 }
500
501 static u32
502 nvc0_screen_fence_update(struct pipe_screen *pscreen)
503 {
504 struct nvc0_screen *screen = nvc0_screen(pscreen);
505 return screen->fence.map[0];
506 }
507
508 static int
509 nvc0_screen_init_compute(struct nvc0_screen *screen)
510 {
511 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
512
513 switch (screen->base.device->chipset & ~0xf) {
514 case 0xc0:
515 case 0xd0:
516 /* Using COMPUTE has weird effects on 3D state, we need to
517 * investigate this further before enabling it by default.
518 */
519 if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
520 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
521 return 0;
522 case 0xe0:
523 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
524 case 0xf0:
525 case 0x100:
526 case 0x110:
527 return 0;
528 default:
529 return -1;
530 }
531 }
532
533 boolean
534 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
535 uint32_t lpos, uint32_t lneg, uint32_t cstack)
536 {
537 struct nouveau_bo *bo = NULL;
538 int ret;
539 uint64_t size = (lpos + lneg) * 32 + cstack;
540
541 if (size >= (1 << 20)) {
542 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
543 return FALSE;
544 }
545
546 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
547 size = align(size, 0x8000);
548 size *= screen->mp_count;
549
550 size = align(size, 1 << 17);
551
552 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
553 NULL, &bo);
554 if (ret) {
555 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
556 return FALSE;
557 }
558 nouveau_bo_ref(NULL, &screen->tls);
559 screen->tls = bo;
560 return TRUE;
561 }
562
563 #define FAIL_SCREEN_INIT(str, err) \
564 do { \
565 NOUVEAU_ERR(str, err); \
566 nvc0_screen_destroy(pscreen); \
567 return NULL; \
568 } while(0)
569
570 struct pipe_screen *
571 nvc0_screen_create(struct nouveau_device *dev)
572 {
573 struct nvc0_screen *screen;
574 struct pipe_screen *pscreen;
575 struct nouveau_object *chan;
576 struct nouveau_pushbuf *push;
577 uint64_t value;
578 uint32_t obj_class;
579 int ret;
580 unsigned i;
581 union nouveau_bo_config mm_config;
582
583 switch (dev->chipset & ~0xf) {
584 case 0xc0:
585 case 0xd0:
586 case 0xe0:
587 case 0xf0:
588 case 0x100:
589 case 0x110:
590 break;
591 default:
592 return NULL;
593 }
594
595 screen = CALLOC_STRUCT(nvc0_screen);
596 if (!screen)
597 return NULL;
598 pscreen = &screen->base.base;
599
600 ret = nouveau_screen_init(&screen->base, dev);
601 if (ret) {
602 nvc0_screen_destroy(pscreen);
603 return NULL;
604 }
605 chan = screen->base.channel;
606 push = screen->base.pushbuf;
607 push->user_priv = screen;
608 push->rsvd_kick = 5;
609
610 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
611 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
612 PIPE_BIND_COMMAND_ARGS_BUFFER;
613 screen->base.sysmem_bindings |=
614 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
615
616 pscreen->destroy = nvc0_screen_destroy;
617 pscreen->context_create = nvc0_create;
618 pscreen->is_format_supported = nvc0_screen_is_format_supported;
619 pscreen->get_param = nvc0_screen_get_param;
620 pscreen->get_shader_param = nvc0_screen_get_shader_param;
621 pscreen->get_paramf = nvc0_screen_get_paramf;
622 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
623
624 nvc0_screen_init_resource_functions(pscreen);
625
626 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
627 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
628
629 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
630 &screen->fence.bo);
631 if (ret)
632 goto fail;
633 nouveau_bo_map(screen->fence.bo, 0, NULL);
634 screen->fence.map = screen->fence.bo->map;
635 screen->base.fence.emit = nvc0_screen_fence_emit;
636 screen->base.fence.update = nvc0_screen_fence_update;
637
638
639 ret = nouveau_object_new(chan,
640 (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
641 NULL, 0, &screen->nvsw);
642 if (ret)
643 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
644
645
646 switch (dev->chipset & ~0xf) {
647 case 0x110:
648 case 0x100:
649 case 0xf0:
650 obj_class = NVF0_P2MF_CLASS;
651 break;
652 case 0xe0:
653 obj_class = NVE4_P2MF_CLASS;
654 break;
655 default:
656 obj_class = NVC0_M2MF_CLASS;
657 break;
658 }
659 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
660 &screen->m2mf);
661 if (ret)
662 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
663
664 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
665 PUSH_DATA (push, screen->m2mf->oclass);
666 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
667 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
668 PUSH_DATA (push, 0xa0b5);
669 }
670
671 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
672 &screen->eng2d);
673 if (ret)
674 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
675
676 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
677 PUSH_DATA (push, screen->eng2d->oclass);
678 BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
679 PUSH_DATA (push, 0);
680 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
681 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
682 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
683 PUSH_DATA (push, 0);
684 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
685 PUSH_DATA (push, 0);
686 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
687 PUSH_DATA (push, 0x3f);
688 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
689 PUSH_DATA (push, 1);
690 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
691 PUSH_DATA (push, NVC0_2D_COND_MODE_ALWAYS);
692
693 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
694 PUSH_DATAh(push, screen->fence.bo->offset + 16);
695 PUSH_DATA (push, screen->fence.bo->offset + 16);
696
697 switch (dev->chipset & ~0xf) {
698 case 0x110:
699 obj_class = GM107_3D_CLASS;
700 break;
701 case 0x100:
702 case 0xf0:
703 obj_class = NVF0_3D_CLASS;
704 break;
705 case 0xe0:
706 switch (dev->chipset) {
707 case 0xea:
708 obj_class = NVEA_3D_CLASS;
709 break;
710 default:
711 obj_class = NVE4_3D_CLASS;
712 break;
713 }
714 break;
715 case 0xd0:
716 obj_class = NVC8_3D_CLASS;
717 break;
718 case 0xc0:
719 default:
720 switch (dev->chipset) {
721 case 0xc8:
722 obj_class = NVC8_3D_CLASS;
723 break;
724 case 0xc1:
725 obj_class = NVC1_3D_CLASS;
726 break;
727 default:
728 obj_class = NVC0_3D_CLASS;
729 break;
730 }
731 break;
732 }
733 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
734 &screen->eng3d);
735 if (ret)
736 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
737 screen->base.class_3d = obj_class;
738
739 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
740 PUSH_DATA (push, screen->eng3d->oclass);
741
742 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
743 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
744
745 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
746 /* kill shaders after about 1 second (at 100 MHz) */
747 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
748 PUSH_DATA (push, 0x17);
749 }
750
751 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
752 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
753 for (i = 0; i < 8; ++i)
754 PUSH_DATA(push, dev->drm_version >= 0x01000101);
755
756 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
757 PUSH_DATA (push, 1);
758
759 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
760 PUSH_DATA (push, 0);
761 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
762 PUSH_DATA (push, 0);
763 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
764 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
765 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
766 PUSH_DATA (push, 0);
767 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
768 PUSH_DATA (push, 1);
769 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
770 PUSH_DATA (push, 0);
771 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
772 PUSH_DATA (push, 1);
773 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
774 PUSH_DATA (push, 1);
775 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
776 PUSH_DATA (push, 0);
777 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
778 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
779 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
780 } else {
781 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
782 PUSH_DATA (push, 15);
783 }
784 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
785 PUSH_DATA (push, 8); /* 128 */
786 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
787 PUSH_DATA (push, 1);
788 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
789 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
790 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
791 }
792
793 nvc0_magic_3d_init(push, screen->eng3d->oclass);
794
795 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
796 &screen->text);
797 if (ret)
798 goto fail;
799
800 /* XXX: getting a page fault at the end of the code buffer every few
801 * launches, don't use the last 256 bytes to work around them - prefetch ?
802 */
803 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
804
805 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
806 &screen->uniform_bo);
807 if (ret)
808 goto fail;
809
810 PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
811
812 for (i = 0; i < 5; ++i) {
813 /* TIC and TSC entries for each unit (nve4+ only) */
814 /* auxiliary constants (6 user clip planes, base instance id) */
815 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
816 PUSH_DATA (push, 512);
817 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
818 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
819 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
820 PUSH_DATA (push, (15 << 4) | 1);
821 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
822 unsigned j;
823 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
824 PUSH_DATA (push, 0);
825 for (j = 0; j < 8; ++j)
826 PUSH_DATA(push, j);
827 } else {
828 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
829 PUSH_DATA (push, 0x54);
830 }
831 }
832 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
833 PUSH_DATA (push, 0);
834
835 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
836 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
837 PUSH_DATA (push, 256);
838 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
839 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
840 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
841 PUSH_DATA (push, 0);
842 PUSH_DATAf(push, 0.0f);
843 PUSH_DATAf(push, 0.0f);
844 PUSH_DATAf(push, 0.0f);
845 PUSH_DATAf(push, 0.0f);
846 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
847 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
848 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
849
850 if (dev->drm_version >= 0x01000101) {
851 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
852 if (ret) {
853 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
854 goto fail;
855 }
856 } else {
857 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
858 value = (8 << 8) | 4;
859 else
860 value = (16 << 8) | 4;
861 }
862 screen->mp_count = value >> 8;
863 screen->mp_count_compute = screen->mp_count;
864
865 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
866
867 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
868 PUSH_DATAh(push, screen->text->offset);
869 PUSH_DATA (push, screen->text->offset);
870 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
871 PUSH_DATAh(push, screen->tls->offset);
872 PUSH_DATA (push, screen->tls->offset);
873 PUSH_DATA (push, screen->tls->size >> 32);
874 PUSH_DATA (push, screen->tls->size);
875 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
876 PUSH_DATA (push, 0);
877 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
878 PUSH_DATA (push, 0);
879
880 if (screen->eng3d->oclass < GM107_3D_CLASS) {
881 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
882 &screen->poly_cache);
883 if (ret)
884 goto fail;
885
886 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
887 PUSH_DATAh(push, screen->poly_cache->offset);
888 PUSH_DATA (push, screen->poly_cache->offset);
889 PUSH_DATA (push, 3);
890 }
891
892 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
893 &screen->txc);
894 if (ret)
895 goto fail;
896
897 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
898 PUSH_DATAh(push, screen->txc->offset);
899 PUSH_DATA (push, screen->txc->offset);
900 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
901
902 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
903 PUSH_DATAh(push, screen->txc->offset + 65536);
904 PUSH_DATA (push, screen->txc->offset + 65536);
905 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
906
907 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
908 PUSH_DATA (push, 0);
909 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
910 PUSH_DATA (push, 0);
911 PUSH_DATA (push, 0);
912 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
913 PUSH_DATA (push, 0x3f);
914
915 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
916 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
917 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
918 for (i = 0; i < 8 * 2; ++i)
919 PUSH_DATA(push, 0);
920 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
921 PUSH_DATA (push, 0);
922 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
923 PUSH_DATA (push, 0);
924
925 /* neither scissors, viewport nor stencil mask should affect clears */
926 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
927 PUSH_DATA (push, 0);
928
929 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
930 PUSH_DATA (push, 1);
931 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
932 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
933 PUSH_DATAf(push, 0.0f);
934 PUSH_DATAf(push, 1.0f);
935 }
936 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
937 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
938
939 /* We use scissors instead of exact view volume clipping,
940 * so they're always enabled.
941 */
942 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
943 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
944 PUSH_DATA (push, 1);
945 PUSH_DATA (push, 8192 << 16);
946 PUSH_DATA (push, 8192 << 16);
947 }
948
949 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
950
951 i = 0;
952 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
953 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
954 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
955 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
956 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
957 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
958 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
959 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
960 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
961
962 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
963 PUSH_DATA (push, 1);
964 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
965 PUSH_DATA (push, 1);
966 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
967 PUSH_DATA (push, 0x40);
968 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
969 PUSH_DATA (push, 0);
970 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
971 PUSH_DATA (push, 0x30);
972 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
973 PUSH_DATA (push, 3);
974 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
975 PUSH_DATA (push, 0x20);
976 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
977 PUSH_DATA (push, 0x00);
978
979 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
980 PUSH_DATA (push, 0);
981 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
982 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
983
984 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
985
986 if (nvc0_screen_init_compute(screen))
987 goto fail;
988
989 PUSH_KICK (push);
990
991 screen->tic.entries = CALLOC(4096, sizeof(void *));
992 screen->tsc.entries = screen->tic.entries + 2048;
993
994 mm_config.nvc0.tile_mode = 0;
995 mm_config.nvc0.memtype = 0xfe0;
996 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
997
998 if (!nvc0_blitter_create(screen))
999 goto fail;
1000
1001 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
1002
1003 return pscreen;
1004
1005 fail:
1006 nvc0_screen_destroy(pscreen);
1007 return NULL;
1008 }
1009
1010 int
1011 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1012 {
1013 int i = screen->tic.next;
1014
1015 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1016 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1017
1018 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1019
1020 if (screen->tic.entries[i])
1021 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1022
1023 screen->tic.entries[i] = entry;
1024 return i;
1025 }
1026
1027 int
1028 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1029 {
1030 int i = screen->tsc.next;
1031
1032 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1033 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1034
1035 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1036
1037 if (screen->tsc.entries[i])
1038 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1039
1040 screen->tsc.entries[i] = entry;
1041 return i;
1042 }