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gallium: add PIPE_SHADER_CAP_MAX_SHADER_IMAGES
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39
40 static boolean
41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
42 enum pipe_format format,
43 enum pipe_texture_target target,
44 unsigned sample_count,
45 unsigned bindings)
46 {
47 if (sample_count > 8)
48 return false;
49 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
50 return false;
51
52 if (!util_format_is_supported(format, bindings))
53 return false;
54
55 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
56 if (util_format_get_blocksizebits(format) == 3 * 32)
57 return false;
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
71 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
72
73 switch (param) {
74 /* non-boolean caps */
75 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
76 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
77 return 15;
78 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
79 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
80 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
81 return 2048;
82 case PIPE_CAP_MIN_TEXEL_OFFSET:
83 return -8;
84 case PIPE_CAP_MAX_TEXEL_OFFSET:
85 return 7;
86 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
87 return -32;
88 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
89 return 31;
90 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
91 return 128 * 1024 * 1024;
92 case PIPE_CAP_GLSL_FEATURE_LEVEL:
93 return 410;
94 case PIPE_CAP_MAX_RENDER_TARGETS:
95 return 8;
96 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
97 return 1;
98 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
99 return 4;
100 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
101 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
102 return 128;
103 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
104 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
105 return 1024;
106 case PIPE_CAP_MAX_VERTEX_STREAMS:
107 return 4;
108 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
109 return 2048;
110 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
111 return 256;
112 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
113 return 1; /* 256 for binding as RT, but that's not possible in GL */
114 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
115 return 16;
116 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
117 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
118 case PIPE_CAP_MAX_VIEWPORTS:
119 return NVC0_MAX_VIEWPORTS;
120 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
121 return 4;
122 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
123 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
124 case PIPE_CAP_ENDIANNESS:
125 return PIPE_ENDIAN_LITTLE;
126 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
127 return 30;
128
129 /* supported caps */
130 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
131 case PIPE_CAP_TEXTURE_SWIZZLE:
132 case PIPE_CAP_TEXTURE_SHADOW_MAP:
133 case PIPE_CAP_NPOT_TEXTURES:
134 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
135 case PIPE_CAP_ANISOTROPIC_FILTER:
136 case PIPE_CAP_SEAMLESS_CUBE_MAP:
137 case PIPE_CAP_CUBE_MAP_ARRAY:
138 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
139 case PIPE_CAP_TEXTURE_MULTISAMPLE:
140 case PIPE_CAP_TWO_SIDED_STENCIL:
141 case PIPE_CAP_DEPTH_CLIP_DISABLE:
142 case PIPE_CAP_POINT_SPRITE:
143 case PIPE_CAP_TGSI_TEXCOORD:
144 case PIPE_CAP_SM3:
145 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
146 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
147 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
148 case PIPE_CAP_QUERY_TIMESTAMP:
149 case PIPE_CAP_QUERY_TIME_ELAPSED:
150 case PIPE_CAP_OCCLUSION_QUERY:
151 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
152 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
153 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
154 case PIPE_CAP_INDEP_BLEND_ENABLE:
155 case PIPE_CAP_INDEP_BLEND_FUNC:
156 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
157 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
158 case PIPE_CAP_PRIMITIVE_RESTART:
159 case PIPE_CAP_TGSI_INSTANCEID:
160 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
161 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
162 case PIPE_CAP_CONDITIONAL_RENDER:
163 case PIPE_CAP_TEXTURE_BARRIER:
164 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
165 case PIPE_CAP_START_INSTANCE:
166 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
167 case PIPE_CAP_DRAW_INDIRECT:
168 case PIPE_CAP_USER_CONSTANT_BUFFERS:
169 case PIPE_CAP_USER_INDEX_BUFFERS:
170 case PIPE_CAP_USER_VERTEX_BUFFERS:
171 case PIPE_CAP_TEXTURE_QUERY_LOD:
172 case PIPE_CAP_SAMPLE_SHADING:
173 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
174 case PIPE_CAP_TEXTURE_GATHER_SM5:
175 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
176 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
177 case PIPE_CAP_SAMPLER_VIEW_TARGET:
178 case PIPE_CAP_CLIP_HALFZ:
179 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
180 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
181 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
182 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
183 case PIPE_CAP_DEPTH_BOUNDS_TEST:
184 case PIPE_CAP_TGSI_TXQS:
185 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
186 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
187 case PIPE_CAP_SHAREABLE_SHADERS:
188 case PIPE_CAP_CLEAR_TEXTURE:
189 case PIPE_CAP_DRAW_PARAMETERS:
190 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
191 case PIPE_CAP_MULTI_DRAW_INDIRECT:
192 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
193 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
194 case PIPE_CAP_QUERY_BUFFER_OBJECT:
195 return 1;
196 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
197 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
198 case PIPE_CAP_COMPUTE:
199 return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
200 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
201 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
202
203 /* unsupported caps */
204 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
205 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
206 case PIPE_CAP_SHADER_STENCIL_EXPORT:
207 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
208 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
209 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
210 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
211 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
212 case PIPE_CAP_FAKE_SW_MSAA:
213 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
214 case PIPE_CAP_VERTEXID_NOBASE:
215 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
216 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
217 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
218 case PIPE_CAP_INVALIDATE_BUFFER:
219 case PIPE_CAP_GENERATE_MIPMAP:
220 case PIPE_CAP_STRING_MARKER:
221 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
222 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
223 case PIPE_CAP_QUERY_MEMORY_INFO:
224 return 0;
225
226 case PIPE_CAP_VENDOR_ID:
227 return 0x10de;
228 case PIPE_CAP_DEVICE_ID: {
229 uint64_t device_id;
230 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
231 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
232 return -1;
233 }
234 return device_id;
235 }
236 case PIPE_CAP_ACCELERATED:
237 return 1;
238 case PIPE_CAP_VIDEO_MEMORY:
239 return dev->vram_size >> 20;
240 case PIPE_CAP_UMA:
241 return 0;
242 }
243
244 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
245 return 0;
246 }
247
248 static int
249 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
250 enum pipe_shader_cap param)
251 {
252 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
253
254 switch (shader) {
255 case PIPE_SHADER_VERTEX:
256 case PIPE_SHADER_GEOMETRY:
257 case PIPE_SHADER_FRAGMENT:
258 break;
259 case PIPE_SHADER_TESS_CTRL:
260 case PIPE_SHADER_TESS_EVAL:
261 if (class_3d >= GM107_3D_CLASS)
262 return 0;
263 break;
264 case PIPE_SHADER_COMPUTE:
265 if (class_3d > NVE4_3D_CLASS)
266 return 0;
267 break;
268 default:
269 return 0;
270 }
271
272 switch (param) {
273 case PIPE_SHADER_CAP_PREFERRED_IR:
274 return PIPE_SHADER_IR_TGSI;
275 case PIPE_SHADER_CAP_SUPPORTED_IRS:
276 return 0;
277 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
278 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
279 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
280 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
281 return 16384;
282 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
283 return 16;
284 case PIPE_SHADER_CAP_MAX_INPUTS:
285 if (shader == PIPE_SHADER_VERTEX)
286 return 32;
287 /* NOTE: These only count our slots for GENERIC varyings.
288 * The address space may be larger, but the actual hard limit seems to be
289 * less than what the address space layout permits, so don't add TEXCOORD,
290 * COLOR, etc. here.
291 */
292 if (shader == PIPE_SHADER_FRAGMENT)
293 return 0x1f0 / 16;
294 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
295 * and excludes 0x60 per-patch inputs.
296 */
297 return 0x200 / 16;
298 case PIPE_SHADER_CAP_MAX_OUTPUTS:
299 return 32;
300 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
301 return 65536;
302 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
303 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
304 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
305 return NVC0_MAX_PIPE_CONSTBUFS;
306 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
307 return shader != PIPE_SHADER_FRAGMENT;
308 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
309 return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
310 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
311 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
312 return 1;
313 case PIPE_SHADER_CAP_MAX_PREDS:
314 return 0;
315 case PIPE_SHADER_CAP_MAX_TEMPS:
316 return NVC0_CAP_MAX_PROGRAM_TEMPS;
317 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
318 return 1;
319 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
320 return 0;
321 case PIPE_SHADER_CAP_SUBROUTINES:
322 return 1;
323 case PIPE_SHADER_CAP_INTEGERS:
324 return 1;
325 case PIPE_SHADER_CAP_DOUBLES:
326 return 1;
327 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
328 return 1;
329 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
330 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
331 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
332 return 0;
333 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
334 return NVC0_MAX_BUFFERS;
335 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
336 return 16; /* would be 32 in linked (OpenGL-style) mode */
337 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
338 return 16; /* XXX not sure if more are really safe */
339 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
340 return 32;
341 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
342 return 0;
343 default:
344 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
345 return 0;
346 }
347 }
348
349 static float
350 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
351 {
352 switch (param) {
353 case PIPE_CAPF_MAX_LINE_WIDTH:
354 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
355 return 10.0f;
356 case PIPE_CAPF_MAX_POINT_WIDTH:
357 return 63.0f;
358 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
359 return 63.375f;
360 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
361 return 16.0f;
362 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
363 return 15.0f;
364 case PIPE_CAPF_GUARD_BAND_LEFT:
365 case PIPE_CAPF_GUARD_BAND_TOP:
366 return 0.0f;
367 case PIPE_CAPF_GUARD_BAND_RIGHT:
368 case PIPE_CAPF_GUARD_BAND_BOTTOM:
369 return 0.0f; /* that or infinity */
370 }
371
372 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
373 return 0.0f;
374 }
375
376 static int
377 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
378 enum pipe_compute_cap param, void *data)
379 {
380 struct nvc0_screen *screen = nvc0_screen(pscreen);
381 const uint16_t obj_class = screen->compute->oclass;
382
383 #define RET(x) do { \
384 if (data) \
385 memcpy(data, x, sizeof(x)); \
386 return sizeof(x); \
387 } while (0)
388
389 switch (param) {
390 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
391 RET((uint64_t []) { 3 });
392 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
393 if (obj_class >= NVE4_COMPUTE_CLASS) {
394 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
395 } else {
396 RET(((uint64_t []) { 65535, 65535, 65535 }));
397 }
398 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
399 RET(((uint64_t []) { 1024, 1024, 64 }));
400 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
401 RET((uint64_t []) { 1024 });
402 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
403 RET((uint64_t []) { 1ULL << 40 });
404 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
405 RET((uint64_t []) { 48 << 10 });
406 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
407 RET((uint64_t []) { 512 << 10 });
408 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
409 RET((uint64_t []) { 4096 });
410 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
411 RET((uint32_t []) { 32 });
412 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
413 RET((uint64_t []) { 1ULL << 40 });
414 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
415 RET((uint32_t []) { 0 });
416 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
417 RET((uint32_t []) { screen->mp_count_compute });
418 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
419 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
420 default:
421 return 0;
422 }
423
424 #undef RET
425 }
426
427 static void
428 nvc0_screen_destroy(struct pipe_screen *pscreen)
429 {
430 struct nvc0_screen *screen = nvc0_screen(pscreen);
431
432 if (!nouveau_drm_screen_unref(&screen->base))
433 return;
434
435 if (screen->base.fence.current) {
436 struct nouveau_fence *current = NULL;
437
438 /* nouveau_fence_wait will create a new current fence, so wait on the
439 * _current_ one, and remove both.
440 */
441 nouveau_fence_ref(screen->base.fence.current, &current);
442 nouveau_fence_wait(current, NULL);
443 nouveau_fence_ref(NULL, &current);
444 nouveau_fence_ref(NULL, &screen->base.fence.current);
445 }
446 if (screen->base.pushbuf)
447 screen->base.pushbuf->user_priv = NULL;
448
449 if (screen->blitter)
450 nvc0_blitter_destroy(screen);
451 if (screen->pm.prog) {
452 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
453 nvc0_program_destroy(NULL, screen->pm.prog);
454 FREE(screen->pm.prog);
455 }
456
457 nouveau_bo_ref(NULL, &screen->text);
458 nouveau_bo_ref(NULL, &screen->uniform_bo);
459 nouveau_bo_ref(NULL, &screen->tls);
460 nouveau_bo_ref(NULL, &screen->txc);
461 nouveau_bo_ref(NULL, &screen->fence.bo);
462 nouveau_bo_ref(NULL, &screen->poly_cache);
463 nouveau_bo_ref(NULL, &screen->parm);
464
465 nouveau_heap_destroy(&screen->lib_code);
466 nouveau_heap_destroy(&screen->text_heap);
467
468 FREE(screen->tic.entries);
469
470 nouveau_object_del(&screen->eng3d);
471 nouveau_object_del(&screen->eng2d);
472 nouveau_object_del(&screen->m2mf);
473 nouveau_object_del(&screen->compute);
474 nouveau_object_del(&screen->nvsw);
475
476 nouveau_screen_fini(&screen->base);
477
478 FREE(screen);
479 }
480
481 static int
482 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
483 unsigned size, const uint32_t *data)
484 {
485 struct nouveau_pushbuf *push = screen->base.pushbuf;
486
487 size /= 4;
488
489 assert((pos + size) <= 0x800);
490
491 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
492 PUSH_DATA (push, (m - 0x3800) / 8);
493 PUSH_DATA (push, pos);
494 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
495 PUSH_DATA (push, pos);
496 PUSH_DATAp(push, data, size);
497
498 return pos + size;
499 }
500
501 static void
502 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
503 {
504 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
505 PUSH_DATA (push, 0xff);
506 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
507 PUSH_DATA (push, 0xff);
508 PUSH_DATA (push, 0xff);
509 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
510 PUSH_DATA (push, 0xff);
511 PUSH_DATA (push, 0xff);
512 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
513 PUSH_DATA (push, 0x3f);
514
515 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
516 PUSH_DATA (push, (3 << 16) | 3);
517 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
518 PUSH_DATA (push, (2 << 16) | 2);
519
520 if (obj_class < GM107_3D_CLASS) {
521 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
522 PUSH_DATA (push, 0);
523 }
524 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
525 PUSH_DATA (push, 0x10);
526 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
527 PUSH_DATA (push, 0x10);
528 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
529 PUSH_DATA (push, 0x10);
530 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
531 PUSH_DATA (push, 0x10);
532 PUSH_DATA (push, 0x10);
533 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
534 PUSH_DATA (push, 0x10);
535 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
536 PUSH_DATA (push, 0xe);
537
538 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
539 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
540 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
541 PUSH_DATA (push, 0);
542 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
543 PUSH_DATA (push, 3);
544
545 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
546 PUSH_DATA (push, 0x3fffff);
547 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
548 PUSH_DATA (push, 1);
549 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
550 PUSH_DATA (push, 1);
551
552 if (obj_class < GM107_3D_CLASS) {
553 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
554 PUSH_DATA (push, 3);
555
556 if (obj_class >= NVE4_3D_CLASS) {
557 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
558 PUSH_DATA (push, 1);
559 }
560 }
561
562 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
563 * are supposed to do */
564 }
565
566 static void
567 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
568 {
569 struct nvc0_screen *screen = nvc0_screen(pscreen);
570 struct nouveau_pushbuf *push = screen->base.pushbuf;
571
572 /* we need to do it after possible flush in MARK_RING */
573 *sequence = ++screen->base.fence.sequence;
574
575 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
576 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
577 PUSH_DATAh(push, screen->fence.bo->offset);
578 PUSH_DATA (push, screen->fence.bo->offset);
579 PUSH_DATA (push, *sequence);
580 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
581 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
582 }
583
584 static u32
585 nvc0_screen_fence_update(struct pipe_screen *pscreen)
586 {
587 struct nvc0_screen *screen = nvc0_screen(pscreen);
588 return screen->fence.map[0];
589 }
590
591 static int
592 nvc0_screen_init_compute(struct nvc0_screen *screen)
593 {
594 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
595
596 switch (screen->base.device->chipset & ~0xf) {
597 case 0xc0:
598 case 0xd0:
599 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
600 case 0xe0:
601 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
602 case 0xf0:
603 case 0x100:
604 case 0x110:
605 return 0;
606 default:
607 return -1;
608 }
609 }
610
611 bool
612 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
613 uint32_t lpos, uint32_t lneg, uint32_t cstack)
614 {
615 struct nouveau_bo *bo = NULL;
616 int ret;
617 uint64_t size = (lpos + lneg) * 32 + cstack;
618
619 if (size >= (1 << 20)) {
620 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
621 return false;
622 }
623
624 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
625 size = align(size, 0x8000);
626 size *= screen->mp_count;
627
628 size = align(size, 1 << 17);
629
630 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
631 NULL, &bo);
632 if (ret) {
633 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
634 return false;
635 }
636 nouveau_bo_ref(NULL, &screen->tls);
637 screen->tls = bo;
638 return true;
639 }
640
641 #define FAIL_SCREEN_INIT(str, err) \
642 do { \
643 NOUVEAU_ERR(str, err); \
644 goto fail; \
645 } while(0)
646
647 struct nouveau_screen *
648 nvc0_screen_create(struct nouveau_device *dev)
649 {
650 struct nvc0_screen *screen;
651 struct pipe_screen *pscreen;
652 struct nouveau_object *chan;
653 struct nouveau_pushbuf *push;
654 uint64_t value;
655 uint32_t obj_class;
656 uint32_t flags;
657 int ret;
658 unsigned i;
659
660 switch (dev->chipset & ~0xf) {
661 case 0xc0:
662 case 0xd0:
663 case 0xe0:
664 case 0xf0:
665 case 0x100:
666 case 0x110:
667 break;
668 default:
669 return NULL;
670 }
671
672 screen = CALLOC_STRUCT(nvc0_screen);
673 if (!screen)
674 return NULL;
675 pscreen = &screen->base.base;
676 pscreen->destroy = nvc0_screen_destroy;
677
678 ret = nouveau_screen_init(&screen->base, dev);
679 if (ret) {
680 nvc0_screen_destroy(pscreen);
681 return NULL;
682 }
683 chan = screen->base.channel;
684 push = screen->base.pushbuf;
685 push->user_priv = screen;
686 push->rsvd_kick = 5;
687
688 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
689 PIPE_BIND_SHADER_BUFFER |
690 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
691 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
692 screen->base.sysmem_bindings |=
693 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
694
695 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
696 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
697 screen->base.vidmem_bindings = 0;
698 }
699
700 pscreen->context_create = nvc0_create;
701 pscreen->is_format_supported = nvc0_screen_is_format_supported;
702 pscreen->get_param = nvc0_screen_get_param;
703 pscreen->get_shader_param = nvc0_screen_get_shader_param;
704 pscreen->get_paramf = nvc0_screen_get_paramf;
705 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
706 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
707
708 nvc0_screen_init_resource_functions(pscreen);
709
710 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
711 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
712
713 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
714 if (screen->base.drm->version >= 0x01000202)
715 flags |= NOUVEAU_BO_COHERENT;
716
717 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
718 if (ret)
719 goto fail;
720 nouveau_bo_map(screen->fence.bo, 0, NULL);
721 screen->fence.map = screen->fence.bo->map;
722 screen->base.fence.emit = nvc0_screen_fence_emit;
723 screen->base.fence.update = nvc0_screen_fence_update;
724
725
726 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
727 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
728 if (ret)
729 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
730
731 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
732 PUSH_DATA (push, screen->nvsw->handle);
733
734 switch (dev->chipset & ~0xf) {
735 case 0x110:
736 case 0x100:
737 case 0xf0:
738 obj_class = NVF0_P2MF_CLASS;
739 break;
740 case 0xe0:
741 obj_class = NVE4_P2MF_CLASS;
742 break;
743 default:
744 obj_class = NVC0_M2MF_CLASS;
745 break;
746 }
747 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
748 &screen->m2mf);
749 if (ret)
750 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
751
752 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
753 PUSH_DATA (push, screen->m2mf->oclass);
754 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
755 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
756 PUSH_DATA (push, 0xa0b5);
757 }
758
759 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
760 &screen->eng2d);
761 if (ret)
762 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
763
764 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
765 PUSH_DATA (push, screen->eng2d->oclass);
766 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
767 PUSH_DATA (push, 0);
768 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
769 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
770 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
771 PUSH_DATA (push, 0);
772 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
773 PUSH_DATA (push, 0);
774 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
775 PUSH_DATA (push, 0x3f);
776 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
777 PUSH_DATA (push, 1);
778 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
779 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
780
781 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
782 PUSH_DATAh(push, screen->fence.bo->offset + 16);
783 PUSH_DATA (push, screen->fence.bo->offset + 16);
784
785 switch (dev->chipset & ~0xf) {
786 case 0x110:
787 obj_class = GM107_3D_CLASS;
788 break;
789 case 0x100:
790 case 0xf0:
791 obj_class = NVF0_3D_CLASS;
792 break;
793 case 0xe0:
794 switch (dev->chipset) {
795 case 0xea:
796 obj_class = NVEA_3D_CLASS;
797 break;
798 default:
799 obj_class = NVE4_3D_CLASS;
800 break;
801 }
802 break;
803 case 0xd0:
804 obj_class = NVC8_3D_CLASS;
805 break;
806 case 0xc0:
807 default:
808 switch (dev->chipset) {
809 case 0xc8:
810 obj_class = NVC8_3D_CLASS;
811 break;
812 case 0xc1:
813 obj_class = NVC1_3D_CLASS;
814 break;
815 default:
816 obj_class = NVC0_3D_CLASS;
817 break;
818 }
819 break;
820 }
821 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
822 &screen->eng3d);
823 if (ret)
824 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
825 screen->base.class_3d = obj_class;
826
827 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
828 PUSH_DATA (push, screen->eng3d->oclass);
829
830 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
831 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
832
833 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
834 /* kill shaders after about 1 second (at 100 MHz) */
835 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
836 PUSH_DATA (push, 0x17);
837 }
838
839 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
840 screen->base.drm->version >= 0x01000101);
841 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
842 for (i = 0; i < 8; ++i)
843 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
844
845 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
846 PUSH_DATA (push, 1);
847
848 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
849 PUSH_DATA (push, 0);
850 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
851 PUSH_DATA (push, 0);
852 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
853 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
854 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
855 PUSH_DATA (push, 0);
856 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
857 PUSH_DATA (push, 1);
858 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
859 PUSH_DATA (push, 1);
860 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
861 PUSH_DATA (push, 1);
862 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
863 PUSH_DATA (push, 0);
864 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
865 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
866 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
867 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
868 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
869 } else {
870 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
871 PUSH_DATA (push, 15);
872 }
873 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
874 PUSH_DATA (push, 8); /* 128 */
875 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
876 PUSH_DATA (push, 1);
877 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
878 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
879 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
880 }
881
882 nvc0_magic_3d_init(push, screen->eng3d->oclass);
883
884 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
885 &screen->text);
886 if (ret)
887 goto fail;
888
889 /* XXX: getting a page fault at the end of the code buffer every few
890 * launches, don't use the last 256 bytes to work around them - prefetch ?
891 */
892 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
893
894 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 6 << 16, NULL,
895 &screen->uniform_bo);
896 if (ret)
897 goto fail;
898
899 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
900
901 for (i = 0; i < 5; ++i) {
902 /* TIC and TSC entries for each unit (nve4+ only) */
903 /* auxiliary constants (6 user clip planes, base instance id) */
904 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
905 PUSH_DATA (push, 1024);
906 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 10));
907 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 10));
908 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
909 PUSH_DATA (push, (15 << 4) | 1);
910 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
911 unsigned j;
912 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
913 PUSH_DATA (push, 0);
914 for (j = 0; j < 8; ++j)
915 PUSH_DATA(push, j);
916 } else {
917 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
918 PUSH_DATA (push, 0x54);
919 }
920 }
921 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
922 PUSH_DATA (push, 0);
923
924 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
925 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
926 PUSH_DATA (push, 256);
927 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
928 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
929 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
930 PUSH_DATA (push, 0);
931 PUSH_DATAf(push, 0.0f);
932 PUSH_DATAf(push, 0.0f);
933 PUSH_DATAf(push, 0.0f);
934 PUSH_DATAf(push, 0.0f);
935 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
936 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
937 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 10));
938
939 if (screen->base.drm->version >= 0x01000101) {
940 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
941 if (ret) {
942 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
943 goto fail;
944 }
945 } else {
946 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
947 value = (8 << 8) | 4;
948 else
949 value = (16 << 8) | 4;
950 }
951 screen->gpc_count = value & 0x000000ff;
952 screen->mp_count = value >> 8;
953 screen->mp_count_compute = screen->mp_count;
954
955 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
956
957 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
958 PUSH_DATAh(push, screen->text->offset);
959 PUSH_DATA (push, screen->text->offset);
960 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
961 PUSH_DATAh(push, screen->tls->offset);
962 PUSH_DATA (push, screen->tls->offset);
963 PUSH_DATA (push, screen->tls->size >> 32);
964 PUSH_DATA (push, screen->tls->size);
965 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
966 PUSH_DATA (push, 0);
967 /* Reduce likelihood of collision with real buffers by placing the hole at
968 * the top of the 4G area. This will have to be dealt with for real
969 * eventually by blocking off that area from the VM.
970 */
971 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
972 PUSH_DATA (push, 0xff << 24);
973
974 if (screen->eng3d->oclass < GM107_3D_CLASS) {
975 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
976 &screen->poly_cache);
977 if (ret)
978 goto fail;
979
980 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
981 PUSH_DATAh(push, screen->poly_cache->offset);
982 PUSH_DATA (push, screen->poly_cache->offset);
983 PUSH_DATA (push, 3);
984 }
985
986 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
987 &screen->txc);
988 if (ret)
989 goto fail;
990
991 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
992 PUSH_DATAh(push, screen->txc->offset);
993 PUSH_DATA (push, screen->txc->offset);
994 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
995
996 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
997 PUSH_DATAh(push, screen->txc->offset + 65536);
998 PUSH_DATA (push, screen->txc->offset + 65536);
999 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1000
1001 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1002 PUSH_DATA (push, 0);
1003 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1004 PUSH_DATA (push, 0);
1005 PUSH_DATA (push, 0);
1006 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1007 PUSH_DATA (push, 0x3f);
1008
1009 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1010 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1011 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1012 for (i = 0; i < 8 * 2; ++i)
1013 PUSH_DATA(push, 0);
1014 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1015 PUSH_DATA (push, 0);
1016 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1017 PUSH_DATA (push, 0);
1018
1019 /* neither scissors, viewport nor stencil mask should affect clears */
1020 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1021 PUSH_DATA (push, 0);
1022
1023 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1024 PUSH_DATA (push, 1);
1025 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1026 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1027 PUSH_DATAf(push, 0.0f);
1028 PUSH_DATAf(push, 1.0f);
1029 }
1030 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1031 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1032
1033 /* We use scissors instead of exact view volume clipping,
1034 * so they're always enabled.
1035 */
1036 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1037 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1038 PUSH_DATA (push, 1);
1039 PUSH_DATA (push, 8192 << 16);
1040 PUSH_DATA (push, 8192 << 16);
1041 }
1042
1043 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1044
1045 i = 0;
1046 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1047 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1048 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1049 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1050 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1051 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1052 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1053 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1054 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1055 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1056 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1057 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1058
1059 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1060 PUSH_DATA (push, 1);
1061 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1062 PUSH_DATA (push, 1);
1063 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1064 PUSH_DATA (push, 0x40);
1065 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1066 PUSH_DATA (push, 0);
1067 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1068 PUSH_DATA (push, 0x30);
1069 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1070 PUSH_DATA (push, 3);
1071 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1072 PUSH_DATA (push, 0x20);
1073 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1074 PUSH_DATA (push, 0x00);
1075 screen->save_state.patch_vertices = 3;
1076
1077 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1078 PUSH_DATA (push, 0);
1079 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1080 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1081
1082 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1083
1084 if (nvc0_screen_init_compute(screen))
1085 goto fail;
1086
1087 PUSH_KICK (push);
1088
1089 screen->tic.entries = CALLOC(4096, sizeof(void *));
1090 screen->tsc.entries = screen->tic.entries + 2048;
1091
1092 if (!nvc0_blitter_create(screen))
1093 goto fail;
1094
1095 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1096
1097 return &screen->base;
1098
1099 fail:
1100 screen->base.base.context_create = NULL;
1101 return &screen->base;
1102 }
1103
1104 int
1105 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1106 {
1107 int i = screen->tic.next;
1108
1109 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1110 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1111
1112 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1113
1114 if (screen->tic.entries[i])
1115 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1116
1117 screen->tic.entries[i] = entry;
1118 return i;
1119 }
1120
1121 int
1122 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1123 {
1124 int i = screen->tsc.next;
1125
1126 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1127 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1128
1129 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1130
1131 if (screen->tsc.entries[i])
1132 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1133
1134 screen->tsc.entries[i] = entry;
1135 return i;
1136 }